1/* SPDX-License-Identifier: GPL-2.0+ */ 2/************************************************************************ 3 * Copyright 2003 Digi International (www.digi.com) 4 * 5 * Copyright (C) 2004 IBM Corporation. All rights reserved. 6 * 7 * Contact Information: 8 * Scott H Kilau <Scott_Kilau@digi.com> 9 * Wendy Xiong <wendyx@us.ibm.com> 10 * 11 ***********************************************************************/ 12 13#ifndef __JSM_DRIVER_H 14#define __JSM_DRIVER_H 15 16#include <linux/kernel.h> 17#include <linux/types.h> /* To pick up the varions Linux types */ 18#include <linux/tty.h> 19#include <linux/serial_core.h> 20#include <linux/device.h> 21 22/* 23 * Debugging levels can be set using debug insmod variable 24 * They can also be compiled out completely. 25 */ 26enum { 27 DBG_INIT = 0x01, 28 DBG_BASIC = 0x02, 29 DBG_CORE = 0x04, 30 DBG_OPEN = 0x08, 31 DBG_CLOSE = 0x10, 32 DBG_READ = 0x20, 33 DBG_WRITE = 0x40, 34 DBG_IOCTL = 0x80, 35 DBG_PROC = 0x100, 36 DBG_PARAM = 0x200, 37 DBG_PSCAN = 0x400, 38 DBG_EVENT = 0x800, 39 DBG_DRAIN = 0x1000, 40 DBG_MSIGS = 0x2000, 41 DBG_MGMT = 0x4000, 42 DBG_INTR = 0x8000, 43 DBG_CARR = 0x10000, 44}; 45 46#define jsm_dbg(nlevel, pdev, fmt, ...) \ 47do { \ 48 if (DBG_##nlevel & jsm_debug) \ 49 dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \ 50} while (0) 51 52#define MAXLINES 256 53#define MAXPORTS 8 54#define MAX_STOPS_SENT 5 55 56/* Board ids */ 57#define PCI_DEVICE_ID_CLASSIC_4 0x0028 58#define PCI_DEVICE_ID_CLASSIC_8 0x0029 59#define PCI_DEVICE_ID_CLASSIC_4_422 0x00D0 60#define PCI_DEVICE_ID_CLASSIC_8_422 0x00D1 61#define PCI_DEVICE_ID_NEO_4 0x00B0 62#define PCI_DEVICE_ID_NEO_1_422 0x00CC 63#define PCI_DEVICE_ID_NEO_1_422_485 0x00CD 64#define PCI_DEVICE_ID_NEO_2_422_485 0x00CE 65#define PCIE_DEVICE_ID_NEO_8 0x00F0 66#define PCIE_DEVICE_ID_NEO_4 0x00F1 67#define PCIE_DEVICE_ID_NEO_4RJ45 0x00F2 68#define PCIE_DEVICE_ID_NEO_8RJ45 0x00F3 69 70/* Board type definitions */ 71 72#define T_NEO 0000 73#define T_CLASSIC 0001 74#define T_PCIBUS 0400 75 76/* Board State Definitions */ 77 78#define BD_RUNNING 0x0 79#define BD_REASON 0x7f 80#define BD_NOTFOUND 0x1 81#define BD_NOIOPORT 0x2 82#define BD_NOMEM 0x3 83#define BD_NOBIOS 0x4 84#define BD_NOFEP 0x5 85#define BD_FAILED 0x6 86#define BD_ALLOCATED 0x7 87#define BD_TRIBOOT 0x8 88#define BD_BADKME 0x80 89 90 91/* 4 extra for alignment play space */ 92#define WRITEBUFLEN ((4096) + 4) 93 94#define JSM_VERSION "jsm: 1.2-1-INKERNEL" 95#define JSM_PARTNUM "40002438_A-INKERNEL" 96 97struct jsm_board; 98struct jsm_channel; 99 100/************************************************************************ 101 * Per board operations structure * 102 ************************************************************************/ 103struct board_ops { 104 irq_handler_t intr; 105 void (*uart_init)(struct jsm_channel *ch); 106 void (*uart_off)(struct jsm_channel *ch); 107 void (*param)(struct jsm_channel *ch); 108 void (*assert_modem_signals)(struct jsm_channel *ch); 109 void (*flush_uart_write)(struct jsm_channel *ch); 110 void (*flush_uart_read)(struct jsm_channel *ch); 111 void (*disable_receiver)(struct jsm_channel *ch); 112 void (*enable_receiver)(struct jsm_channel *ch); 113 void (*send_break)(struct jsm_channel *ch); 114 void (*clear_break)(struct jsm_channel *ch); 115 void (*send_start_character)(struct jsm_channel *ch); 116 void (*send_stop_character)(struct jsm_channel *ch); 117 void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch); 118}; 119 120 121/* 122 * Per-board information 123 */ 124struct jsm_board 125{ 126 int boardnum; /* Board number: 0-32 */ 127 128 u8 rev; /* PCI revision ID */ 129 struct pci_dev *pci_dev; 130 u32 maxports; /* MAX ports this board can handle */ 131 132 spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and 133 * the interrupt routine from each other. 134 */ 135 136 u32 nasync; /* Number of ports on card */ 137 138 u32 irq; /* Interrupt request number */ 139 140 u64 membase; /* Start of base memory of the card */ 141 u64 membase_end; /* End of base memory of the card */ 142 143 u8 __iomem *re_map_membase;/* Remapped memory of the card */ 144 145 u64 iobase; /* Start of io base of the card */ 146 u64 iobase_end; /* End of io base of the card */ 147 148 u32 bd_uart_offset; /* Space between each UART */ 149 150 struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */ 151 152 u32 bd_dividend; /* Board/UARTs specific dividend */ 153 154 struct board_ops *bd_ops; 155}; 156 157/************************************************************************ 158 * Device flag definitions for ch_flags. 159 ************************************************************************/ 160#define CH_PRON 0x0001 /* Printer on string */ 161#define CH_STOP 0x0002 /* Output is stopped */ 162#define CH_STOPI 0x0004 /* Input is stopped */ 163#define CH_CD 0x0008 /* Carrier is present */ 164#define CH_FCAR 0x0010 /* Carrier forced on */ 165#define CH_HANGUP 0x0020 /* Hangup received */ 166 167#define CH_RECEIVER_OFF 0x0040 /* Receiver is off */ 168#define CH_OPENING 0x0080 /* Port in fragile open state */ 169#define CH_CLOSING 0x0100 /* Port in fragile close state */ 170#define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */ 171#define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */ 172#define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */ 173#define CH_BREAK_SENDING 0x1000 /* Break is being sent */ 174#define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */ 175#define CH_BAUD0 0x08000 /* Used for checking B0 transitions */ 176 177/* Our Read/Error queue sizes */ 178#define RQUEUEMASK 0x1FFF /* 8 K - 1 */ 179#define EQUEUEMASK 0x1FFF /* 8 K - 1 */ 180#define RQUEUESIZE (RQUEUEMASK + 1) 181#define EQUEUESIZE RQUEUESIZE 182 183 184/************************************************************************ 185 * Channel information structure. 186 ************************************************************************/ 187struct jsm_channel { 188 struct uart_port uart_port; 189 struct jsm_board *ch_bd; /* Board structure pointer */ 190 191 spinlock_t ch_lock; /* provide for serialization */ 192 wait_queue_head_t ch_flags_wait; 193 194 u32 ch_portnum; /* Port number, 0 offset. */ 195 u32 ch_open_count; /* open count */ 196 u32 ch_flags; /* Channel flags */ 197 198 u64 ch_close_delay; /* How long we should drop RTS/DTR for */ 199 200 tcflag_t ch_c_iflag; /* channel iflags */ 201 tcflag_t ch_c_cflag; /* channel cflags */ 202 tcflag_t ch_c_oflag; /* channel oflags */ 203 tcflag_t ch_c_lflag; /* channel lflags */ 204 u8 ch_stopc; /* Stop character */ 205 u8 ch_startc; /* Start character */ 206 207 u8 ch_mostat; /* FEP output modem status */ 208 u8 ch_mistat; /* FEP input modem status */ 209 210 /* Pointers to the "mapped" UART structs */ 211 struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */ 212 struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */ 213 214 u8 ch_cached_lsr; /* Cached value of the LSR register */ 215 216 u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */ 217 u16 ch_r_head; /* Head location of the read queue */ 218 u16 ch_r_tail; /* Tail location of the read queue */ 219 220 u8 *ch_equeue; /* Our error queue buffer - malloc'ed */ 221 u16 ch_e_head; /* Head location of the error queue */ 222 u16 ch_e_tail; /* Tail location of the error queue */ 223 224 u64 ch_rxcount; /* total of data received so far */ 225 u64 ch_txcount; /* total of data transmitted so far */ 226 227 u8 ch_r_tlevel; /* Receive Trigger level */ 228 u8 ch_t_tlevel; /* Transmit Trigger level */ 229 230 u8 ch_r_watermark; /* Receive Watermark */ 231 232 233 u32 ch_stops_sent; /* How many times I have sent a stop character 234 * to try to stop the other guy sending. 235 */ 236 u64 ch_err_parity; /* Count of parity errors on channel */ 237 u64 ch_err_frame; /* Count of framing errors on channel */ 238 u64 ch_err_break; /* Count of breaks on channel */ 239 u64 ch_err_overrun; /* Count of overruns on channel */ 240 241 u64 ch_xon_sends; /* Count of xons transmitted */ 242 u64 ch_xoff_sends; /* Count of xoffs transmitted */ 243}; 244 245/************************************************************************ 246 * Per channel/port Classic UART structures * 247 ************************************************************************ 248 * Base Structure Entries Usage Meanings to Host * 249 * * 250 * W = read write R = read only * 251 * U = Unused. * 252 ************************************************************************/ 253 254struct cls_uart_struct { 255 u8 txrx; /* WR RHR/THR - Holding Reg */ 256 u8 ier; /* WR IER - Interrupt Enable Reg */ 257 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/ 258 u8 lcr; /* WR LCR - Line Control Reg */ 259 u8 mcr; /* WR MCR - Modem Control Reg */ 260 u8 lsr; /* WR LSR - Line Status Reg */ 261 u8 msr; /* WR MSR - Modem Status Reg */ 262 u8 spr; /* WR SPR - Scratch Pad Reg */ 263}; 264 265/* Where to read the interrupt register (8bits) */ 266#define UART_CLASSIC_POLL_ADDR_OFFSET 0x40 267 268#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF 269 270#define UART_16654_FCR_TXTRIGGER_8 0x0 271#define UART_16654_FCR_TXTRIGGER_16 0x10 272#define UART_16654_FCR_TXTRIGGER_32 0x20 273#define UART_16654_FCR_TXTRIGGER_56 0x30 274 275#define UART_16654_FCR_RXTRIGGER_8 0x0 276#define UART_16654_FCR_RXTRIGGER_16 0x40 277#define UART_16654_FCR_RXTRIGGER_56 0x80 278#define UART_16654_FCR_RXTRIGGER_60 0xC0 279 280#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */ 281#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 282 283/* 284 * These are the EXTENDED definitions for the Exar 654's Interrupt 285 * Enable Register. 286 */ 287#define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */ 288#define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 289#define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 290#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 291#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 292 293#define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 294#define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 295 296#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 297#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 298#define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 299 300/************************************************************************ 301 * Per channel/port NEO UART structure * 302 ************************************************************************ 303 * Base Structure Entries Usage Meanings to Host * 304 * * 305 * W = read write R = read only * 306 * U = Unused. * 307 ************************************************************************/ 308 309struct neo_uart_struct { 310 u8 txrx; /* WR RHR/THR - Holding Reg */ 311 u8 ier; /* WR IER - Interrupt Enable Reg */ 312 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ 313 u8 lcr; /* WR LCR - Line Control Reg */ 314 u8 mcr; /* WR MCR - Modem Control Reg */ 315 u8 lsr; /* WR LSR - Line Status Reg */ 316 u8 msr; /* WR MSR - Modem Status Reg */ 317 u8 spr; /* WR SPR - Scratch Pad Reg */ 318 u8 fctr; /* WR FCTR - Feature Control Reg */ 319 u8 efr; /* WR EFR - Enhanced Function Reg */ 320 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */ 321 u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */ 322 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */ 323 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */ 324 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */ 325 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */ 326 327 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */ 328 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */ 329 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */ 330 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */ 331}; 332 333/* Where to read the extended interrupt register (32bits instead of 8bits) */ 334#define UART_17158_POLL_ADDR_OFFSET 0x80 335 336/* 337 * These are the redefinitions for the FCTR on the XR17C158, since 338 * Exar made them different than their earlier design. (XR16C854) 339 */ 340 341/* These are only applicable when table D is selected */ 342#define UART_17158_FCTR_RTS_NODELAY 0x00 343#define UART_17158_FCTR_RTS_4DELAY 0x01 344#define UART_17158_FCTR_RTS_6DELAY 0x02 345#define UART_17158_FCTR_RTS_8DELAY 0x03 346#define UART_17158_FCTR_RTS_12DELAY 0x12 347#define UART_17158_FCTR_RTS_16DELAY 0x05 348#define UART_17158_FCTR_RTS_20DELAY 0x13 349#define UART_17158_FCTR_RTS_24DELAY 0x06 350#define UART_17158_FCTR_RTS_28DELAY 0x14 351#define UART_17158_FCTR_RTS_32DELAY 0x07 352#define UART_17158_FCTR_RTS_36DELAY 0x16 353#define UART_17158_FCTR_RTS_40DELAY 0x08 354#define UART_17158_FCTR_RTS_44DELAY 0x09 355#define UART_17158_FCTR_RTS_48DELAY 0x10 356#define UART_17158_FCTR_RTS_52DELAY 0x11 357 358#define UART_17158_FCTR_RTS_IRDA 0x10 359#define UART_17158_FCTR_RS485 0x20 360#define UART_17158_FCTR_TRGA 0x00 361#define UART_17158_FCTR_TRGB 0x40 362#define UART_17158_FCTR_TRGC 0x80 363#define UART_17158_FCTR_TRGD 0xC0 364 365/* 17158 trigger table selects.. */ 366#define UART_17158_FCTR_BIT6 0x40 367#define UART_17158_FCTR_BIT7 0x80 368 369/* 17158 TX/RX memmapped buffer offsets */ 370#define UART_17158_RX_FIFOSIZE 64 371#define UART_17158_TX_FIFOSIZE 64 372 373/* 17158 Extended IIR's */ 374#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 375#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ 376#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ 377#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ 378 379/* 380 * These are the extended interrupts that get sent 381 * back to us from the UART's 32bit interrupt register 382 */ 383#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */ 384#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */ 385#define UART_17158_TXRDY 0x3 /* TX Ready */ 386#define UART_17158_MSR 0x4 /* Modem State Change */ 387#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ 388#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ 389 390/* 391 * These are the EXTENDED definitions for the 17C158's Interrupt 392 * Enable Register. 393 */ 394#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */ 395#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 396#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 397#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 398#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 399 400#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 401#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 402 403#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */ 404#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 405#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 406#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 407 408#define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI" 409#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator" 410#define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI" 411#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator" 412#define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM" 413 414/* 415 * Our Global Variables. 416 */ 417extern struct uart_driver jsm_uart_driver; 418extern struct board_ops jsm_neo_ops; 419extern struct board_ops jsm_cls_ops; 420extern int jsm_debug; 421 422/************************************************************************* 423 * 424 * Prototypes for non-static functions used in more than one module 425 * 426 *************************************************************************/ 427int jsm_tty_init(struct jsm_board *); 428int jsm_uart_port_init(struct jsm_board *); 429int jsm_remove_uart_port(struct jsm_board *); 430void jsm_input(struct jsm_channel *ch); 431void jsm_check_queue_flow_control(struct jsm_channel *ch); 432 433#endif 434