1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Driver for Realtek PCI-Express card reader 4 * 5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 * 7 * Author: 8 * Wei WANG (wei_wang@realsil.com.cn) 9 * Micky Ching (micky_ching@realsil.com.cn) 10 */ 11 12#ifndef __REALTEK_RTSX_CARD_H 13#define __REALTEK_RTSX_CARD_H 14 15#include "rtsx.h" 16#include "rtsx_chip.h" 17#include "rtsx_transport.h" 18#include "sd.h" 19 20#define SSC_POWER_DOWN 0x01 21#define SD_OC_POWER_DOWN 0x02 22#define MS_OC_POWER_DOWN 0x04 23#define ALL_POWER_DOWN 0x07 24#define OC_POWER_DOWN 0x06 25 26#define PMOS_STRG_MASK 0x10 27#define PMOS_STRG_800mA 0x10 28#define PMOS_STRG_400mA 0x00 29 30#define POWER_OFF 0x03 31#define PARTIAL_POWER_ON 0x01 32#define POWER_ON 0x00 33 34#define MS_POWER_OFF 0x0C 35#define MS_PARTIAL_POWER_ON 0x04 36#define MS_POWER_ON 0x00 37#define MS_POWER_MASK 0x0C 38 39#define SD_POWER_OFF 0x03 40#define SD_PARTIAL_POWER_ON 0x01 41#define SD_POWER_ON 0x00 42#define SD_POWER_MASK 0x03 43 44#define XD_OUTPUT_EN 0x02 45#define SD_OUTPUT_EN 0x04 46#define MS_OUTPUT_EN 0x08 47#define SPI_OUTPUT_EN 0x10 48 49#define CLK_LOW_FREQ 0x01 50 51#define CLK_DIV_1 0x01 52#define CLK_DIV_2 0x02 53#define CLK_DIV_4 0x03 54#define CLK_DIV_8 0x04 55 56#define SSC_80 0 57#define SSC_100 1 58#define SSC_120 2 59#define SSC_150 3 60#define SSC_200 4 61 62#define XD_CLK_EN 0x02 63#define SD_CLK_EN 0x04 64#define MS_CLK_EN 0x08 65#define SPI_CLK_EN 0x10 66 67#define XD_MOD_SEL 1 68#define SD_MOD_SEL 2 69#define MS_MOD_SEL 3 70#define SPI_MOD_SEL 4 71 72#define CHANGE_CLK 0x01 73 74#define SD_CRC7_ERR 0x80 75#define SD_CRC16_ERR 0x40 76#define SD_CRC_WRITE_ERR 0x20 77#define SD_CRC_WRITE_ERR_MASK 0x1C 78#define GET_CRC_TIME_OUT 0x02 79#define SD_TUNING_COMPARE_ERR 0x01 80 81#define SD_RSP_80CLK_TIMEOUT 0x01 82 83#define SD_CLK_TOGGLE_EN 0x80 84#define SD_CLK_FORCE_STOP 0x40 85#define SD_DAT3_STATUS 0x10 86#define SD_DAT2_STATUS 0x08 87#define SD_DAT1_STATUS 0x04 88#define SD_DAT0_STATUS 0x02 89#define SD_CMD_STATUS 0x01 90 91#define SD_IO_USING_1V8 0x80 92#define SD_IO_USING_3V3 0x7F 93#define TYPE_A_DRIVING 0x00 94#define TYPE_B_DRIVING 0x01 95#define TYPE_C_DRIVING 0x02 96#define TYPE_D_DRIVING 0x03 97 98#define DDR_FIX_RX_DAT 0x00 99#define DDR_VAR_RX_DAT 0x80 100#define DDR_FIX_RX_DAT_EDGE 0x00 101#define DDR_FIX_RX_DAT_14_DELAY 0x40 102#define DDR_FIX_RX_CMD 0x00 103#define DDR_VAR_RX_CMD 0x20 104#define DDR_FIX_RX_CMD_POS_EDGE 0x00 105#define DDR_FIX_RX_CMD_14_DELAY 0x10 106#define SD20_RX_POS_EDGE 0x00 107#define SD20_RX_14_DELAY 0x08 108#define SD20_RX_SEL_MASK 0x08 109 110#define DDR_FIX_TX_CMD_DAT 0x00 111#define DDR_VAR_TX_CMD_DAT 0x80 112#define DDR_FIX_TX_DAT_14_TSU 0x00 113#define DDR_FIX_TX_DAT_12_TSU 0x40 114#define DDR_FIX_TX_CMD_NEG_EDGE 0x00 115#define DDR_FIX_TX_CMD_14_AHEAD 0x20 116#define SD20_TX_NEG_EDGE 0x00 117#define SD20_TX_14_AHEAD 0x10 118#define SD20_TX_SEL_MASK 0x10 119#define DDR_VAR_SDCLK_POL_SWAP 0x01 120 121#define SD_TRANSFER_START 0x80 122#define SD_TRANSFER_END 0x40 123#define SD_STAT_IDLE 0x20 124#define SD_TRANSFER_ERR 0x10 125#define SD_TM_NORMAL_WRITE 0x00 126#define SD_TM_AUTO_WRITE_3 0x01 127#define SD_TM_AUTO_WRITE_4 0x02 128#define SD_TM_AUTO_READ_3 0x05 129#define SD_TM_AUTO_READ_4 0x06 130#define SD_TM_CMD_RSP 0x08 131#define SD_TM_AUTO_WRITE_1 0x09 132#define SD_TM_AUTO_WRITE_2 0x0A 133#define SD_TM_NORMAL_READ 0x0C 134#define SD_TM_AUTO_READ_1 0x0D 135#define SD_TM_AUTO_READ_2 0x0E 136#define SD_TM_AUTO_TUNING 0x0F 137 138#define PHASE_CHANGE 0x80 139#define PHASE_NOT_RESET 0x40 140 141#define DCMPS_CHANGE 0x80 142#define DCMPS_CHANGE_DONE 0x40 143#define DCMPS_ERROR 0x20 144#define DCMPS_CURRENT_PHASE 0x1F 145 146#define SD_CLK_DIVIDE_0 0x00 147#define SD_CLK_DIVIDE_256 0xC0 148#define SD_CLK_DIVIDE_128 0x80 149#define SD_BUS_WIDTH_1 0x00 150#define SD_BUS_WIDTH_4 0x01 151#define SD_BUS_WIDTH_8 0x02 152#define SD_ASYNC_FIFO_NOT_RST 0x10 153#define SD_20_MODE 0x00 154#define SD_DDR_MODE 0x04 155#define SD_30_MODE 0x08 156 157#define SD_CLK_DIVIDE_MASK 0xC0 158 159#define SD_CMD_IDLE 0x80 160 161#define SD_DATA_IDLE 0x80 162 163#define DCM_RESET 0x08 164#define DCM_LOCKED 0x04 165#define DCM_208M 0x00 166#define DCM_TX 0x01 167#define DCM_RX 0x02 168 169#define DRP_START 0x80 170#define DRP_DONE 0x40 171 172#define DRP_WRITE 0x80 173#define DRP_READ 0x00 174#define DCM_WRITE_ADDRESS_50 0x50 175#define DCM_WRITE_ADDRESS_51 0x51 176#define DCM_READ_ADDRESS_00 0x00 177#define DCM_READ_ADDRESS_51 0x51 178 179#define SD_CALCULATE_CRC7 0x00 180#define SD_NO_CALCULATE_CRC7 0x80 181#define SD_CHECK_CRC16 0x00 182#define SD_NO_CHECK_CRC16 0x40 183#define SD_NO_CHECK_WAIT_CRC_TO 0x20 184#define SD_WAIT_BUSY_END 0x08 185#define SD_NO_WAIT_BUSY_END 0x00 186#define SD_CHECK_CRC7 0x00 187#define SD_NO_CHECK_CRC7 0x04 188#define SD_RSP_LEN_0 0x00 189#define SD_RSP_LEN_6 0x01 190#define SD_RSP_LEN_17 0x02 191#define SD_RSP_TYPE_R0 0x04 192#define SD_RSP_TYPE_R1 0x01 193#define SD_RSP_TYPE_R1b 0x09 194#define SD_RSP_TYPE_R2 0x02 195#define SD_RSP_TYPE_R3 0x05 196#define SD_RSP_TYPE_R4 0x05 197#define SD_RSP_TYPE_R5 0x01 198#define SD_RSP_TYPE_R6 0x01 199#define SD_RSP_TYPE_R7 0x01 200 201#define SD_RSP_80CLK_TIMEOUT_EN 0x01 202 203#define SAMPLE_TIME_RISING 0x00 204#define SAMPLE_TIME_FALLING 0x80 205#define PUSH_TIME_DEFAULT 0x00 206#define PUSH_TIME_ODD 0x40 207#define NO_EXTEND_TOGGLE 0x00 208#define EXTEND_TOGGLE_CHK 0x20 209#define MS_BUS_WIDTH_1 0x00 210#define MS_BUS_WIDTH_4 0x10 211#define MS_BUS_WIDTH_8 0x18 212#define MS_2K_SECTOR_MODE 0x04 213#define MS_512_SECTOR_MODE 0x00 214#define MS_TOGGLE_TIMEOUT_EN 0x00 215#define MS_TOGGLE_TIMEOUT_DISEN 0x01 216#define MS_NO_CHECK_INT 0x02 217 218#define WAIT_INT 0x80 219#define NO_WAIT_INT 0x00 220#define NO_AUTO_READ_INT_REG 0x00 221#define AUTO_READ_INT_REG 0x40 222#define MS_CRC16_ERR 0x20 223#define MS_RDY_TIMEOUT 0x10 224#define MS_INT_CMDNK 0x08 225#define MS_INT_BREQ 0x04 226#define MS_INT_ERR 0x02 227#define MS_INT_CED 0x01 228 229#define MS_TRANSFER_START 0x80 230#define MS_TRANSFER_END 0x40 231#define MS_TRANSFER_ERR 0x20 232#define MS_BS_STATE 0x10 233#define MS_TM_READ_BYTES 0x00 234#define MS_TM_NORMAL_READ 0x01 235#define MS_TM_WRITE_BYTES 0x04 236#define MS_TM_NORMAL_WRITE 0x05 237#define MS_TM_AUTO_READ 0x08 238#define MS_TM_AUTO_WRITE 0x0C 239 240#define CARD_SHARE_MASK 0x0F 241#define CARD_SHARE_MULTI_LUN 0x00 242#define CARD_SHARE_NORMAL 0x00 243#define CARD_SHARE_48_XD 0x02 244#define CARD_SHARE_48_SD 0x04 245#define CARD_SHARE_48_MS 0x08 246#define CARD_SHARE_BAROSSA_XD 0x00 247#define CARD_SHARE_BAROSSA_SD 0x01 248#define CARD_SHARE_BAROSSA_MS 0x02 249 250#define MS_DRIVE_8 0x00 251#define MS_DRIVE_4 0x40 252#define MS_DRIVE_12 0x80 253#define SD_DRIVE_8 0x00 254#define SD_DRIVE_4 0x10 255#define SD_DRIVE_12 0x20 256#define XD_DRIVE_8 0x00 257#define XD_DRIVE_4 0x04 258#define XD_DRIVE_12 0x08 259 260#define SPI_STOP 0x01 261#define XD_STOP 0x02 262#define SD_STOP 0x04 263#define MS_STOP 0x08 264#define SPI_CLR_ERR 0x10 265#define XD_CLR_ERR 0x20 266#define SD_CLR_ERR 0x40 267#define MS_CLR_ERR 0x80 268 269#define CRC_FIX_CLK (0x00 << 0) 270#define CRC_VAR_CLK0 (0x01 << 0) 271#define CRC_VAR_CLK1 (0x02 << 0) 272#define SD30_FIX_CLK (0x00 << 2) 273#define SD30_VAR_CLK0 (0x01 << 2) 274#define SD30_VAR_CLK1 (0x02 << 2) 275#define SAMPLE_FIX_CLK (0x00 << 4) 276#define SAMPLE_VAR_CLK0 (0x01 << 4) 277#define SAMPLE_VAR_CLK1 (0x02 << 4) 278 279#define SDIO_VER_20 0x80 280#define SDIO_VER_10 0x00 281#define SDIO_VER_CHG 0x40 282#define SDIO_BUS_AUTO_SWITCH 0x10 283 284#define PINGPONG_BUFFER 0x01 285#define RING_BUFFER 0x00 286 287#define RB_FLUSH 0x80 288 289#define DMA_DONE_INT_EN 0x80 290#define SUSPEND_INT_EN 0x40 291#define LINK_RDY_INT_EN 0x20 292#define LINK_DOWN_INT_EN 0x10 293 294#define DMA_DONE_INT 0x80 295#define SUSPEND_INT 0x40 296#define LINK_RDY_INT 0x20 297#define LINK_DOWN_INT 0x10 298 299#define MRD_ERR_INT_EN 0x40 300#define MWR_ERR_INT_EN 0x20 301#define SCSI_CMD_INT_EN 0x10 302#define TLP_RCV_INT_EN 0x08 303#define TLP_TRSMT_INT_EN 0x04 304#define MRD_COMPLETE_INT_EN 0x02 305#define MWR_COMPLETE_INT_EN 0x01 306 307#define MRD_ERR_INT 0x40 308#define MWR_ERR_INT 0x20 309#define SCSI_CMD_INT 0x10 310#define TLP_RX_INT 0x08 311#define TLP_TX_INT 0x04 312#define MRD_COMPLETE_INT 0x02 313#define MWR_COMPLETE_INT 0x01 314 315#define MSG_RX_INT_EN 0x08 316#define MRD_RX_INT_EN 0x04 317#define MWR_RX_INT_EN 0x02 318#define CPLD_RX_INT_EN 0x01 319 320#define MSG_RX_INT 0x08 321#define MRD_RX_INT 0x04 322#define MWR_RX_INT 0x02 323#define CPLD_RX_INT 0x01 324 325#define MSG_TX_INT_EN 0x08 326#define MRD_TX_INT_EN 0x04 327#define MWR_TX_INT_EN 0x02 328#define CPLD_TX_INT_EN 0x01 329 330#define MSG_TX_INT 0x08 331#define MRD_TX_INT 0x04 332#define MWR_TX_INT 0x02 333#define CPLD_TX_INT 0x01 334 335#define DMA_RST 0x80 336#define DMA_BUSY 0x04 337#define DMA_DIR_TO_CARD 0x00 338#define DMA_DIR_FROM_CARD 0x02 339#define DMA_EN 0x01 340#define DMA_128 (0 << 4) 341#define DMA_256 (1 << 4) 342#define DMA_512 (2 << 4) 343#define DMA_1024 (3 << 4) 344#define DMA_PACK_SIZE_MASK 0x30 345 346#define XD_PWR_OFF_DELAY0 0x00 347#define XD_PWR_OFF_DELAY1 0x02 348#define XD_PWR_OFF_DELAY2 0x04 349#define XD_PWR_OFF_DELAY3 0x06 350#define XD_AUTO_PWR_OFF_EN 0xF7 351#define XD_NO_AUTO_PWR_OFF 0x08 352 353#define XD_TIME_RWN_1 0x00 354#define XD_TIME_RWN_STEP 0x20 355#define XD_TIME_RW_1 0x00 356#define XD_TIME_RW_STEP 0x04 357#define XD_TIME_SETUP_1 0x00 358#define XD_TIME_SETUP_STEP 0x01 359 360#define XD_ECC2_UNCORRECTABLE 0x80 361#define XD_ECC2_ERROR 0x40 362#define XD_ECC1_UNCORRECTABLE 0x20 363#define XD_ECC1_ERROR 0x10 364#define XD_RDY 0x04 365#define XD_CE_EN 0xFD 366#define XD_CE_DISEN 0x02 367#define XD_WP_EN 0xFE 368#define XD_WP_DISEN 0x01 369 370#define XD_TRANSFER_START 0x80 371#define XD_TRANSFER_END 0x40 372#define XD_PPB_EMPTY 0x20 373#define XD_RESET 0x00 374#define XD_ERASE 0x01 375#define XD_READ_STATUS 0x02 376#define XD_READ_ID 0x03 377#define XD_READ_REDUNDANT 0x04 378#define XD_READ_PAGES 0x05 379#define XD_SET_CMD 0x06 380#define XD_NORMAL_READ 0x07 381#define XD_WRITE_PAGES 0x08 382#define XD_NORMAL_WRITE 0x09 383#define XD_WRITE_REDUNDANT 0x0A 384#define XD_SET_ADDR 0x0B 385 386#define XD_PPB_TO_SIE 0x80 387#define XD_TO_PPB_ONLY 0x00 388#define XD_BA_TRANSFORM 0x40 389#define XD_BA_NO_TRANSFORM 0x00 390#define XD_NO_CALC_ECC 0x20 391#define XD_CALC_ECC 0x00 392#define XD_IGNORE_ECC 0x10 393#define XD_CHECK_ECC 0x00 394#define XD_DIRECT_TO_RB 0x08 395#define XD_ADDR_LENGTH_0 0x00 396#define XD_ADDR_LENGTH_1 0x01 397#define XD_ADDR_LENGTH_2 0x02 398#define XD_ADDR_LENGTH_3 0x03 399#define XD_ADDR_LENGTH_4 0x04 400 401#define XD_GPG 0xFF 402#define XD_BPG 0x00 403 404#define XD_GBLK 0xFF 405#define XD_LATER_BBLK 0xF0 406 407#define XD_ECC2_ALL1 0x80 408#define XD_ECC1_ALL1 0x40 409#define XD_BA2_ALL0 0x20 410#define XD_BA1_ALL0 0x10 411#define XD_BA1_BA2_EQL 0x04 412#define XD_BA2_VALID 0x02 413#define XD_BA1_VALID 0x01 414 415#define XD_PGSTS_ZEROBIT_OVER4 0x00 416#define XD_PGSTS_NOT_FF 0x02 417#define XD_AUTO_CHK_DATA_STATUS 0x01 418 419#define RSTB_MODE_DETECT 0x80 420#define MODE_OUT_VLD 0x40 421#define MODE_OUT_0_NONE 0x00 422#define MODE_OUT_10_NONE 0x04 423#define MODE_OUT_10_47 0x05 424#define MODE_OUT_10_180 0x06 425#define MODE_OUT_10_680 0x07 426#define MODE_OUT_16_NONE 0x08 427#define MODE_OUT_16_47 0x09 428#define MODE_OUT_16_180 0x0A 429#define MODE_OUT_16_680 0x0B 430#define MODE_OUT_NONE_NONE 0x0C 431#define MODE_OUT_NONE_47 0x0D 432#define MODE_OUT_NONE_180 0x0E 433#define MODE_OUT_NONE_680 0x0F 434 435#define CARD_OC_INT_EN 0x20 436#define CARD_DETECT_EN 0x08 437 438#define MS_DETECT_EN 0x80 439#define MS_OCP_INT_EN 0x40 440#define MS_OCP_INT_CLR 0x20 441#define MS_OC_CLR 0x10 442#define SD_DETECT_EN 0x08 443#define SD_OCP_INT_EN 0x04 444#define SD_OCP_INT_CLR 0x02 445#define SD_OC_CLR 0x01 446 447#define CARD_OCP_DETECT 0x80 448#define CARD_OC_NOW 0x08 449#define CARD_OC_EVER 0x04 450 451#define MS_OCP_DETECT 0x80 452#define MS_OC_NOW 0x40 453#define MS_OC_EVER 0x20 454#define SD_OCP_DETECT 0x08 455#define SD_OC_NOW 0x04 456#define SD_OC_EVER 0x02 457 458#define CARD_OC_INT_CLR 0x08 459#define CARD_OC_CLR 0x02 460 461#define SD_OCP_GLITCH_MASK 0x07 462#define SD_OCP_GLITCH_6_4 0x00 463#define SD_OCP_GLITCH_64 0x01 464#define SD_OCP_GLITCH_640 0x02 465#define SD_OCP_GLITCH_1000 0x03 466#define SD_OCP_GLITCH_2000 0x04 467#define SD_OCP_GLITCH_4000 0x05 468#define SD_OCP_GLITCH_8000 0x06 469#define SD_OCP_GLITCH_10000 0x07 470 471#define MS_OCP_GLITCH_MASK 0x70 472#define MS_OCP_GLITCH_6_4 (0x00 << 4) 473#define MS_OCP_GLITCH_64 (0x01 << 4) 474#define MS_OCP_GLITCH_640 (0x02 << 4) 475#define MS_OCP_GLITCH_1000 (0x03 << 4) 476#define MS_OCP_GLITCH_2000 (0x04 << 4) 477#define MS_OCP_GLITCH_4000 (0x05 << 4) 478#define MS_OCP_GLITCH_8000 (0x06 << 4) 479#define MS_OCP_GLITCH_10000 (0x07 << 4) 480 481#define OCP_TIME_60 0x00 482#define OCP_TIME_100 (0x01 << 3) 483#define OCP_TIME_200 (0x02 << 3) 484#define OCP_TIME_400 (0x03 << 3) 485#define OCP_TIME_600 (0x04 << 3) 486#define OCP_TIME_800 (0x05 << 3) 487#define OCP_TIME_1100 (0x06 << 3) 488#define OCP_TIME_MASK 0x38 489 490#define MS_OCP_TIME_60 0x00 491#define MS_OCP_TIME_100 (0x01 << 4) 492#define MS_OCP_TIME_200 (0x02 << 4) 493#define MS_OCP_TIME_400 (0x03 << 4) 494#define MS_OCP_TIME_600 (0x04 << 4) 495#define MS_OCP_TIME_800 (0x05 << 4) 496#define MS_OCP_TIME_1100 (0x06 << 4) 497#define MS_OCP_TIME_MASK 0x70 498 499#define SD_OCP_TIME_60 0x00 500#define SD_OCP_TIME_100 0x01 501#define SD_OCP_TIME_200 0x02 502#define SD_OCP_TIME_400 0x03 503#define SD_OCP_TIME_600 0x04 504#define SD_OCP_TIME_800 0x05 505#define SD_OCP_TIME_1100 0x06 506#define SD_OCP_TIME_MASK 0x07 507 508#define OCP_THD_315_417 0x00 509#define OCP_THD_283_783 (0x01 << 6) 510#define OCP_THD_244_946 (0x02 << 6) 511#define OCP_THD_191_1080 (0x03 << 6) 512#define OCP_THD_MASK 0xC0 513 514#define MS_OCP_THD_450 0x00 515#define MS_OCP_THD_550 (0x01 << 4) 516#define MS_OCP_THD_650 (0x02 << 4) 517#define MS_OCP_THD_750 (0x03 << 4) 518#define MS_OCP_THD_850 (0x04 << 4) 519#define MS_OCP_THD_950 (0x05 << 4) 520#define MS_OCP_THD_1050 (0x06 << 4) 521#define MS_OCP_THD_1150 (0x07 << 4) 522#define MS_OCP_THD_MASK 0x70 523 524#define SD_OCP_THD_450 0x00 525#define SD_OCP_THD_550 0x01 526#define SD_OCP_THD_650 0x02 527#define SD_OCP_THD_750 0x03 528#define SD_OCP_THD_850 0x04 529#define SD_OCP_THD_950 0x05 530#define SD_OCP_THD_1050 0x06 531#define SD_OCP_THD_1150 0x07 532#define SD_OCP_THD_MASK 0x07 533 534#define FPGA_MS_PULL_CTL_EN 0xEF 535#define FPGA_SD_PULL_CTL_EN 0xF7 536#define FPGA_XD_PULL_CTL_EN1 0xFE 537#define FPGA_XD_PULL_CTL_EN2 0xFD 538#define FPGA_XD_PULL_CTL_EN3 0xFB 539 540#define FPGA_MS_PULL_CTL_BIT 0x10 541#define FPGA_SD_PULL_CTL_BIT 0x08 542 543#define BLINK_EN 0x08 544#define LED_GPIO0 (0 << 4) 545#define LED_GPIO1 (1 << 4) 546#define LED_GPIO2 (2 << 4) 547 548#define SDIO_BUS_CTRL 0x01 549#define SDIO_CD_CTRL 0x02 550 551#define SSC_RSTB 0x80 552#define SSC_8X_EN 0x40 553#define SSC_FIX_FRAC 0x20 554#define SSC_SEL_1M 0x00 555#define SSC_SEL_2M 0x08 556#define SSC_SEL_4M 0x10 557#define SSC_SEL_8M 0x18 558 559#define SSC_DEPTH_MASK 0x07 560#define SSC_DEPTH_DISALBE 0x00 561#define SSC_DEPTH_4M 0x01 562#define SSC_DEPTH_2M 0x02 563#define SSC_DEPTH_1M 0x03 564#define SSC_DEPTH_512K 0x04 565#define SSC_DEPTH_256K 0x05 566#define SSC_DEPTH_128K 0x06 567#define SSC_DEPTH_64K 0x07 568 569#define XD_D3_NP 0x00 570#define XD_D3_PD (0x01 << 6) 571#define XD_D3_PU (0x02 << 6) 572#define XD_D2_NP 0x00 573#define XD_D2_PD (0x01 << 4) 574#define XD_D2_PU (0x02 << 4) 575#define XD_D1_NP 0x00 576#define XD_D1_PD (0x01 << 2) 577#define XD_D1_PU (0x02 << 2) 578#define XD_D0_NP 0x00 579#define XD_D0_PD 0x01 580#define XD_D0_PU 0x02 581 582#define SD_D7_NP 0x00 583#define SD_D7_PD (0x01 << 4) 584#define SD_DAT7_PU (0x02 << 4) 585#define SD_CLK_NP 0x00 586#define SD_CLK_PD (0x01 << 2) 587#define SD_CLK_PU (0x02 << 2) 588#define SD_D5_NP 0x00 589#define SD_D5_PD 0x01 590#define SD_D5_PU 0x02 591 592#define MS_D1_NP 0x00 593#define MS_D1_PD (0x01 << 6) 594#define MS_D1_PU (0x02 << 6) 595#define MS_D2_NP 0x00 596#define MS_D2_PD (0x01 << 4) 597#define MS_D2_PU (0x02 << 4) 598#define MS_CLK_NP 0x00 599#define MS_CLK_PD (0x01 << 2) 600#define MS_CLK_PU (0x02 << 2) 601#define MS_D6_NP 0x00 602#define MS_D6_PD 0x01 603#define MS_D6_PU 0x02 604 605#define XD_D7_NP 0x00 606#define XD_D7_PD (0x01 << 6) 607#define XD_D7_PU (0x02 << 6) 608#define XD_D6_NP 0x00 609#define XD_D6_PD (0x01 << 4) 610#define XD_D6_PU (0x02 << 4) 611#define XD_D5_NP 0x00 612#define XD_D5_PD (0x01 << 2) 613#define XD_D5_PU (0x02 << 2) 614#define XD_D4_NP 0x00 615#define XD_D4_PD 0x01 616#define XD_D4_PU 0x02 617 618#define SD_D6_NP 0x00 619#define SD_D6_PD (0x01 << 6) 620#define SD_D6_PU (0x02 << 6) 621#define SD_D0_NP 0x00 622#define SD_D0_PD (0x01 << 4) 623#define SD_D0_PU (0x02 << 4) 624#define SD_D1_NP 0x00 625#define SD_D1_PD 0x01 626#define SD_D1_PU 0x02 627 628#define MS_D3_NP 0x00 629#define MS_D3_PD (0x01 << 6) 630#define MS_D3_PU (0x02 << 6) 631#define MS_D0_NP 0x00 632#define MS_D0_PD (0x01 << 4) 633#define MS_D0_PU (0x02 << 4) 634#define MS_BS_NP 0x00 635#define MS_BS_PD (0x01 << 2) 636#define MS_BS_PU (0x02 << 2) 637 638#define XD_WP_NP 0x00 639#define XD_WP_PD (0x01 << 6) 640#define XD_WP_PU (0x02 << 6) 641#define XD_CE_NP 0x00 642#define XD_CE_PD (0x01 << 3) 643#define XD_CE_PU (0x02 << 3) 644#define XD_CLE_NP 0x00 645#define XD_CLE_PD (0x01 << 1) 646#define XD_CLE_PU (0x02 << 1) 647#define XD_CD_PD 0x00 648#define XD_CD_PU 0x01 649 650#define SD_D4_NP 0x00 651#define SD_D4_PD (0x01 << 6) 652#define SD_D4_PU (0x02 << 6) 653 654#define MS_D7_NP 0x00 655#define MS_D7_PD (0x01 << 6) 656#define MS_D7_PU (0x02 << 6) 657 658#define XD_RDY_NP 0x00 659#define XD_RDY_PD (0x01 << 6) 660#define XD_RDY_PU (0x02 << 6) 661#define XD_WE_NP 0x00 662#define XD_WE_PD (0x01 << 4) 663#define XD_WE_PU (0x02 << 4) 664#define XD_RE_NP 0x00 665#define XD_RE_PD (0x01 << 2) 666#define XD_RE_PU (0x02 << 2) 667#define XD_ALE_NP 0x00 668#define XD_ALE_PD 0x01 669#define XD_ALE_PU 0x02 670 671#define SD_D3_NP 0x00 672#define SD_D3_PD (0x01 << 4) 673#define SD_D3_PU (0x02 << 4) 674#define SD_D2_NP 0x00 675#define SD_D2_PD (0x01 << 2) 676#define SD_D2_PU (0x02 << 2) 677 678#define MS_INS_PD 0x00 679#define MS_INS_PU (0x01 << 7) 680#define SD_WP_NP 0x00 681#define SD_WP_PD (0x01 << 5) 682#define SD_WP_PU (0x02 << 5) 683#define SD_CD_PD 0x00 684#define SD_CD_PU (0x01 << 4) 685#define SD_CMD_NP 0x00 686#define SD_CMD_PD (0x01 << 2) 687#define SD_CMD_PU (0x02 << 2) 688 689#define MS_D5_NP 0x00 690#define MS_D5_PD (0x01 << 2) 691#define MS_D5_PU (0x02 << 2) 692#define MS_D4_NP 0x00 693#define MS_D4_PD 0x01 694#define MS_D4_PU 0x02 695 696#define FORCE_PM_CLOCK 0x10 697#define EN_CLOCK_PM 0x01 698 699#define HOST_ENTER_S3 0x02 700#define HOST_ENTER_S1 0x01 701 702#define AUX_PWR_DETECTED 0x01 703 704#define PHY_DEBUG_MODE 0x01 705 706#define SPI_COMMAND_BIT_8 0xE0 707#define SPI_ADDRESS_BIT_24 0x17 708#define SPI_ADDRESS_BIT_32 0x1F 709 710#define SPI_TRANSFER0_START 0x80 711#define SPI_TRANSFER0_END 0x40 712#define SPI_C_MODE0 0x00 713#define SPI_CA_MODE0 0x01 714#define SPI_CDO_MODE0 0x02 715#define SPI_CDI_MODE0 0x03 716#define SPI_CADO_MODE0 0x04 717#define SPI_CADI_MODE0 0x05 718#define SPI_POLLING_MODE0 0x06 719 720#define SPI_TRANSFER1_START 0x80 721#define SPI_TRANSFER1_END 0x40 722#define SPI_DO_MODE1 0x00 723#define SPI_DI_MODE1 0x01 724 725#define CS_POLARITY_HIGH 0x40 726#define CS_POLARITY_LOW 0x00 727#define DTO_MSB_FIRST 0x00 728#define DTO_LSB_FIRST 0x20 729#define SPI_MASTER 0x00 730#define SPI_SLAVE 0x10 731#define SPI_MODE0 0x00 732#define SPI_MODE1 0x04 733#define SPI_MODE2 0x08 734#define SPI_MODE3 0x0C 735#define SPI_MANUAL 0x00 736#define SPI_HALF_AUTO 0x01 737#define SPI_AUTO 0x02 738#define SPI_EEPROM_AUTO 0x03 739 740#define EDO_TIMING_MASK 0x03 741#define SAMPLE_RISING 0x00 742#define SAMPLE_DELAY_HALF 0x01 743#define SAMPLE_DELAY_ONE 0x02 744#define SAPMLE_DELAY_ONE_HALF 0x03 745#define TCS_MASK 0x0C 746 747#define NOT_BYPASS_SD 0x02 748#define DISABLE_SDIO_FUNC 0x04 749#define SELECT_1LUN 0x08 750 751#define PWR_GATE_EN 0x01 752#define LDO3318_PWR_MASK 0x06 753#define LDO_ON 0x00 754#define LDO_SUSPEND 0x04 755#define LDO_OFF 0x06 756 757#define SD_CFG1 0xFDA0 758#define SD_CFG2 0xFDA1 759#define SD_CFG3 0xFDA2 760#define SD_STAT1 0xFDA3 761#define SD_STAT2 0xFDA4 762#define SD_BUS_STAT 0xFDA5 763#define SD_PAD_CTL 0xFDA6 764#define SD_SAMPLE_POINT_CTL 0xFDA7 765#define SD_PUSH_POINT_CTL 0xFDA8 766#define SD_CMD0 0xFDA9 767#define SD_CMD1 0xFDAA 768#define SD_CMD2 0xFDAB 769#define SD_CMD3 0xFDAC 770#define SD_CMD4 0xFDAD 771#define SD_CMD5 0xFDAE 772#define SD_BYTE_CNT_L 0xFDAF 773#define SD_BYTE_CNT_H 0xFDB0 774#define SD_BLOCK_CNT_L 0xFDB1 775#define SD_BLOCK_CNT_H 0xFDB2 776#define SD_TRANSFER 0xFDB3 777#define SD_CMD_STATE 0xFDB5 778#define SD_DATA_STATE 0xFDB6 779 780#define DCM_DRP_CTL 0xFC23 781#define DCM_DRP_TRIG 0xFC24 782#define DCM_DRP_CFG 0xFC25 783#define DCM_DRP_WR_DATA_L 0xFC26 784#define DCM_DRP_WR_DATA_H 0xFC27 785#define DCM_DRP_RD_DATA_L 0xFC28 786#define DCM_DRP_RD_DATA_H 0xFC29 787#define SD_VPCLK0_CTL 0xFC2A 788#define SD_VPCLK1_CTL 0xFC2B 789#define SD_DCMPS0_CTL 0xFC2C 790#define SD_DCMPS1_CTL 0xFC2D 791#define SD_VPTX_CTL SD_VPCLK0_CTL 792#define SD_VPRX_CTL SD_VPCLK1_CTL 793#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL 794#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL 795 796#define CARD_CLK_SOURCE 0xFC2E 797 798#define CARD_PWR_CTL 0xFD50 799#define CARD_CLK_SWITCH 0xFD51 800#define CARD_SHARE_MODE 0xFD52 801#define CARD_DRIVE_SEL 0xFD53 802#define CARD_STOP 0xFD54 803#define CARD_OE 0xFD55 804#define CARD_AUTO_BLINK 0xFD56 805#define CARD_GPIO_DIR 0xFD57 806#define CARD_GPIO 0xFD58 807 808#define CARD_DATA_SOURCE 0xFD5B 809#define CARD_SELECT 0xFD5C 810#define SD30_DRIVE_SEL 0xFD5E 811 812#define CARD_CLK_EN 0xFD69 813 814#define SDIO_CTRL 0xFD6B 815 816#define FPDCTL 0xFC00 817#define PDINFO 0xFC01 818 819#define CLK_CTL 0xFC02 820#define CLK_DIV 0xFC03 821#define CLK_SEL 0xFC04 822 823#define SSC_DIV_N_0 0xFC0F 824#define SSC_DIV_N_1 0xFC10 825 826#define RCCTL 0xFC14 827 828#define FPGA_PULL_CTL 0xFC1D 829 830#define CARD_PULL_CTL1 0xFD60 831#define CARD_PULL_CTL2 0xFD61 832#define CARD_PULL_CTL3 0xFD62 833#define CARD_PULL_CTL4 0xFD63 834#define CARD_PULL_CTL5 0xFD64 835#define CARD_PULL_CTL6 0xFD65 836 837#define IRQEN0 0xFE20 838#define IRQSTAT0 0xFE21 839#define IRQEN1 0xFE22 840#define IRQSTAT1 0xFE23 841#define TLPRIEN 0xFE24 842#define TLPRISTAT 0xFE25 843#define TLPTIEN 0xFE26 844#define TLPTISTAT 0xFE27 845#define DMATC0 0xFE28 846#define DMATC1 0xFE29 847#define DMATC2 0xFE2A 848#define DMATC3 0xFE2B 849#define DMACTL 0xFE2C 850#define BCTL 0xFE2D 851#define RBBC0 0xFE2E 852#define RBBC1 0xFE2F 853#define RBDAT 0xFE30 854#define RBCTL 0xFE34 855#define CFGADDR0 0xFE35 856#define CFGADDR1 0xFE36 857#define CFGDATA0 0xFE37 858#define CFGDATA1 0xFE38 859#define CFGDATA2 0xFE39 860#define CFGDATA3 0xFE3A 861#define CFGRWCTL 0xFE3B 862#define PHYRWCTL 0xFE3C 863#define PHYDATA0 0xFE3D 864#define PHYDATA1 0xFE3E 865#define PHYADDR 0xFE3F 866#define MSGRXDATA0 0xFE40 867#define MSGRXDATA1 0xFE41 868#define MSGRXDATA2 0xFE42 869#define MSGRXDATA3 0xFE43 870#define MSGTXDATA0 0xFE44 871#define MSGTXDATA1 0xFE45 872#define MSGTXDATA2 0xFE46 873#define MSGTXDATA3 0xFE47 874#define MSGTXCTL 0xFE48 875#define PETXCFG 0xFE49 876 877#define CDRESUMECTL 0xFE52 878#define WAKE_SEL_CTL 0xFE54 879#define PME_FORCE_CTL 0xFE56 880#define ASPM_FORCE_CTL 0xFE57 881#define PM_CLK_FORCE_CTL 0xFE58 882#define PERST_GLITCH_WIDTH 0xFE5C 883#define CHANGE_LINK_STATE 0xFE5B 884#define RESET_LOAD_REG 0xFE5E 885#define HOST_SLEEP_STATE 0xFE60 886#define MAIN_PWR_OFF_CTL 0xFE70 /* RTS5208 */ 887 888#define NFTS_TX_CTRL 0xFE72 889 890#define PWR_GATE_CTRL 0xFE75 891#define PWD_SUSPEND_EN 0xFE76 892 893#define EFUSE_CONTENT 0xFE5F 894 895#define XD_INIT 0xFD10 896#define XD_DTCTL 0xFD11 897#define XD_CTL 0xFD12 898#define XD_TRANSFER 0xFD13 899#define XD_CFG 0xFD14 900#define XD_ADDRESS0 0xFD15 901#define XD_ADDRESS1 0xFD16 902#define XD_ADDRESS2 0xFD17 903#define XD_ADDRESS3 0xFD18 904#define XD_ADDRESS4 0xFD19 905#define XD_DAT 0xFD1A 906#define XD_PAGE_CNT 0xFD1B 907#define XD_PAGE_STATUS 0xFD1C 908#define XD_BLOCK_STATUS 0xFD1D 909#define XD_BLOCK_ADDR1_L 0xFD1E 910#define XD_BLOCK_ADDR1_H 0xFD1F 911#define XD_BLOCK_ADDR2_L 0xFD20 912#define XD_BLOCK_ADDR2_H 0xFD21 913#define XD_BYTE_CNT_L 0xFD22 914#define XD_BYTE_CNT_H 0xFD23 915#define XD_PARITY 0xFD24 916#define XD_ECC_BIT1 0xFD25 917#define XD_ECC_BYTE1 0xFD26 918#define XD_ECC_BIT2 0xFD27 919#define XD_ECC_BYTE2 0xFD28 920#define XD_RESERVED0 0xFD29 921#define XD_RESERVED1 0xFD2A 922#define XD_RESERVED2 0xFD2B 923#define XD_RESERVED3 0xFD2C 924#define XD_CHK_DATA_STATUS 0xFD2D 925#define XD_CATCTL 0xFD2E 926 927#define MS_CFG 0xFD40 928#define MS_TPC 0xFD41 929#define MS_TRANS_CFG 0xFD42 930#define MS_TRANSFER 0xFD43 931#define MS_INT_REG 0xFD44 932#define MS_BYTE_CNT 0xFD45 933#define MS_SECTOR_CNT_L 0xFD46 934#define MS_SECTOR_CNT_H 0xFD47 935#define MS_DBUS_H 0xFD48 936 937#define SSC_CTL1 0xFC11 938#define SSC_CTL2 0xFC12 939 940#define OCPCTL 0xFC15 941#define OCPSTAT 0xFC16 942#define OCPCLR 0xFC17 /* 5208 */ 943#define OCPPARA1 0xFC18 944#define OCPPARA2 0xFC19 945 946#define EFUSE_OP 0xFC20 947#define EFUSE_CTRL 0xFC21 948#define EFUSE_DATA 0xFC22 949 950#define SPI_COMMAND 0xFD80 951#define SPI_ADDR0 0xFD81 952#define SPI_ADDR1 0xFD82 953#define SPI_ADDR2 0xFD83 954#define SPI_ADDR3 0xFD84 955#define SPI_CA_NUMBER 0xFD85 956#define SPI_LENGTH0 0xFD86 957#define SPI_LENGTH1 0xFD87 958#define SPI_DATA 0xFD88 959#define SPI_DATA_NUMBER 0xFD89 960#define SPI_TRANSFER0 0xFD90 961#define SPI_TRANSFER1 0xFD91 962#define SPI_CONTROL 0xFD92 963#define SPI_SIG 0xFD93 964#define SPI_TCTL 0xFD94 965#define SPI_SLAVE_NUM 0xFD95 966#define SPI_CLK_DIVIDER0 0xFD96 967#define SPI_CLK_DIVIDER1 0xFD97 968 969#define SRAM_BASE 0xE600 970#define RBUF_BASE 0xF400 971#define PPBUF_BASE1 0xF800 972#define PPBUF_BASE2 0xFA00 973#define IMAGE_FLAG_ADDR0 0xCE80 974#define IMAGE_FLAG_ADDR1 0xCE81 975 976#define READ_OP 1 977#define WRITE_OP 2 978 979#define LCTLR 0x80 980 981#define POLLING_WAIT_CNT 1 982#define IDLE_MAX_COUNT 10 983#define SDIO_IDLE_COUNT 10 984 985#define DEBOUNCE_CNT 5 986 987void do_remaining_work(struct rtsx_chip *chip); 988void try_to_switch_sdio_ctrl(struct rtsx_chip *chip); 989void do_reset_sd_card(struct rtsx_chip *chip); 990void do_reset_xd_card(struct rtsx_chip *chip); 991void do_reset_ms_card(struct rtsx_chip *chip); 992void rtsx_power_off_card(struct rtsx_chip *chip); 993void rtsx_release_cards(struct rtsx_chip *chip); 994void rtsx_reset_cards(struct rtsx_chip *chip); 995void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip); 996void rtsx_init_cards(struct rtsx_chip *chip); 997int switch_ssc_clock(struct rtsx_chip *chip, int clk); 998int switch_normal_clock(struct rtsx_chip *chip, int clk); 999int enable_card_clock(struct rtsx_chip *chip, u8 card); 1000int disable_card_clock(struct rtsx_chip *chip, u8 card); 1001int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 1002 u32 sec_addr, u16 sec_cnt); 1003void trans_dma_enable(enum dma_data_direction dir, 1004 struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size); 1005void toggle_gpio(struct rtsx_chip *chip, u8 gpio); 1006void turn_on_led(struct rtsx_chip *chip, u8 gpio); 1007void turn_off_led(struct rtsx_chip *chip, u8 gpio); 1008 1009int card_share_mode(struct rtsx_chip *chip, int card); 1010int select_card(struct rtsx_chip *chip, int card); 1011int detect_card_cd(struct rtsx_chip *chip, int card); 1012int check_card_exist(struct rtsx_chip *chip, unsigned int lun); 1013int check_card_ready(struct rtsx_chip *chip, unsigned int lun); 1014int check_card_wp(struct rtsx_chip *chip, unsigned int lun); 1015void eject_card(struct rtsx_chip *chip, unsigned int lun); 1016u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun); 1017 1018static inline u32 get_card_size(struct rtsx_chip *chip, unsigned int lun) 1019{ 1020#ifdef SUPPORT_SD_LOCK 1021 struct sd_info *sd_card = &chip->sd_card; 1022 1023 if ((get_lun_card(chip, lun) == SD_CARD) && 1024 (sd_card->sd_lock_status & SD_LOCKED)) 1025 return 0; 1026 1027 return chip->capacity[lun]; 1028#else 1029 return chip->capacity[lun]; 1030#endif 1031} 1032 1033static inline int switch_clock(struct rtsx_chip *chip, int clk) 1034{ 1035 int retval = 0; 1036 1037 if (chip->asic_code) 1038 retval = switch_ssc_clock(chip, clk); 1039 else 1040 retval = switch_normal_clock(chip, clk); 1041 1042 return retval; 1043} 1044 1045int card_power_on(struct rtsx_chip *chip, u8 card); 1046int card_power_off(struct rtsx_chip *chip, u8 card); 1047 1048static inline int card_power_off_all(struct rtsx_chip *chip) 1049{ 1050 int retval; 1051 1052 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0x0F, 0x0F); 1053 if (retval) 1054 return retval; 1055 1056 return STATUS_SUCCESS; 1057} 1058 1059static inline void rtsx_clear_xd_error(struct rtsx_chip *chip) 1060{ 1061 rtsx_write_register(chip, CARD_STOP, XD_STOP | XD_CLR_ERR, 1062 XD_STOP | XD_CLR_ERR); 1063} 1064 1065static inline void rtsx_clear_sd_error(struct rtsx_chip *chip) 1066{ 1067 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, 1068 SD_STOP | SD_CLR_ERR); 1069} 1070 1071static inline void rtsx_clear_ms_error(struct rtsx_chip *chip) 1072{ 1073 rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 1074 MS_STOP | MS_CLR_ERR); 1075} 1076 1077static inline void rtsx_clear_spi_error(struct rtsx_chip *chip) 1078{ 1079 rtsx_write_register(chip, CARD_STOP, SPI_STOP | SPI_CLR_ERR, 1080 SPI_STOP | SPI_CLR_ERR); 1081} 1082 1083#ifdef SUPPORT_SDIO_ASPM 1084void dynamic_configure_sdio_aspm(struct rtsx_chip *chip); 1085#endif 1086 1087#endif /* __REALTEK_RTSX_CARD_H */ 1088