1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7#ifndef __RTL8712_CMDCTRL_BITDEF_H__ 8#define __RTL8712_CMDCTRL_BITDEF_H__ 9 10/* 11 * 2. Command Control Registers (Offset: 0x0040 - 0x004F) 12 */ 13/*--------------------------------------------------------------------------*/ 14/* 8192S (CMD) command register bits (Offset 0x40, 16 bits)*/ 15/*--------------------------------------------------------------------------*/ 16#define _APSDOFF_STATUS BIT(15) 17#define _APSDOFF BIT(14) 18#define _BBRSTn BIT(13) /*Enable OFDM/CCK*/ 19#define _BB_GLB_RSTn BIT(12) /*Enable BB*/ 20#define _SCHEDULE_EN BIT(10) /*Enable MAC scheduler*/ 21#define _MACRXEN BIT(9) 22#define _MACTXEN BIT(8) 23#define _DDMA_EN BIT(7) /*FW off load function enable*/ 24#define _FW2HW_EN BIT(6) /*MAC every module reset */ 25#define _RXDMA_EN BIT(5) 26#define _TXDMA_EN BIT(4) 27#define _HCI_RXDMA_EN BIT(3) 28#define _HCI_TXDMA_EN BIT(2) 29 30/*TXPAUSE*/ 31#define _STOPHCCA BIT(6) 32#define _STOPHIGH BIT(5) 33#define _STOPMGT BIT(4) 34#define _STOPVO BIT(3) 35#define _STOPVI BIT(2) 36#define _STOPBE BIT(1) 37#define _STOPBK BIT(0) 38 39/*TCR*/ 40#define _DISCW BIT(20) 41#define _ICV BIT(19) 42#define _CFEND_FMT BIT(17) 43#define _CRC BIT(16) 44#define _FWRDY BIT(7) 45#define _BASECHG BIT(6) 46#define _IMEM_RDY BIT(5) 47#define _DMEM_CODE_DONE BIT(4) 48#define _EMEM_CHK_RPT BIT(3) 49#define _EMEM_CODE_DONE BIT(2) 50#define _IMEM_CHK_RPT BIT(1) 51#define _IMEM_CODE_DONE BIT(0) 52 53#define _TXDMA_INIT_VALUE (_IMEM_CHK_RPT | _EMEM_CHK_RPT) 54 55/*RCR*/ 56#define _ENMBID BIT(27) 57#define _APP_PHYST_RXFF BIT(25) 58#define _APP_PHYST_STAFF BIT(24) 59#define _CBSSID BIT(23) 60#define _APWRMGT BIT(22) 61#define _ADD3 BIT(21) 62#define _AMF BIT(20) 63#define _ACF BIT(19) 64#define _ADF BIT(18) 65#define _APP_MIC BIT(17) 66#define _APP_ICV BIT(16) 67#define _RXFTH_MSK 0x0000E000 68#define _RXFTH_SHT 13 69#define _AICV BIT(12) 70#define _RXPKTLMT_MSK 0x00000FC0 71#define _RXPKTLMT_SHT 6 72#define _ACRC32 BIT(5) 73#define _AB BIT(3) 74#define _AM BIT(2) 75#define _APM BIT(1) 76#define _AAP BIT(0) 77 78/*MSR*/ 79#define _NETTYPE_MSK 0x03 80#define _NETTYPE_SHT 0 81 82/*BT*/ 83#define _BTMODE_MSK 0x06 84#define _BTMODE_SHT 1 85#define _ENBT BIT(0) 86 87/*MBIDCTRL*/ 88#define _ENMBID_MODE BIT(15) 89#define _BCNNO_MSK 0x7000 90#define _BCNNO_SHT 12 91#define _BCNSPACE_MSK 0x0FFF 92#define _BCNSPACE_SHT 0 93 94#endif /* __RTL8712_CMDCTRL_BITDEF_H__*/ 95 96