1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7#ifndef R8180_HW 8#define R8180_HW 9 10enum baseband_config { 11 BB_CONFIG_PHY_REG = 0, 12 BB_CONFIG_AGC_TAB = 1, 13}; 14 15#define RTL8190_EEPROM_ID 0x8129 16#define EEPROM_VID 0x02 17#define EEPROM_DID 0x04 18#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C 19 20#define EEPROM_Default_ThermalMeter 0x77 21#define EEPROM_Default_AntTxPowerDiff 0x0 22#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 23#define EEPROM_Default_TxPower 0x1010 24#define EEPROM_ICVersion_ChannelPlan 0x7C 25#define EEPROM_Customer_ID 0x7B 26#define EEPROM_RFInd_PowerDiff 0x28 27 28#define EEPROM_ThermalMeter 0x29 29#define EEPROM_TxPwDiff_CrystalCap 0x2A 30#define EEPROM_TxPwIndex_CCK 0x2C 31#define EEPROM_TxPwIndex_OFDM_24G 0x3A 32 33#define EEPROM_CID_TOSHIBA 0x4 34#define EEPROM_CID_NetCore 0x5 35enum _RTL8192PCI_HW { 36 MAC0 = 0x000, 37 MAC4 = 0x004, 38 PCIF = 0x009, 39#define MXDMA2_NO_LIMIT 0x7 40 41#define MXDMA2_RX_SHIFT 4 42#define MXDMA2_TX_SHIFT 0 43 PMR = 0x00c, 44 EPROM_CMD = 0x00e, 45 46#define EPROM_CMD_9356SEL BIT(4) 47#define EPROM_CMD_OPERATING_MODE_SHIFT 6 48#define EPROM_CMD_NORMAL 0 49#define EPROM_CMD_PROGRAM 2 50#define EPROM_CS_BIT 3 51#define EPROM_CK_BIT 2 52#define EPROM_W_BIT 1 53#define EPROM_R_BIT 0 54 55 ANAPAR = 0x17, 56#define BB_GLOBAL_RESET_BIT 0x1 57 BB_GLOBAL_RESET = 0x020, 58 BSSIDR = 0x02E, 59 CMDR = 0x037, 60#define CR_RE 0x08 61#define CR_TE 0x04 62 SIFS = 0x03E, 63 RCR = 0x044, 64#define RCR_ONLYERLPKT BIT(31) 65#define RCR_CBSSID BIT(23) 66#define RCR_ADD3 BIT(21) 67#define RCR_AMF BIT(20) 68#define RCR_ADF BIT(18) 69#define RCR_AICV BIT(12) 70#define RCR_AB BIT(3) 71#define RCR_AM BIT(2) 72#define RCR_APM BIT(1) 73#define RCR_AAP BIT(0) 74#define RCR_MXDMA_OFFSET 8 75#define RCR_FIFO_OFFSET 13 76 SLOT_TIME = 0x049, 77 ACK_TIMEOUT = 0x04c, 78 EDCAPARA_BE = 0x050, 79 EDCAPARA_BK = 0x054, 80 EDCAPARA_VO = 0x058, 81 EDCAPARA_VI = 0x05C, 82#define AC_PARAM_TXOP_LIMIT_OFFSET 16 83#define AC_PARAM_ECW_MAX_OFFSET 12 84#define AC_PARAM_ECW_MIN_OFFSET 8 85#define AC_PARAM_AIFS_OFFSET 0 86 BCN_TCFG = 0x062, 87#define BCN_TCFG_CW_SHIFT 8 88#define BCN_TCFG_IFS 0 89 BCN_INTERVAL = 0x070, 90 ATIMWND = 0x072, 91 BCN_DRV_EARLY_INT = 0x074, 92 BCN_DMATIME = 0x076, 93 BCN_ERR_THRESH = 0x078, 94 RWCAM = 0x0A0, 95#define TOTAL_CAM_ENTRY 32 96 WCAMI = 0x0A4, 97 SECR = 0x0B0, 98#define SCR_TxUseDK BIT(0) 99#define SCR_RxUseDK BIT(1) 100#define SCR_TxEncEnable BIT(2) 101#define SCR_RxDecEnable BIT(3) 102#define SCR_NoSKMC BIT(5) 103 SWREGULATOR = 0x0BD, 104 INTA_MASK = 0x0f4, 105#define IMR_TBDOK BIT(27) 106#define IMR_TBDER BIT(26) 107#define IMR_TXFOVW BIT(15) 108#define IMR_TIMEOUT0 BIT(14) 109#define IMR_BcnInt BIT(13) 110#define IMR_RXFOVW BIT(12) 111#define IMR_RDU BIT(11) 112#define IMR_RXCMDOK BIT(10) 113#define IMR_BDOK BIT(9) 114#define IMR_HIGHDOK BIT(8) 115#define IMR_COMDOK BIT(7) 116#define IMR_MGNTDOK BIT(6) 117#define IMR_HCCADOK BIT(5) 118#define IMR_BKDOK BIT(4) 119#define IMR_BEDOK BIT(3) 120#define IMR_VIDOK BIT(2) 121#define IMR_VODOK BIT(1) 122#define IMR_ROK BIT(0) 123 ISR = 0x0f8, 124 TP_POLL = 0x0fd, 125#define TP_POLL_CQ BIT(5) 126 PSR = 0x0ff, 127 CPU_GEN = 0x100, 128#define CPU_CCK_LOOPBACK 0x00030000 129#define CPU_GEN_SYSTEM_RESET 0x00000001 130#define CPU_GEN_FIRMWARE_RESET 0x00000008 131#define CPU_GEN_BOOT_RDY 0x00000010 132#define CPU_GEN_FIRM_RDY 0x00000020 133#define CPU_GEN_PUT_CODE_OK 0x00000080 134#define CPU_GEN_BB_RST 0x00000100 135#define CPU_GEN_PWR_STB_CPU 0x00000004 136#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF 137#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 138 ACM_HW_CTRL = 0x171, 139#define ACM_HW_BEQ_EN BIT(1) 140#define ACM_HW_VIQ_EN BIT(2) 141#define ACM_HW_VOQ_EN BIT(3) 142 RQPN1 = 0x180, 143 RQPN2 = 0x184, 144 RQPN3 = 0x188, 145 QPNR = 0x1F0, 146 BQDA = 0x200, 147 HQDA = 0x204, 148 CQDA = 0x208, 149 MQDA = 0x20C, 150 HCCAQDA = 0x210, 151 VOQDA = 0x214, 152 VIQDA = 0x218, 153 BEQDA = 0x21C, 154 BKQDA = 0x220, 155 RDQDA = 0x228, 156 157 WFCRC0 = 0x2f0, 158 WFCRC1 = 0x2f4, 159 WFCRC2 = 0x2f8, 160 161 BW_OPMODE = 0x300, 162#define BW_OPMODE_20MHZ BIT(2) 163 IC_VERRSION = 0x301, 164 MSR = 0x303, 165#define MSR_LINK_MASK (BIT(1) | BIT(0)) 166#define MSR_LINK_MANAGED 2 167#define MSR_LINK_ADHOC 1 168#define MSR_LINK_MASTER 3 169 170#define MSR_NOLINK 0x00 171#define MSR_ADHOC 0x01 172#define MSR_INFRA 0x02 173#define MSR_AP 0x03 174 175 RETRY_LIMIT = 0x304, 176#define RETRY_LIMIT_SHORT_SHIFT 8 177#define RETRY_LIMIT_LONG_SHIFT 0 178 TSFR = 0x308, 179 RRSR = 0x310, 180#define RRSR_SHORT_OFFSET 23 181#define RRSR_1M BIT(0) 182#define RRSR_2M BIT(1) 183#define RRSR_5_5M BIT(2) 184#define RRSR_11M BIT(3) 185#define RRSR_6M BIT(4) 186#define RRSR_9M BIT(5) 187#define RRSR_12M BIT(6) 188#define RRSR_18M BIT(7) 189#define RRSR_24M BIT(8) 190#define RRSR_36M BIT(9) 191#define RRSR_48M BIT(10) 192#define RRSR_54M BIT(11) 193#define BRSR_AckShortPmb BIT(23) 194 UFWP = 0x318, 195 RATR0 = 0x320, 196#define RATR_1M 0x00000001 197#define RATR_2M 0x00000002 198#define RATR_55M 0x00000004 199#define RATR_11M 0x00000008 200#define RATR_6M 0x00000010 201#define RATR_9M 0x00000020 202#define RATR_12M 0x00000040 203#define RATR_18M 0x00000080 204#define RATR_24M 0x00000100 205#define RATR_36M 0x00000200 206#define RATR_48M 0x00000400 207#define RATR_54M 0x00000800 208#define RATR_MCS0 0x00001000 209#define RATR_MCS1 0x00002000 210#define RATR_MCS2 0x00004000 211#define RATR_MCS3 0x00008000 212#define RATR_MCS4 0x00010000 213#define RATR_MCS5 0x00020000 214#define RATR_MCS6 0x00040000 215#define RATR_MCS7 0x00080000 216#define RATR_MCS8 0x00100000 217#define RATR_MCS9 0x00200000 218#define RATR_MCS10 0x00400000 219#define RATR_MCS11 0x00800000 220#define RATR_MCS12 0x01000000 221#define RATR_MCS13 0x02000000 222#define RATR_MCS14 0x04000000 223#define RATR_MCS15 0x08000000 224#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 225#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \ 226 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 227#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 228 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 229 RATR_MCS6 | RATR_MCS7) 230#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 231 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 232 RATR_MCS14|RATR_MCS15) 233 234 DRIVER_RSSI = 0x32c, 235 MCS_TXAGC = 0x340, 236 CCK_TXAGC = 0x348, 237 MAC_BLK_CTRL = 0x403, 238}; 239 240#define GPI 0x108 241 242#define ANAPAR_FOR_8192PCIE 0x17 243 244#endif 245