1/* SPDX-License-Identifier: GPL-2.0 */
2// SPDX-License-Identifier: GPL-2.0-or-later
3/*
4 *    (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
5 */
6
7#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
8#define __SYSTEM_GLOBAL_H_INCLUDED__
9
10/*
11 * Create a list of HAS and IS properties that defines the system
12 * Those are common for both ISP2400 and ISP2401
13 *
14 * The configuration assumes the following
15 * - The system is hetereogeneous; Multiple cells and devices classes
16 * - The cell and device instances are homogeneous, each device type
17 *   belongs to the same class
18 * - Device instances supporting a subset of the class capabilities are
19 *   allowed
20 *
21 * We could manage different device classes through the enumerated
22 * lists (C) or the use of classes (C++), but that is presently not
23 * fully supported
24 *
25 * N.B. the 3 input formatters are of 2 different classess
26 */
27
28#define DMA_DDR_TO_VAMEM_WORKAROUND
29#define DMA_DDR_TO_HMEM_WORKAROUND
30
31/*
32 * The longest allowed (uninteruptible) bus transfer, does not
33 * take stalling into account
34 */
35#define HIVE_ISP_MAX_BURST_LENGTH	1024
36
37/*
38 * Maximum allowed burst length in words for the ISP DMA
39 * This value is set to 2 to prevent the ISP DMA from blocking
40 * the bus for too long; as the input system can only buffer
41 * 2 lines on Moorefield and Cherrytrail, the input system buffers
42 * may overflow if blocked for too long (BZ 2726).
43 */
44#define ISP2400_DMA_MAX_BURST_LENGTH	128
45#define ISP2401_DMA_MAX_BURST_LENGTH	2
46
47#include <hive_isp_css_defs.h>
48#include <type_support.h>
49
50/* This interface is deprecated */
51#include "hive_types.h"
52
53/*
54 * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
55 */
56#define HRT_VADDRESS_WIDTH	32
57
58#define SIZEOF_HRT_REG		(HRT_DATA_WIDTH >> 3)
59#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
60
61/* The main bus connecting all devices */
62#define HRT_BUS_WIDTH		HIVE_ISP_CTRL_DATA_WIDTH
63#define HRT_BUS_BYTES		HIVE_ISP_CTRL_DATA_BYTES
64
65typedef u32			hrt_bus_align_t;
66
67/*
68 * Enumerate the devices, device access through the API is by ID,
69 * through the DLI by address. The enumerator terminators are used
70 * to size the wiring arrays and as an exception value.
71 */
72typedef enum {
73	DDR0_ID = 0,
74	N_DDR_ID
75} ddr_ID_t;
76
77typedef enum {
78	ISP0_ID = 0,
79	N_ISP_ID
80} isp_ID_t;
81
82typedef enum {
83	SP0_ID = 0,
84	N_SP_ID
85} sp_ID_t;
86
87typedef enum {
88	MMU0_ID = 0,
89	MMU1_ID,
90	N_MMU_ID
91} mmu_ID_t;
92
93typedef enum {
94	DMA0_ID = 0,
95	N_DMA_ID
96} dma_ID_t;
97
98typedef enum {
99	GDC0_ID = 0,
100	GDC1_ID,
101	N_GDC_ID
102} gdc_ID_t;
103
104/* this extra define is needed because we want to use it also
105   in the preprocessor, and that doesn't work with enums.
106 */
107#define N_GDC_ID_CPP 2
108
109typedef enum {
110	VAMEM0_ID = 0,
111	VAMEM1_ID,
112	VAMEM2_ID,
113	N_VAMEM_ID
114} vamem_ID_t;
115
116typedef enum {
117	BAMEM0_ID = 0,
118	N_BAMEM_ID
119} bamem_ID_t;
120
121typedef enum {
122	HMEM0_ID = 0,
123	N_HMEM_ID
124} hmem_ID_t;
125
126typedef enum {
127	IRQ0_ID = 0,	/* GP IRQ block */
128	IRQ1_ID,	/* Input formatter */
129	IRQ2_ID,	/* input system */
130	IRQ3_ID,	/* input selector */
131	N_IRQ_ID
132} irq_ID_t;
133
134typedef enum {
135	FIFO_MONITOR0_ID = 0,
136	N_FIFO_MONITOR_ID
137} fifo_monitor_ID_t;
138
139typedef enum {
140	GP_DEVICE0_ID = 0,
141	N_GP_DEVICE_ID
142} gp_device_ID_t;
143
144typedef enum {
145	GP_TIMER0_ID = 0,
146	GP_TIMER1_ID,
147	GP_TIMER2_ID,
148	GP_TIMER3_ID,
149	GP_TIMER4_ID,
150	GP_TIMER5_ID,
151	GP_TIMER6_ID,
152	GP_TIMER7_ID,
153	N_GP_TIMER_ID
154} gp_timer_ID_t;
155
156typedef enum {
157	GPIO0_ID = 0,
158	N_GPIO_ID
159} gpio_ID_t;
160
161typedef enum {
162	TIMED_CTRL0_ID = 0,
163	N_TIMED_CTRL_ID
164} timed_ctrl_ID_t;
165
166typedef enum {
167	INPUT_FORMATTER0_ID = 0,
168	INPUT_FORMATTER1_ID,
169	INPUT_FORMATTER2_ID,
170	INPUT_FORMATTER3_ID,
171	N_INPUT_FORMATTER_ID
172} input_formatter_ID_t;
173
174/* The IF RST is outside the IF */
175#define INPUT_FORMATTER0_SRST_OFFSET	0x0824
176#define INPUT_FORMATTER1_SRST_OFFSET	0x0624
177#define INPUT_FORMATTER2_SRST_OFFSET	0x0424
178#define INPUT_FORMATTER3_SRST_OFFSET	0x0224
179
180#define INPUT_FORMATTER0_SRST_MASK		0x0001
181#define INPUT_FORMATTER1_SRST_MASK		0x0002
182#define INPUT_FORMATTER2_SRST_MASK		0x0004
183#define INPUT_FORMATTER3_SRST_MASK		0x0008
184
185typedef enum {
186	INPUT_SYSTEM0_ID = 0,
187	N_INPUT_SYSTEM_ID
188} input_system_ID_t;
189
190typedef enum {
191	RX0_ID = 0,
192	N_RX_ID
193} rx_ID_t;
194
195enum mipi_port_id {
196	MIPI_PORT0_ID = 0,
197	MIPI_PORT1_ID,
198	MIPI_PORT2_ID,
199	N_MIPI_PORT_ID
200};
201
202#define	N_RX_CHANNEL_ID		4
203
204/* Generic port enumeration with an internal port type ID */
205typedef enum {
206	CSI_PORT0_ID = 0,
207	CSI_PORT1_ID,
208	CSI_PORT2_ID,
209	TPG_PORT0_ID,
210	PRBS_PORT0_ID,
211	FIFO_PORT0_ID,
212	MEMORY_PORT0_ID,
213	N_INPUT_PORT_ID
214} input_port_ID_t;
215
216typedef enum {
217	CAPTURE_UNIT0_ID = 0,
218	CAPTURE_UNIT1_ID,
219	CAPTURE_UNIT2_ID,
220	ACQUISITION_UNIT0_ID,
221	DMA_UNIT0_ID,
222	CTRL_UNIT0_ID,
223	GPREGS_UNIT0_ID,
224	FIFO_UNIT0_ID,
225	IRQ_UNIT0_ID,
226	N_SUB_SYSTEM_ID
227} sub_system_ID_t;
228
229#define	N_CAPTURE_UNIT_ID		3
230#define	N_ACQUISITION_UNIT_ID		1
231#define	N_CTRL_UNIT_ID			1
232
233
234enum ia_css_isp_memories {
235	IA_CSS_ISP_PMEM0 = 0,
236	IA_CSS_ISP_DMEM0,
237	IA_CSS_ISP_VMEM0,
238	IA_CSS_ISP_VAMEM0,
239	IA_CSS_ISP_VAMEM1,
240	IA_CSS_ISP_VAMEM2,
241	IA_CSS_ISP_HMEM0,
242	IA_CSS_SP_DMEM0,
243	IA_CSS_DDR,
244	N_IA_CSS_MEMORIES
245};
246
247#define IA_CSS_NUM_MEMORIES 9
248/* For driver compatibility */
249#define N_IA_CSS_ISP_MEMORIES   IA_CSS_NUM_MEMORIES
250#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
251
252/*
253 * ISP2401 specific enums
254 */
255
256typedef enum {
257	ISYS_IRQ0_ID = 0,	/* port a */
258	ISYS_IRQ1_ID,	/* port b */
259	ISYS_IRQ2_ID,	/* port c */
260	N_ISYS_IRQ_ID
261} isys_irq_ID_t;
262
263
264/*
265 * Input-buffer Controller.
266 */
267typedef enum {
268	IBUF_CTRL0_ID = 0,	/* map to ISYS2401_IBUF_CNTRL_A */
269	IBUF_CTRL1_ID,		/* map to ISYS2401_IBUF_CNTRL_B */
270	IBUF_CTRL2_ID,		/* map ISYS2401_IBUF_CNTRL_C */
271	N_IBUF_CTRL_ID
272} ibuf_ctrl_ID_t;
273/* end of Input-buffer Controller */
274
275/*
276 * Stream2MMIO.
277 */
278typedef enum {
279	STREAM2MMIO0_ID = 0,	/* map to ISYS2401_S2M_A */
280	STREAM2MMIO1_ID,	/* map to ISYS2401_S2M_B */
281	STREAM2MMIO2_ID,	/* map to ISYS2401_S2M_C */
282	N_STREAM2MMIO_ID
283} stream2mmio_ID_t;
284
285typedef enum {
286	/*
287	 * Stream2MMIO 0 has 8 SIDs that are indexed by
288	 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
289	 *
290	 * Stream2MMIO 1 has 4 SIDs that are indexed by
291	 * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
292	 *
293	 * Stream2MMIO 2 has 4 SIDs that are indexed by
294	 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
295	 */
296	STREAM2MMIO_SID0_ID = 0,
297	STREAM2MMIO_SID1_ID,
298	STREAM2MMIO_SID2_ID,
299	STREAM2MMIO_SID3_ID,
300	STREAM2MMIO_SID4_ID,
301	STREAM2MMIO_SID5_ID,
302	STREAM2MMIO_SID6_ID,
303	STREAM2MMIO_SID7_ID,
304	N_STREAM2MMIO_SID_ID
305} stream2mmio_sid_ID_t;
306/* end of Stream2MMIO */
307
308/**
309 * Input System 2401: CSI-MIPI recevier.
310 */
311typedef enum {
312	CSI_RX_BACKEND0_ID = 0,	/* map to ISYS2401_MIPI_BE_A */
313	CSI_RX_BACKEND1_ID,		/* map to ISYS2401_MIPI_BE_B */
314	CSI_RX_BACKEND2_ID,		/* map to ISYS2401_MIPI_BE_C */
315	N_CSI_RX_BACKEND_ID
316} csi_rx_backend_ID_t;
317
318typedef enum {
319	CSI_RX_FRONTEND0_ID = 0,	/* map to ISYS2401_CSI_RX_A */
320	CSI_RX_FRONTEND1_ID,		/* map to ISYS2401_CSI_RX_B */
321	CSI_RX_FRONTEND2_ID,		/* map to ISYS2401_CSI_RX_C */
322#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
323} csi_rx_frontend_ID_t;
324
325typedef enum {
326	CSI_RX_DLANE0_ID = 0,		/* map to DLANE0 in CSI RX */
327	CSI_RX_DLANE1_ID,		/* map to DLANE1 in CSI RX */
328	CSI_RX_DLANE2_ID,		/* map to DLANE2 in CSI RX */
329	CSI_RX_DLANE3_ID,		/* map to DLANE3 in CSI RX */
330	N_CSI_RX_DLANE_ID
331} csi_rx_fe_dlane_ID_t;
332/* end of CSI-MIPI receiver */
333
334typedef enum {
335	ISYS2401_DMA0_ID = 0,
336	N_ISYS2401_DMA_ID
337} isys2401_dma_ID_t;
338
339/**
340 * Pixel-generator. ("system_global.h")
341 */
342typedef enum {
343	PIXELGEN0_ID = 0,
344	PIXELGEN1_ID,
345	PIXELGEN2_ID,
346	N_PIXELGEN_ID
347} pixelgen_ID_t;
348/* end of pixel-generator. ("system_global.h") */
349
350typedef enum {
351	INPUT_SYSTEM_CSI_PORT0_ID = 0,
352	INPUT_SYSTEM_CSI_PORT1_ID,
353	INPUT_SYSTEM_CSI_PORT2_ID,
354
355	INPUT_SYSTEM_PIXELGEN_PORT0_ID,
356	INPUT_SYSTEM_PIXELGEN_PORT1_ID,
357	INPUT_SYSTEM_PIXELGEN_PORT2_ID,
358
359	N_INPUT_SYSTEM_INPUT_PORT_ID
360} input_system_input_port_ID_t;
361
362#define N_INPUT_SYSTEM_CSI_PORT	3
363
364typedef enum {
365	ISYS2401_DMA_CHANNEL_0 = 0,
366	ISYS2401_DMA_CHANNEL_1,
367	ISYS2401_DMA_CHANNEL_2,
368	ISYS2401_DMA_CHANNEL_3,
369	ISYS2401_DMA_CHANNEL_4,
370	ISYS2401_DMA_CHANNEL_5,
371	ISYS2401_DMA_CHANNEL_6,
372	ISYS2401_DMA_CHANNEL_7,
373	ISYS2401_DMA_CHANNEL_8,
374	ISYS2401_DMA_CHANNEL_9,
375	ISYS2401_DMA_CHANNEL_10,
376	ISYS2401_DMA_CHANNEL_11,
377	N_ISYS2401_DMA_CHANNEL
378} isys2401_dma_channel;
379
380#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */
381