1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16#ifndef _SH_CSS_INTERNAL_H_ 17#define _SH_CSS_INTERNAL_H_ 18 19#include <system_global.h> 20#include <math_support.h> 21#include <type_support.h> 22#include <platform_support.h> 23#include <linux/stdarg.h> 24 25#include "input_formatter.h" 26#include "input_system.h" 27 28#include "ia_css_types.h" 29#include "ia_css_acc_types.h" 30#include "ia_css_buffer.h" 31 32#include "ia_css_binary.h" 33#include "sh_css_firmware.h" /* not needed/desired on SP/ISP */ 34#include "sh_css_legacy.h" 35#include "sh_css_defs.h" 36#include "sh_css_uds.h" 37#include "dma.h" /* N_DMA_CHANNEL_ID */ 38#include "ia_css_circbuf_comm.h" /* Circular buffer */ 39#include "ia_css_frame_comm.h" 40#include "ia_css_3a.h" 41#include "ia_css_dvs.h" 42#include "ia_css_metadata.h" 43#include "runtime/bufq/interface/ia_css_bufq.h" 44#include "ia_css_timer.h" 45 46/* TODO: Move to a more suitable place when sp pipeline design is done. */ 47#define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2 48#define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1 49#define IA_CSS_NUM_CBS 2 50#define IA_CSS_CB_MAX_ELEMS 2 51 52/* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or 53 * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively. 54 * TODO: Enforce the limitation above. 55*/ 56#define IA_CSS_COPYSINK_SEM_INDEX 0 57#define IA_CSS_TAGGER_SEM_INDEX 1 58 59/* Force generation of output event. Used by acceleration pipe. */ 60#define IA_CSS_POST_OUT_EVENT_FORCE 2 61 62#define SH_CSS_MAX_BINARY_NAME 64 63 64#define SP_DEBUG_NONE (0) 65#define SP_DEBUG_DUMP (1) 66#define SP_DEBUG_COPY (2) 67#define SP_DEBUG_TRACE (3) 68#define SP_DEBUG_MINIMAL (4) 69 70#define SP_DEBUG SP_DEBUG_NONE 71#define SP_DEBUG_MINIMAL_OVERWRITE 1 72 73#define SH_CSS_TNR_BIT_DEPTH 8 74#define SH_CSS_REF_BIT_DEPTH 8 75 76/* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */ 77#define NUM_CONTINUOUS_FRAMES 15 78#define NUM_MIPI_FRAMES_PER_STREAM 2 79 80#define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2 81 82#define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */ 83 84#define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/ 85#define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF 86 87#define SH_CSS_MAX_SP_THREADS 5 88 89/** 90 * The C99 standard does not specify the exact object representation of structs; 91 * the representation is compiler dependent. 92 * 93 * The structs that are communicated between host and SP/ISP should have the 94 * exact same object representation. The compiler that is used to compile the 95 * firmware is hivecc. 96 * 97 * To check if a different compiler, used to compile a host application, uses 98 * another object representation, macros are defined specifying the size of 99 * the structs as expected by the firmware. 100 * 101 * A host application shall verify that a sizeof( ) of the struct is equal to 102 * the SIZE_OF_XXX macro of the corresponding struct. If they are not 103 * equal, functionality will break. 104 */ 105#define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x) 106#define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32) 107#define SIZE_OF_IA_CSS_PTR sizeof(uint32_t) 108 109/* Number of SP's */ 110#define NUM_OF_SPS 1 111 112#define NUM_OF_BLS 0 113 114/* Enum for order of Binaries */ 115enum sh_css_order_binaries { 116 SP_FIRMWARE = 0, 117 ISP_FIRMWARE 118}; 119 120/* 121* JB: keep next enum in sync with thread id's 122* and pipe id's 123*/ 124enum sh_css_pipe_config_override { 125 SH_CSS_PIPE_CONFIG_OVRD_NONE = 0, 126 SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff 127}; 128 129enum host2sp_commands { 130 host2sp_cmd_error = 0, 131 /* 132 * The host2sp_cmd_ready command is the only command written by the SP 133 * It acknowledges that is previous command has been received. 134 * (this does not mean that the command has been executed) 135 * It also indicates that a new command can be send (it is a queue 136 * with depth 1). 137 */ 138 host2sp_cmd_ready = 1, 139 /* Command written by the Host */ 140 host2sp_cmd_dummy, /* No action, can be used as watchdog */ 141 host2sp_cmd_start_flash, /* Request SP to start the flash */ 142 host2sp_cmd_terminate, /* SP should terminate itself */ 143 N_host2sp_cmd 144}; 145 146/* Enumeration used to indicate the events that are produced by 147 * the SP and consumed by the Host. 148 * 149 * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: 150 * 1) "enum ia_css_event_type" (ia_css_event_public.h) 151 * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) 152 * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) 153 * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) 154 */ 155enum sh_css_sp_event_type { 156 SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE, 157 SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE, 158 SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE, 159 SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE, 160 SH_CSS_SP_EVENT_3A_STATISTICS_DONE, 161 SH_CSS_SP_EVENT_DIS_STATISTICS_DONE, 162 SH_CSS_SP_EVENT_PIPELINE_DONE, 163 SH_CSS_SP_EVENT_FRAME_TAGGED, 164 SH_CSS_SP_EVENT_INPUT_FRAME_DONE, 165 SH_CSS_SP_EVENT_METADATA_DONE, 166 SH_CSS_SP_EVENT_LACE_STATISTICS_DONE, 167 SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE, 168 SH_CSS_SP_EVENT_TIMER, 169 SH_CSS_SP_EVENT_PORT_EOF, 170 SH_CSS_SP_EVENT_FW_WARNING, 171 SH_CSS_SP_EVENT_FW_ASSERT, 172 SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */ 173}; 174 175/* xmem address map allocation per pipeline, css pointers */ 176/* Note that the struct below should only consist of ia_css_ptr-es 177 Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map 178 */ 179struct sh_css_ddr_address_map { 180 ia_css_ptr isp_param; 181 ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; 182 ia_css_ptr macc_tbl; 183 ia_css_ptr fpn_tbl; 184 ia_css_ptr sc_tbl; 185 ia_css_ptr tetra_r_x; 186 ia_css_ptr tetra_r_y; 187 ia_css_ptr tetra_gr_x; 188 ia_css_ptr tetra_gr_y; 189 ia_css_ptr tetra_gb_x; 190 ia_css_ptr tetra_gb_y; 191 ia_css_ptr tetra_b_x; 192 ia_css_ptr tetra_b_y; 193 ia_css_ptr tetra_ratb_x; 194 ia_css_ptr tetra_ratb_y; 195 ia_css_ptr tetra_batr_x; 196 ia_css_ptr tetra_batr_y; 197 ia_css_ptr dvs_6axis_params_y; 198}; 199 200#define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \ 201 (SIZE_OF_HRT_VADDRESS + \ 202 (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \ 203 (16 * SIZE_OF_HRT_VADDRESS)) 204 205/* xmem address map allocation per pipeline */ 206struct sh_css_ddr_address_map_size { 207 size_t isp_param; 208 size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; 209 size_t macc_tbl; 210 size_t fpn_tbl; 211 size_t sc_tbl; 212 size_t tetra_r_x; 213 size_t tetra_r_y; 214 size_t tetra_gr_x; 215 size_t tetra_gr_y; 216 size_t tetra_gb_x; 217 size_t tetra_gb_y; 218 size_t tetra_b_x; 219 size_t tetra_b_y; 220 size_t tetra_ratb_x; 221 size_t tetra_ratb_y; 222 size_t tetra_batr_x; 223 size_t tetra_batr_y; 224 size_t dvs_6axis_params_y; 225}; 226 227struct sh_css_ddr_address_map_compound { 228 struct sh_css_ddr_address_map map; 229 struct sh_css_ddr_address_map_size size; 230}; 231 232struct ia_css_isp_parameter_set_info { 233 struct sh_css_ddr_address_map 234 mem_map;/** pointers to Parameters in ISP format IMPT: 235 This should be first member of this struct */ 236 u32 237 isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */ 238 ia_css_ptr 239 output_frame_ptr;/** Output frame to which this config has to be applied (optional) */ 240}; 241 242/* this struct contains all arguments that can be passed to 243 a binary. It depends on the binary which ones are used. */ 244struct sh_css_binary_args { 245 struct ia_css_frame *in_frame; /* input frame */ 246 const struct ia_css_frame 247 *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */ 248 const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; /* tnr frames */ 249 struct ia_css_frame 250 *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */ 251 struct ia_css_frame *out_vf_frame; /* viewfinder output frame */ 252 bool copy_vf; 253 bool copy_output; 254 unsigned int vf_downscale_log2; 255}; 256 257#if SP_DEBUG == SP_DEBUG_DUMP 258 259#define SH_CSS_NUM_SP_DEBUG 48 260 261struct sh_css_sp_debug_state { 262 unsigned int error; 263 unsigned int debug[SH_CSS_NUM_SP_DEBUG]; 264}; 265 266#elif SP_DEBUG == SP_DEBUG_COPY 267 268#define SH_CSS_SP_DBG_TRACE_DEPTH (40) 269 270struct sh_css_sp_debug_trace { 271 u16 frame; 272 u16 line; 273 u16 pixel_distance; 274 u16 mipi_used_dword; 275 u16 sp_index; 276}; 277 278struct sh_css_sp_debug_state { 279 u16 if_start_line; 280 u16 if_start_column; 281 u16 if_cropped_height; 282 u16 if_cropped_width; 283 unsigned int index; 284 struct sh_css_sp_debug_trace 285 trace[SH_CSS_SP_DBG_TRACE_DEPTH]; 286}; 287 288#elif SP_DEBUG == SP_DEBUG_TRACE 289 290/* Example of just one global trace */ 291#define SH_CSS_SP_DBG_NR_OF_TRACES (1) 292#define SH_CSS_SP_DBG_TRACE_DEPTH (40) 293 294#define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13) 295 296struct sh_css_sp_debug_trace { 297 u16 time_stamp; 298 u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */ 299 u32 data; 300}; 301 302struct sh_css_sp_debug_state { 303 struct sh_css_sp_debug_trace 304 trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH]; 305 u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES]; 306 u8 index[SH_CSS_SP_DBG_NR_OF_TRACES]; 307}; 308 309#elif SP_DEBUG == SP_DEBUG_MINIMAL 310 311#define SH_CSS_NUM_SP_DEBUG 128 312 313struct sh_css_sp_debug_state { 314 unsigned int error; 315 unsigned int debug[SH_CSS_NUM_SP_DEBUG]; 316}; 317 318#endif 319 320struct sh_css_sp_debug_command { 321 /* 322 * The DMA software-mask, 323 * Bit 31...24: unused. 324 * Bit 23...16: unused. 325 * Bit 15...08: reading-request enabling bits for DMA channel 7..0 326 * Bit 07...00: writing-request enabling bits for DMA channel 7..0 327 * 328 * For example, "0...0 0...0 11111011 11111101" indicates that the 329 * writing request through DMA Channel 1 and the reading request 330 * through DMA channel 2 are both disabled. The others are enabled. 331 */ 332 u32 dma_sw_reg; 333}; 334 335/* SP input formatter configuration.*/ 336struct sh_css_sp_input_formatter_set { 337 u32 stream_format; 338 input_formatter_cfg_t config_a; 339 input_formatter_cfg_t config_b; 340}; 341 342#define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3) 343 344/* SP configuration information */ 345struct sh_css_sp_config { 346 u8 no_isp_sync; /* Signal host immediately after start */ 347 u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */ 348 u8 lock_all; 349 /** If raw buffer locking is enabled, this flag indicates whether raw 350 frames are locked when their EOF event is successfully sent to the 351 host (true) or when they are passed to the preview/video pipe 352 (false). */ 353 354 struct { 355 u8 a_changed; 356 u8 b_changed; 357 u8 isp_2ppc; 358 struct sh_css_sp_input_formatter_set 359 set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */ 360 } input_formatter; 361 362 sync_generator_cfg_t sync_gen; 363 tpg_cfg_t tpg; 364 prbs_cfg_t prbs; 365 input_system_cfg_t input_circuit; 366 u8 input_circuit_cfg_changed; 367 u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT]; 368 u8 enable_isys_event_queue; 369 u8 disable_cont_vf; 370}; 371 372enum sh_css_stage_type { 373 SH_CSS_SP_STAGE_TYPE = 0, 374 SH_CSS_ISP_STAGE_TYPE = 1 375}; 376 377#define SH_CSS_NUM_STAGE_TYPES 2 378 379#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0) 380#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \ 381 ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1) 382 383struct sh_css_sp_pipeline_terminal { 384 union { 385 /* Input System 2401 */ 386 virtual_input_system_stream_t 387 virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; 388 } context; 389 /* 390 * TODO 391 * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready. 392 */ 393 union { 394 /* Input System 2401 */ 395 virtual_input_system_stream_cfg_t 396 virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; 397 } ctrl; 398}; 399 400struct sh_css_sp_pipeline_io { 401 struct sh_css_sp_pipeline_terminal input; 402 /* pqiao: comment out temporarily to save dmem */ 403 /*struct sh_css_sp_pipeline_terminal output;*/ 404}; 405 406/* This struct tracks how many streams are registered per CSI port. 407 * This is used to track which streams have already been configured. 408 * Only when all streams are configured, the CSI RX is started for that port. 409 */ 410struct sh_css_sp_pipeline_io_status { 411 u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */ 412 u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */ 413}; 414 415enum sh_css_port_dir { 416 SH_CSS_PORT_INPUT = 0, 417 SH_CSS_PORT_OUTPUT = 1 418}; 419 420enum sh_css_port_type { 421 SH_CSS_HOST_TYPE = 0, 422 SH_CSS_COPYSINK_TYPE = 1, 423 SH_CSS_TAGGERSINK_TYPE = 2 424}; 425 426/* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */ 427#define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4) 428#define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt)) 429#define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0) 430#define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 431#define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 432#define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \ 433 SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt)) 434#define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 435#define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \ 436 (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \ 437 SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE))) 438 439#define IA_CSS_ACQUIRE_ISP_POS 31 440 441/* Flags for metadata processing */ 442#define SH_CSS_METADATA_ENABLED 0x01 443#define SH_CSS_METADATA_PROCESSED 0x02 444#define SH_CSS_METADATA_OFFLINE_MODE 0x04 445#define SH_CSS_METADATA_WAIT_INPUT 0x08 446 447/* @brief Free an array of metadata buffers. 448 * 449 * @param[in] num_bufs Number of metadata buffers to be freed. 450 * @param[in] bufs Pointer of array of metadata buffers. 451 * 452 * This function frees an array of metadata buffers. 453 */ 454void 455ia_css_metadata_free_multiple(unsigned int num_bufs, 456 struct ia_css_metadata **bufs); 457 458/* Macro for handling pipe_qos_config */ 459#define QOS_INVALID (~0U) 460 461/* Information for a pipeline */ 462struct sh_css_sp_pipeline { 463 u32 pipe_id; /* the pipe ID */ 464 u32 pipe_num; /* the dynamic pipe number */ 465 u32 thread_id; /* the sp thread ID */ 466 u32 pipe_config; /* the pipe config */ 467 u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state. 468 (0xFFFFFFFF) indicates non QOS pipe.*/ 469 u32 inout_port_config; 470 u32 required_bds_factor; 471 u32 dvs_frame_delay; 472 u32 input_system_mode; /* enum ia_css_input_mode */ 473 u32 port_id; /* port_id for input system */ 474 u32 num_stages; /* the pipe config */ 475 u32 running; /* needed for pipe termination */ 476 ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES]; 477 ia_css_ptr scaler_pp_lut; /* Early bound LUT */ 478 u32 dummy; /* stage ptr is only used on sp but lives in 479 this struct; needs cleanup */ 480 s32 num_execs; /* number of times to run if this is 481 an acceleration pipe. */ 482 struct { 483 u32 format; /* Metadata format in hrt format */ 484 u32 width; /* Width of a line */ 485 u32 height; /* Number of lines */ 486 u32 stride; /* Stride (in bytes) per line */ 487 u32 size; /* Total size (in bytes) */ 488 ia_css_ptr cont_buf; /* Address of continuous buffer */ 489 } metadata; 490 u32 output_frame_queue_id; 491 union { 492 struct { 493 u32 bytes_available; 494 } bin; 495 struct { 496 u32 height; 497 u32 width; 498 u32 padded_width; 499 u32 max_input_width; 500 u32 raw_bit_depth; 501 } raw; 502 } copy; 503}; 504 505/* 506 * The first frames (with comment Dynamic) can be dynamic or static 507 * The other frames (ref_in and below) can only be static 508 * Static means that the data address will not change during the life time 509 * of the associated pipe. Dynamic means that the data address can 510 * change with every (frame) iteration of the associated pipe 511 * 512 * s3a and dis are now also dynamic but (stil) handled separately 513 */ 514#define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3) 515 516struct ia_css_frames_sp { 517 struct ia_css_frame_sp in; 518 struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; 519 struct ia_css_resolution effective_in_res; 520 struct ia_css_frame_sp out_vf; 521 struct ia_css_frame_sp_info internal_frame_info; 522 struct ia_css_buffer_sp s3a_buf; 523 struct ia_css_buffer_sp dvs_buf; 524 struct ia_css_buffer_sp metadata_buf; 525}; 526 527/* Information for a single pipeline stage for an ISP */ 528struct sh_css_isp_stage { 529 /* 530 * For compatibility and portabilty, only types 531 * from "stdint.h" are allowed 532 * 533 * Use of "enum" and "bool" is prohibited 534 * Multiple boolean flags can be stored in an 535 * integer 536 */ 537 struct ia_css_blob_info blob_info; 538 struct ia_css_binary_info binary_info; 539 char binary_name[SH_CSS_MAX_BINARY_NAME]; 540 struct ia_css_isp_param_css_segments mem_initializers; 541}; 542 543/* Information for a single pipeline stage */ 544struct sh_css_sp_stage { 545 /* 546 * For compatibility and portabilty, only types 547 * from "stdint.h" are allowed 548 * 549 * Use of "enum" and "bool" is prohibited 550 * Multiple boolean flags can be stored in an 551 * integer 552 */ 553 u8 num; /* Stage number */ 554 u8 isp_online; 555 u8 isp_copy_vf; 556 u8 isp_copy_output; 557 u8 sp_enable_xnr; 558 u8 isp_deci_log_factor; 559 u8 isp_vf_downscale_bits; 560 u8 deinterleaved; 561 /* 562 * NOTE: Programming the input circuit can only be done at the 563 * start of a session. It is illegal to program it during execution 564 * The input circuit defines the connectivity 565 */ 566 u8 program_input_circuit; 567 /* enum ia_css_pipeline_stage_sp_func func; */ 568 u8 func; 569 /* The type of the pipe-stage */ 570 /* enum sh_css_stage_type stage_type; */ 571 u8 stage_type; 572 u8 num_stripes; 573 u8 isp_pipe_version; 574 struct { 575 u8 vf_output; 576 u8 s3a; 577 u8 sdis; 578 u8 dvs_stats; 579 u8 lace_stats; 580 } enable; 581 /* Add padding to come to a word boundary */ 582 /* unsigned char padding[0]; */ 583 584 struct sh_css_crop_pos sp_out_crop_pos; 585 struct ia_css_frames_sp frames; 586 struct ia_css_resolution dvs_envelope; 587 struct sh_css_uds_info uds; 588 ia_css_ptr isp_stage_addr; 589 ia_css_ptr xmem_bin_addr; 590 ia_css_ptr xmem_map_addr; 591 592 u16 top_cropping; 593 u16 row_stripes_height; 594 u16 row_stripes_overlap_lines; 595 u8 if_config_index; /* Which should be applied by this stage. */ 596}; 597 598/* 599 * Time: 2012-07-19, 17:40. 600 * Note: Add a new data memeber "debug" in "sh_css_sp_group". This 601 * data member is used to pass the debugging command from the 602 * Host to the SP. 603 * 604 * Time: Before 2012-07-19. 605 * Note: 606 * Group all host initialized SP variables into this struct. 607 * This is initialized every stage through dma. 608 * The stage part itself is transferred through sh_css_sp_stage. 609*/ 610struct sh_css_sp_group { 611 struct sh_css_sp_config config; 612 struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS]; 613 struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS]; 614 struct sh_css_sp_pipeline_io_status pipe_io_status; 615 struct sh_css_sp_debug_command debug; 616}; 617 618/* Data in SP dmem that is set from the host every stage. */ 619struct sh_css_sp_per_frame_data { 620 /* ddr address of sp_group and sp_stage */ 621 ia_css_ptr sp_group_addr; 622}; 623 624#define SH_CSS_NUM_SDW_IRQS 3 625 626/* Output data from SP to css */ 627struct sh_css_sp_output { 628 unsigned int bin_copy_bytes_copied; 629#if SP_DEBUG != SP_DEBUG_NONE 630 struct sh_css_sp_debug_state debug; 631#endif 632 unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS]; 633}; 634 635/** 636 * @brief Data structure for the circular buffer. 637 * The circular buffer is empty if "start == end". The 638 * circular buffer is full if "(end + 1) % size == start". 639 */ 640/* Variable Sized Buffer Queue Elements */ 641 642#define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6 643#define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3 644#define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6 645 646/* sp-to-host queue is expected to be emptied in ISR since 647 * it is used instead of HW interrupts (due to HW design issue). 648 * We need one queue element per CSI port. */ 649#define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) 650/* The host-to-sp queue needs to allow for some delay 651 * in the emptying of this queue in the SP since there is no 652 * separate SP thread for this. */ 653#define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) 654 655#define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13 656#define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19 657#define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */ 658 659struct sh_css_hmm_buffer { 660 union { 661 struct ia_css_isp_3a_statistics s3a; 662 struct ia_css_isp_dvs_statistics dis; 663 ia_css_ptr skc_dvs_statistics; 664 ia_css_ptr lace_stat; 665 struct ia_css_metadata metadata; 666 struct frame_data_wrapper { 667 ia_css_ptr frame_data; 668 u32 flashed; 669 u32 exp_id; 670 u32 isp_parameters_id; /** Unique ID to track which config was 671 actually applied to a particular frame */ 672 } frame; 673 ia_css_ptr ddr_ptrs; 674 } payload; 675 /* 676 * kernel_ptr is present for host administration purposes only. 677 * type is uint64_t in order to be 64-bit host compatible. 678 * uint64_t does not exist on SP/ISP. 679 * Size of the struct is checked by sp.hive.c. 680 */ 681 CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */ 682 u64 kernel_ptr; 683 struct ia_css_time_meas timing_data; 684 clock_value_t isys_eof_clock_tick; 685}; 686 687#define SIZE_OF_FRAME_STRUCT \ 688 (SIZE_OF_HRT_VADDRESS + \ 689 (3 * sizeof(uint32_t))) 690 691#define SIZE_OF_PAYLOAD_UNION \ 692 (MAX(MAX(MAX(MAX( \ 693 SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \ 694 SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \ 695 SIZE_OF_IA_CSS_METADATA_STRUCT), \ 696 SIZE_OF_FRAME_STRUCT), \ 697 SIZE_OF_HRT_VADDRESS)) 698 699/* Do not use sizeof(uint64_t) since that does not exist of SP */ 700#define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \ 701 (SIZE_OF_PAYLOAD_UNION + \ 702 CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \ 703 8 + \ 704 8 + \ 705 SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \ 706 SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \ 707 CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8)) 708 709enum sh_css_queue_type { 710 sh_css_invalid_queue_type = -1, 711 sh_css_host2sp_buffer_queue, 712 sh_css_sp2host_buffer_queue, 713 sh_css_host2sp_psys_event_queue, 714 sh_css_sp2host_psys_event_queue, 715 sh_css_sp2host_isys_event_queue, 716 sh_css_host2sp_isys_event_queue, 717 sh_css_host2sp_tag_cmd_queue, 718}; 719 720struct sh_css_event_irq_mask { 721 u16 or_mask; 722 u16 and_mask; 723}; 724 725#define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \ 726 (2 * sizeof(uint16_t)) 727 728struct host_sp_communication { 729 /* 730 * Don't use enum host2sp_commands, because the sizeof an enum is 731 * compiler dependent and thus non-portable 732 */ 733 u32 host2sp_command; 734 735 /* 736 * The frame buffers that are reused by the 737 * copy pipe in the offline preview mode. 738 * 739 * host2sp_offline_frames[0]: the input frame of the preview pipe. 740 * host2sp_offline_frames[1]: the output frame of the copy pipe. 741 * 742 * TODO: 743 * Remove it when the Host and the SP is decoupled. 744 */ 745 ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES]; 746 ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES]; 747 748 ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; 749 ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; 750 u32 host2sp_num_mipi_frames[N_CSI_PORTS]; 751 u32 host2sp_cont_avail_num_raw_frames; 752 u32 host2sp_cont_extra_num_raw_frames; 753 u32 host2sp_cont_target_num_raw_frames; 754 struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES]; 755 756}; 757 758#define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \ 759 (sizeof(uint32_t) + \ 760 (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \ 761 (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \ 762 ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \ 763 (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT)) 764 765struct host_sp_queues { 766 /* 767 * Queues for the dynamic frame information, 768 * i.e. the "in_frame" buffer, the "out_frame" 769 * buffer and the "vf_out_frame" buffer. 770 */ 771 ia_css_circbuf_desc_t host2sp_buffer_queues_desc 772 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; 773 ia_css_circbuf_elem_t host2sp_buffer_queues_elems 774 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES] 775 [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE]; 776 ia_css_circbuf_desc_t sp2host_buffer_queues_desc 777 [SH_CSS_MAX_NUM_QUEUES]; 778 ia_css_circbuf_elem_t sp2host_buffer_queues_elems 779 [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE]; 780 781 /* 782 * The queues for the events. 783 */ 784 ia_css_circbuf_desc_t host2sp_psys_event_queue_desc; 785 786 ia_css_circbuf_elem_t host2sp_psys_event_queue_elems 787 [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE]; 788 ia_css_circbuf_desc_t sp2host_psys_event_queue_desc; 789 790 ia_css_circbuf_elem_t sp2host_psys_event_queue_elems 791 [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE]; 792 793 /* 794 * The queues for the ISYS events. 795 */ 796 ia_css_circbuf_desc_t host2sp_isys_event_queue_desc; 797 798 ia_css_circbuf_elem_t host2sp_isys_event_queue_elems 799 [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE]; 800 ia_css_circbuf_desc_t sp2host_isys_event_queue_desc; 801 802 ia_css_circbuf_elem_t sp2host_isys_event_queue_elems 803 [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE]; 804 /* 805 * The queue for the tagger commands. 806 * CHECK: are these last two present on the 2401 ? 807 */ 808 ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc; 809 810 ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems 811 [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE]; 812}; 813 814#define SIZE_OF_QUEUES_ELEMS \ 815 (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \ 816 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \ 817 (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \ 818 (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \ 819 (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \ 820 (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \ 821 (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \ 822 (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE))) 823 824#define IA_CSS_NUM_CIRCBUF_DESCS 5 825 826#define SIZE_OF_QUEUES_DESC \ 827 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \ 828 SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ 829 (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ 830 (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT)) 831 832#define SIZE_OF_HOST_SP_QUEUES_STRUCT \ 833 (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC) 834 835extern int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args); 836 837static inline void __printf(1, 2) sh_css_print(const char *fmt, ...) 838{ 839 va_list ap; 840 841 if (sh_css_printf) { 842 va_start(ap, fmt); 843 sh_css_printf(fmt, ap); 844 va_end(ap); 845 } 846} 847 848static inline void __printf(1, 0) sh_css_vprint(const char *fmt, va_list args) 849{ 850 if (sh_css_printf) 851 sh_css_printf(fmt, args); 852} 853 854/* The following #if is there because this header file is also included 855 by SP and ISP code but they do not need this data and HIVECC has alignment 856 issue with the firmware struct/union's. 857 More permanent solution will be to refactor this include. 858*/ 859ia_css_ptr sh_css_params_ddr_address_map(void); 860 861int 862sh_css_params_init(void); 863 864void 865sh_css_params_uninit(void); 866 867void 868sh_css_binary_args_reset(struct sh_css_binary_args *args); 869 870/* Check two frames for equality (format, resolution, bits per element) */ 871bool 872sh_css_frame_equal_types(const struct ia_css_frame *frame_a, 873 const struct ia_css_frame *frame_b); 874 875bool 876sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a, 877 const struct ia_css_frame_info *info_b); 878 879void 880sh_css_capture_enable_bayer_downscaling(bool enable); 881 882void 883sh_css_binary_print(const struct ia_css_binary *binary); 884 885/* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement. 886 When 0, no extra alignment is done. */ 887void 888sh_css_frame_info_set_width(struct ia_css_frame_info *info, 889 unsigned int width, 890 unsigned int aligned); 891 892 893unsigned int 894sh_css_get_mipi_sizes_for_check(const unsigned int port, 895 const unsigned int idx); 896 897 898ia_css_ptr 899sh_css_store_sp_group_to_ddr(void); 900 901ia_css_ptr 902sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage); 903 904ia_css_ptr 905sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage); 906 907void 908sh_css_update_uds_and_crop_info( 909 const struct ia_css_binary_info *info, 910 const struct ia_css_frame_info *in_frame_info, 911 const struct ia_css_frame_info *out_frame_info, 912 const struct ia_css_resolution *dvs_env, 913 const struct ia_css_dz_config *zoom, 914 const struct ia_css_vector *motion_vector, 915 struct sh_css_uds_info *uds, /* out */ 916 struct sh_css_crop_pos *sp_out_crop_pos, /* out */ 917 918 bool enable_zoom 919); 920 921void 922sh_css_invalidate_shading_tables(struct ia_css_stream *stream); 923 924struct ia_css_pipeline * 925ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe); 926 927unsigned int 928ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe); 929 930unsigned int 931ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe); 932 933bool 934sh_css_continuous_is_enabled(uint8_t pipe_num); 935 936struct ia_css_pipe * 937find_pipe_by_num(uint32_t pipe_num); 938 939void 940ia_css_get_crop_offsets( 941 struct ia_css_pipe *pipe, 942 struct ia_css_frame_info *in_frame); 943 944#endif /* _SH_CSS_INTERNAL_H_ */ 945