1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __INPUT_SYSTEM_2400_PUBLIC_H_INCLUDED__
17#define __INPUT_SYSTEM_2400_PUBLIC_H_INCLUDED__
18
19#include <type_support.h>
20
21/*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID]
22
23 \param	ID[in]				RECEIVER identifier
24 \param	cfg_ID[in]			Configuration identifier
25 \param	comp[in]			Compression method
26 \param	pred[in]			Predictor method
27
28 \NOTE: the storage of compression configuration is
29	implementation specific. The config can be
30	carried either on MIPI ports or on MIPI channels
31
32 \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred}
33 */
34void receiver_set_compression(
35    const rx_ID_t				ID,
36    const unsigned int			cfg_ID,
37    const mipi_compressor_t		comp,
38    const mipi_predictor_t		pred);
39
40/*! Enable PORT[port_ID] of RECEIVER[ID]
41
42 \param	ID[in]				RECEIVER identifier
43 \param	port_ID[in]			mipi PORT identifier
44 \param	cnd[in]				irq predicate
45
46 \return None, enable(RECEIVER[ID].PORT[port_ID])
47 */
48void receiver_port_enable(
49    const rx_ID_t				ID,
50    const enum mipi_port_id		port_ID,
51    const bool					cnd);
52
53/*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled
54
55 \param	ID[in]				RECEIVER identifier
56 \param	port_ID[in]			mipi PORT identifier
57
58 \return enable(RECEIVER[ID].PORT[port_ID]) == true
59 */
60bool is_receiver_port_enabled(
61    const rx_ID_t				ID,
62    const enum mipi_port_id		port_ID);
63
64/*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID]
65
66 \param	ID[in]				RECEIVER identifier
67 \param	port_ID[in]			mipi PORT identifier
68 \param	irq_info[in]		irq channels
69
70 \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info)
71 */
72void receiver_irq_enable(
73    const rx_ID_t				ID,
74    const enum mipi_port_id		port_ID,
75    const rx_irq_info_t			irq_info);
76
77/*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID]
78
79 \param	ID[in]				RECEIVER identifier
80 \param	port_ID[in]			mipi PORT identifier
81
82 \return RECEIVER[ID].PORT[port_ID].irq_info
83 */
84rx_irq_info_t receiver_get_irq_info(
85    const rx_ID_t				ID,
86    const enum mipi_port_id		port_ID);
87
88/*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID]
89
90 \param	ID[in]				RECEIVER identifier
91 \param	port_ID[in]			mipi PORT identifier
92 \param	irq_info[in]		irq status
93
94 \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info)
95 */
96void receiver_irq_clear(
97    const rx_ID_t				ID,
98    const enum mipi_port_id			port_ID,
99    const rx_irq_info_t			irq_info);
100
101/*! Write to a control register of INPUT_SYSTEM[ID]
102
103 \param	ID[in]				INPUT_SYSTEM identifier
104 \param	reg[in]				register index
105 \param value[in]			The data to be written
106
107 \return none, INPUT_SYSTEM[ID].ctrl[reg] = value
108 */
109STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store(
110    const input_system_ID_t			ID,
111    const hrt_address			reg,
112    const hrt_data				value);
113
114/*! Read from a control register of INPUT_SYSTEM[ID]
115
116 \param	ID[in]				INPUT_SYSTEM identifier
117 \param	reg[in]				register index
118 \param value[in]			The data to be written
119
120 \return INPUT_SYSTEM[ID].ctrl[reg]
121 */
122STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load(
123    const input_system_ID_t			ID,
124    const hrt_address			reg);
125
126/*! Write to a control register of RECEIVER[ID]
127
128 \param	ID[in]				RECEIVER identifier
129 \param	reg[in]				register index
130 \param value[in]			The data to be written
131
132 \return none, RECEIVER[ID].ctrl[reg] = value
133 */
134STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store(
135    const rx_ID_t				ID,
136    const hrt_address			reg,
137    const hrt_data				value);
138
139/*! Read from a control register of RECEIVER[ID]
140
141 \param	ID[in]				RECEIVER identifier
142 \param	reg[in]				register index
143 \param value[in]			The data to be written
144
145 \return RECEIVER[ID].ctrl[reg]
146 */
147STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load(
148    const rx_ID_t				ID,
149    const hrt_address			reg);
150
151/*! Write to a control register of PORT[port_ID] of RECEIVER[ID]
152
153 \param	ID[in]				RECEIVER identifier
154 \param	port_ID[in]			mipi PORT identifier
155 \param	reg[in]				register index
156 \param value[in]			The data to be written
157
158 \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value
159 */
160STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store(
161    const rx_ID_t				ID,
162    const enum mipi_port_id			port_ID,
163    const hrt_address			reg,
164    const hrt_data				value);
165
166/*! Read from a control register PORT[port_ID] of RECEIVER[ID]
167
168 \param	ID[in]				RECEIVER identifier
169 \param	port_ID[in]			mipi PORT identifier
170 \param	reg[in]				register index
171 \param value[in]			The data to be written
172
173 \return RECEIVER[ID].PORT[port_ID].ctrl[reg]
174 */
175STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load(
176    const rx_ID_t				ID,
177    const enum mipi_port_id		port_ID,
178    const hrt_address			reg);
179
180/*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
181
182 \param	ID[in]				INPUT_SYSTEM identifier
183 \param	port_ID[in]			sub system identifier
184 \param	reg[in]				register index
185 \param value[in]			The data to be written
186
187 \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value
188 */
189STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store(
190    const input_system_ID_t			ID,
191    const sub_system_ID_t			sub_ID,
192    const hrt_address			reg,
193    const hrt_data				value);
194
195/*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
196
197 \param	ID[in]				INPUT_SYSTEM identifier
198 \param	port_ID[in]			sub system identifier
199 \param	reg[in]				register index
200 \param value[in]			The data to be written
201
202 \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg]
203 */
204STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load(
205    const input_system_ID_t		ID,
206    const sub_system_ID_t		sub_ID,
207    const hrt_address			reg);
208
209///////////////////////////////////////////////////////////////////////////
210//
211//    Functions for configuration phase on input system.
212//
213///////////////////////////////////////////////////////////////////////////
214
215// Function that resets current configuration.
216// remove the argument since it should be private.
217input_system_err_t input_system_configuration_reset(void);
218
219// Function that commits current configuration.
220// remove the argument since it should be private.
221input_system_err_t input_system_configuration_commit(void);
222
223///////////////////////////////////////////////////////////////////////////
224//
225// User functions:
226//		(encoded generic function)
227//    - no checking
228//    - decoding name and agruments into the generic (channel) configuration
229//    function.
230//
231///////////////////////////////////////////////////////////////////////////
232
233// FIFO channel config function user
234
235input_system_err_t	input_system_csi_fifo_channel_cfg(
236    u32				ch_id,
237    input_system_csi_port_t	port,
238    backend_channel_cfg_t	backend_ch,
239    target_cfg2400_t			target
240);
241
242input_system_err_t	input_system_csi_fifo_channel_with_counting_cfg(
243    u32				ch_id,
244    u32				nof_frame,
245    input_system_csi_port_t	port,
246    backend_channel_cfg_t	backend_ch,
247    u32				mem_region_size,
248    u32				nof_mem_regions,
249    target_cfg2400_t			target
250);
251
252// SRAM channel config function user
253
254input_system_err_t	input_system_csi_sram_channel_cfg(
255    u32				ch_id,
256    input_system_csi_port_t	port,
257    backend_channel_cfg_t	backend_ch,
258    u32				csi_mem_region_size,
259    u32				csi_nof_mem_regions,
260    target_cfg2400_t			target
261);
262
263//XMEM channel config function user
264
265input_system_err_t	input_system_csi_xmem_channel_cfg(
266    u32				ch_id,
267    input_system_csi_port_t port,
268    backend_channel_cfg_t	backend_ch,
269    u32				mem_region_size,
270    u32				nof_mem_regions,
271    u32				acq_mem_region_size,
272    u32				acq_nof_mem_regions,
273    target_cfg2400_t			target,
274    uint32_t				nof_xmem_buffers
275);
276
277input_system_err_t	input_system_csi_xmem_capture_only_channel_cfg(
278    u32				ch_id,
279    u32				nof_frames,
280    input_system_csi_port_t port,
281    u32				csi_mem_region_size,
282    u32				csi_nof_mem_regions,
283    u32				acq_mem_region_size,
284    u32				acq_nof_mem_regions,
285    target_cfg2400_t			target
286);
287
288input_system_err_t	input_system_csi_xmem_acquire_only_channel_cfg(
289    u32				ch_id,
290    u32				nof_frames,
291    input_system_csi_port_t port,
292    backend_channel_cfg_t	backend_ch,
293    u32				acq_mem_region_size,
294    u32				acq_nof_mem_regions,
295    target_cfg2400_t			target
296);
297
298// Non - CSI channel config function user
299
300input_system_err_t	input_system_prbs_channel_cfg(
301    u32		ch_id,
302    u32		nof_frames,
303    u32		seed,
304    u32		sync_gen_width,
305    u32		sync_gen_height,
306    u32		sync_gen_hblank_cycles,
307    u32		sync_gen_vblank_cycles,
308    target_cfg2400_t	target
309);
310
311input_system_err_t	input_system_tpg_channel_cfg(
312    u32		ch_id,
313    u32		nof_frames,//not used yet
314    u32		x_mask,
315    u32		y_mask,
316    u32		x_delta,
317    u32		y_delta,
318    u32		xy_mask,
319    u32		sync_gen_width,
320    u32		sync_gen_height,
321    u32		sync_gen_hblank_cycles,
322    u32		sync_gen_vblank_cycles,
323    target_cfg2400_t	target
324);
325
326input_system_err_t	input_system_gpfifo_channel_cfg(
327    u32		ch_id,
328    u32		nof_frames,
329    target_cfg2400_t	target
330);
331
332#endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */
333