1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16#ifndef __IA_CSS_EED1_8_PARAM_H 17#define __IA_CSS_EED1_8_PARAM_H 18 19#include "type_support.h" 20#include "vmem.h" /* needed for VMEM_ARRAY */ 21 22#include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */ 23 24/* Configuration parameters: */ 25 26/* Enable median for false color correction 27 * 0: Do not use median 28 * 1: Use median 29 * Default: 1 30 */ 31#define EED1_8_FC_ENABLE_MEDIAN 1 32 33/* Coring Threshold minima 34 * Used in Tint color suppression. 35 * Default: 1 36 */ 37#define EED1_8_CORINGTHMIN 1 38 39/* Define size of the state..... TODO: check if this is the correct place */ 40/* 4 planes : GR, R, B, GB */ 41#define NUM_PLANES 4 42 43/* 5 lines state per color plane input_line_state */ 44#define EED1_8_STATE_INPUT_BUFFER_HEIGHT (5 * NUM_PLANES) 45 46/* Each plane has width equal to half frame line */ 47#define EED1_8_STATE_INPUT_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 48 49/* 1 line state per color plane LD_H state */ 50#define EED1_8_STATE_LD_H_HEIGHT (1 * NUM_PLANES) 51#define EED1_8_STATE_LD_H_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 52 53/* 1 line state per color plane LD_V state */ 54#define EED1_8_STATE_LD_V_HEIGHT (1 * NUM_PLANES) 55#define EED1_8_STATE_LD_V_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 56 57/* 1 line (single plane) state for D_Hr state */ 58#define EED1_8_STATE_D_HR_HEIGHT 1 59#define EED1_8_STATE_D_HR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 60 61/* 1 line (single plane) state for D_Hb state */ 62#define EED1_8_STATE_D_HB_HEIGHT 1 63#define EED1_8_STATE_D_HB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 64 65/* 2 lines (single plane) state for D_Vr state */ 66#define EED1_8_STATE_D_VR_HEIGHT 2 67#define EED1_8_STATE_D_VR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 68 69/* 2 line (single plane) state for D_Vb state */ 70#define EED1_8_STATE_D_VB_HEIGHT 2 71#define EED1_8_STATE_D_VB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 72 73/* 2 lines state for R and B (= 2 planes) rb_zipped_state */ 74#define EED1_8_STATE_RB_ZIPPED_HEIGHT (2 * 2) 75#define EED1_8_STATE_RB_ZIPPED_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 76 77#if EED1_8_FC_ENABLE_MEDIAN 78/* 1 full input line (GR-R color line) for Yc state */ 79#define EED1_8_STATE_YC_HEIGHT 1 80#define EED1_8_STATE_YC_WIDTH MAX_FRAME_SIMDWIDTH 81 82/* 1 line state per color plane Cg_state */ 83#define EED1_8_STATE_CG_HEIGHT (1 * NUM_PLANES) 84#define EED1_8_STATE_CG_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 85 86/* 1 line state per color plane Co_state */ 87#define EED1_8_STATE_CO_HEIGHT (1 * NUM_PLANES) 88#define EED1_8_STATE_CO_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 89 90/* 1 full input line (GR-R color line) for AbsK state */ 91#define EED1_8_STATE_ABSK_HEIGHT 1 92#define EED1_8_STATE_ABSK_WIDTH MAX_FRAME_SIMDWIDTH 93#endif 94 95struct eed1_8_vmem_params { 96 VMEM_ARRAY(e_dew_enh_x, ISP_VEC_NELEMS); 97 VMEM_ARRAY(e_dew_enh_y, ISP_VEC_NELEMS); 98 VMEM_ARRAY(e_dew_enh_a, ISP_VEC_NELEMS); 99 VMEM_ARRAY(e_dew_enh_f, ISP_VEC_NELEMS); 100 VMEM_ARRAY(chgrinv_x, ISP_VEC_NELEMS); 101 VMEM_ARRAY(chgrinv_a, ISP_VEC_NELEMS); 102 VMEM_ARRAY(chgrinv_b, ISP_VEC_NELEMS); 103 VMEM_ARRAY(chgrinv_c, ISP_VEC_NELEMS); 104 VMEM_ARRAY(fcinv_x, ISP_VEC_NELEMS); 105 VMEM_ARRAY(fcinv_a, ISP_VEC_NELEMS); 106 VMEM_ARRAY(fcinv_b, ISP_VEC_NELEMS); 107 VMEM_ARRAY(fcinv_c, ISP_VEC_NELEMS); 108 VMEM_ARRAY(tcinv_x, ISP_VEC_NELEMS); 109 VMEM_ARRAY(tcinv_a, ISP_VEC_NELEMS); 110 VMEM_ARRAY(tcinv_b, ISP_VEC_NELEMS); 111 VMEM_ARRAY(tcinv_c, ISP_VEC_NELEMS); 112}; 113 114/* EED (Edge Enhancing Demosaic) ISP parameters */ 115struct eed1_8_dmem_params { 116 s32 rbzp_strength; 117 118 s32 fcstrength; 119 s32 fcthres_0; 120 s32 fc_sat_coef; 121 s32 fc_coring_prm; 122 s32 fc_slope; 123 124 s32 aerel_thres0; 125 s32 aerel_gain0; 126 s32 aerel_thres_diff; 127 s32 aerel_gain_diff; 128 129 s32 derel_thres0; 130 s32 derel_gain0; 131 s32 derel_thres_diff; 132 s32 derel_gain_diff; 133 134 s32 coring_pos0; 135 s32 coring_pos_diff; 136 s32 coring_neg0; 137 s32 coring_neg_diff; 138 139 s32 gain_exp; 140 s32 gain_pos0; 141 s32 gain_pos_diff; 142 s32 gain_neg0; 143 s32 gain_neg_diff; 144 145 s32 margin_pos0; 146 s32 margin_pos_diff; 147 s32 margin_neg0; 148 s32 margin_neg_diff; 149 150 s32 e_dew_enh_asr; 151 s32 dedgew_max; 152}; 153 154#endif /* __IA_CSS_EED1_8_PARAM_H */ 155