1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 * Author: Ray Liu <ray.liu@airoha.com> 6 */ 7 8#include <linux/bitfield.h> 9#include <linux/clk.h> 10#include <linux/delay.h> 11#include <linux/device.h> 12#include <linux/dma-mapping.h> 13#include <linux/errno.h> 14#include <linux/limits.h> 15#include <linux/math.h> 16#include <linux/minmax.h> 17#include <linux/module.h> 18#include <linux/mutex.h> 19#include <linux/platform_device.h> 20#include <linux/property.h> 21#include <linux/regmap.h> 22#include <linux/sizes.h> 23#include <linux/spi/spi.h> 24#include <linux/spi/spi-mem.h> 25#include <linux/types.h> 26#include <asm/unaligned.h> 27 28/* SPI */ 29#define REG_SPI_CTRL_BASE 0x1FA10000 30 31#define REG_SPI_CTRL_READ_MODE 0x0000 32#define REG_SPI_CTRL_READ_IDLE_EN 0x0004 33#define REG_SPI_CTRL_SIDLY 0x0008 34#define REG_SPI_CTRL_CSHEXT 0x000c 35#define REG_SPI_CTRL_CSLEXT 0x0010 36 37#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014 38#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0) 39 40#define REG_SPI_CTRL_RDCTL_FSM 0x0018 41#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0) 42 43#define REG_SPI_CTRL_MACMUX_SEL 0x001c 44 45#define REG_SPI_CTRL_MANUAL_EN 0x0020 46#define SPI_CTRL_MANUAL_EN BIT(0) 47 48#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024 49#define SPI_CTRL_OPFIFO_EMPTY BIT(0) 50 51#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028 52#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0) 53#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9) 54 55#define REG_SPI_CTRL_OPFIFO_FULL 0x002c 56#define SPI_CTRL_OPFIFO_FULL BIT(0) 57 58#define REG_SPI_CTRL_OPFIFO_WR 0x0030 59#define SPI_CTRL_OPFIFO_WR BIT(0) 60 61#define REG_SPI_CTRL_DFIFO_FULL 0x0034 62#define SPI_CTRL_DFIFO_FULL BIT(0) 63 64#define REG_SPI_CTRL_DFIFO_WDATA 0x0038 65#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0) 66 67#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c 68#define SPI_CTRL_DFIFO_EMPTY BIT(0) 69 70#define REG_SPI_CTRL_DFIFO_RD 0x0040 71#define SPI_CTRL_DFIFO_RD BIT(0) 72 73#define REG_SPI_CTRL_DFIFO_RDATA 0x0044 74#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0) 75 76#define REG_SPI_CTRL_DUMMY 0x0080 77#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0) 78 79#define REG_SPI_CTRL_PROBE_SEL 0x0088 80#define REG_SPI_CTRL_INTERRUPT 0x0090 81#define REG_SPI_CTRL_INTERRUPT_EN 0x0094 82#define REG_SPI_CTRL_SI_CK_SEL 0x009c 83#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c 84#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110 85#define REG_SPI_CTRL_SFC_STRAP 0x0114 86 87#define REG_SPI_CTRL_NFI2SPI_EN 0x0130 88#define SPI_CTRL_NFI2SPI_EN BIT(0) 89 90/* NFI2SPI */ 91#define REG_SPI_NFI_CNFG 0x0000 92#define SPI_NFI_DMA_MODE BIT(0) 93#define SPI_NFI_READ_MODE BIT(1) 94#define SPI_NFI_DMA_BURST_EN BIT(2) 95#define SPI_NFI_HW_ECC_EN BIT(8) 96#define SPI_NFI_AUTO_FDM_EN BIT(9) 97#define SPI_NFI_OPMODE GENMASK(14, 12) 98 99#define REG_SPI_NFI_PAGEFMT 0x0004 100#define SPI_NFI_PAGE_SIZE GENMASK(1, 0) 101#define SPI_NFI_SPARE_SIZE GENMASK(5, 4) 102 103#define REG_SPI_NFI_CON 0x0008 104#define SPI_NFI_FIFO_FLUSH BIT(0) 105#define SPI_NFI_RST BIT(1) 106#define SPI_NFI_RD_TRIG BIT(8) 107#define SPI_NFI_WR_TRIG BIT(9) 108#define SPI_NFI_SEC_NUM GENMASK(15, 12) 109 110#define REG_SPI_NFI_INTR_EN 0x0010 111#define SPI_NFI_RD_DONE_EN BIT(0) 112#define SPI_NFI_WR_DONE_EN BIT(1) 113#define SPI_NFI_RST_DONE_EN BIT(2) 114#define SPI_NFI_ERASE_DONE_EN BIT(3) 115#define SPI_NFI_BUSY_RETURN_EN BIT(4) 116#define SPI_NFI_ACCESS_LOCK_EN BIT(5) 117#define SPI_NFI_AHB_DONE_EN BIT(6) 118#define SPI_NFI_ALL_IRQ_EN \ 119 (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \ 120 SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \ 121 SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \ 122 SPI_NFI_AHB_DONE_EN) 123 124#define REG_SPI_NFI_INTR 0x0014 125#define SPI_NFI_AHB_DONE BIT(6) 126 127#define REG_SPI_NFI_CMD 0x0020 128 129#define REG_SPI_NFI_ADDR_NOB 0x0030 130#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4) 131 132#define REG_SPI_NFI_STA 0x0060 133#define REG_SPI_NFI_FIFOSTA 0x0064 134#define REG_SPI_NFI_STRADDR 0x0080 135#define REG_SPI_NFI_FDM0L 0x00a0 136#define REG_SPI_NFI_FDM0M 0x00a4 137#define REG_SPI_NFI_FDM7L 0x00d8 138#define REG_SPI_NFI_FDM7M 0x00dc 139#define REG_SPI_NFI_FIFODATA0 0x0190 140#define REG_SPI_NFI_FIFODATA1 0x0194 141#define REG_SPI_NFI_FIFODATA2 0x0198 142#define REG_SPI_NFI_FIFODATA3 0x019c 143#define REG_SPI_NFI_MASTERSTA 0x0224 144 145#define REG_SPI_NFI_SECCUS_SIZE 0x022c 146#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0) 147#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16) 148 149#define REG_SPI_NFI_RD_CTL2 0x0510 150#define REG_SPI_NFI_RD_CTL3 0x0514 151 152#define REG_SPI_NFI_PG_CTL1 0x0524 153#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8) 154 155#define REG_SPI_NFI_PG_CTL2 0x0528 156#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c 157#define REG_SPI_NFI_NOR_RD_ADDR 0x0534 158 159#define REG_SPI_NFI_SNF_MISC_CTL 0x0538 160#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16) 161 162#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c 163#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0) 164#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16) 165 166#define REG_SPI_NFI_SNF_STA_CTL1 0x0550 167#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25) 168#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26) 169 170#define REG_SPI_NFI_SNF_STA_CTL2 0x0554 171 172#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c 173#define SPI_NFI_SPI_MODE BIT(0) 174 175/* SPI NAND Protocol OP */ 176#define SPI_NAND_OP_GET_FEATURE 0x0f 177#define SPI_NAND_OP_SET_FEATURE 0x1f 178#define SPI_NAND_OP_PAGE_READ 0x13 179#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03 180#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b 181#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b 182#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b 183#define SPI_NAND_OP_WRITE_ENABLE 0x06 184#define SPI_NAND_OP_WRITE_DISABLE 0x04 185#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02 186#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32 187#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84 188#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34 189#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10 190#define SPI_NAND_OP_READ_ID 0x9f 191#define SPI_NAND_OP_BLOCK_ERASE 0xd8 192#define SPI_NAND_OP_RESET 0xff 193#define SPI_NAND_OP_DIE_SELECT 0xc2 194 195#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256) 196#define SPI_MAX_TRANSFER_SIZE 511 197 198enum airoha_snand_mode { 199 SPI_MODE_AUTO, 200 SPI_MODE_MANUAL, 201 SPI_MODE_DMA, 202}; 203 204enum airoha_snand_cs { 205 SPI_CHIP_SEL_HIGH, 206 SPI_CHIP_SEL_LOW, 207}; 208 209struct airoha_snand_dev { 210 size_t buf_len; 211 212 u8 *txrx_buf; 213 dma_addr_t dma_addr; 214 215 u64 cur_page_num; 216 bool data_need_update; 217}; 218 219struct airoha_snand_ctrl { 220 struct device *dev; 221 struct regmap *regmap_ctrl; 222 struct regmap *regmap_nfi; 223 struct clk *spi_clk; 224 225 struct { 226 size_t page_size; 227 size_t sec_size; 228 u8 sec_num; 229 u8 spare_size; 230 } nfi_cfg; 231}; 232 233static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl, 234 u8 op_cmd, int op_len) 235{ 236 int err; 237 u32 val; 238 239 err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA, 240 FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) | 241 FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd)); 242 if (err) 243 return err; 244 245 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl, 246 REG_SPI_CTRL_OPFIFO_FULL, 247 val, !(val & SPI_CTRL_OPFIFO_FULL), 248 0, 250 * USEC_PER_MSEC); 249 if (err) 250 return err; 251 252 err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR, 253 SPI_CTRL_OPFIFO_WR); 254 if (err) 255 return err; 256 257 return regmap_read_poll_timeout(as_ctrl->regmap_ctrl, 258 REG_SPI_CTRL_OPFIFO_EMPTY, 259 val, (val & SPI_CTRL_OPFIFO_EMPTY), 260 0, 250 * USEC_PER_MSEC); 261} 262 263static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs) 264{ 265 return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs)); 266} 267 268static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl, 269 const u8 *data, int len) 270{ 271 int i; 272 273 for (i = 0; i < len; i++) { 274 int err; 275 u32 val; 276 277 /* 1. Wait until dfifo is not full */ 278 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl, 279 REG_SPI_CTRL_DFIFO_FULL, val, 280 !(val & SPI_CTRL_DFIFO_FULL), 281 0, 250 * USEC_PER_MSEC); 282 if (err) 283 return err; 284 285 /* 2. Write data to register DFIFO_WDATA */ 286 err = regmap_write(as_ctrl->regmap_ctrl, 287 REG_SPI_CTRL_DFIFO_WDATA, 288 FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i])); 289 if (err) 290 return err; 291 292 /* 3. Wait until dfifo is not full */ 293 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl, 294 REG_SPI_CTRL_DFIFO_FULL, val, 295 !(val & SPI_CTRL_DFIFO_FULL), 296 0, 250 * USEC_PER_MSEC); 297 if (err) 298 return err; 299 } 300 301 return 0; 302} 303 304static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl, 305 u8 *ptr, int len) 306{ 307 int i; 308 309 for (i = 0; i < len; i++) { 310 int err; 311 u32 val; 312 313 /* 1. wait until dfifo is not empty */ 314 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl, 315 REG_SPI_CTRL_DFIFO_EMPTY, val, 316 !(val & SPI_CTRL_DFIFO_EMPTY), 317 0, 250 * USEC_PER_MSEC); 318 if (err) 319 return err; 320 321 /* 2. read from dfifo to register DFIFO_RDATA */ 322 err = regmap_read(as_ctrl->regmap_ctrl, 323 REG_SPI_CTRL_DFIFO_RDATA, &val); 324 if (err) 325 return err; 326 327 ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val); 328 /* 3. enable register DFIFO_RD to read next byte */ 329 err = regmap_write(as_ctrl->regmap_ctrl, 330 REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD); 331 if (err) 332 return err; 333 } 334 335 return 0; 336} 337 338static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl, 339 enum airoha_snand_mode mode) 340{ 341 int err; 342 343 switch (mode) { 344 case SPI_MODE_MANUAL: { 345 u32 val; 346 347 err = regmap_write(as_ctrl->regmap_ctrl, 348 REG_SPI_CTRL_NFI2SPI_EN, 0); 349 if (err) 350 return err; 351 352 err = regmap_write(as_ctrl->regmap_ctrl, 353 REG_SPI_CTRL_READ_IDLE_EN, 0); 354 if (err) 355 return err; 356 357 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl, 358 REG_SPI_CTRL_RDCTL_FSM, val, 359 !(val & SPI_CTRL_RDCTL_FSM), 360 0, 250 * USEC_PER_MSEC); 361 if (err) 362 return err; 363 364 err = regmap_write(as_ctrl->regmap_ctrl, 365 REG_SPI_CTRL_MTX_MODE_TOG, 9); 366 if (err) 367 return err; 368 369 err = regmap_write(as_ctrl->regmap_ctrl, 370 REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN); 371 if (err) 372 return err; 373 break; 374 } 375 case SPI_MODE_DMA: 376 err = regmap_write(as_ctrl->regmap_ctrl, 377 REG_SPI_CTRL_NFI2SPI_EN, 378 SPI_CTRL_MANUAL_EN); 379 if (err < 0) 380 return err; 381 382 err = regmap_write(as_ctrl->regmap_ctrl, 383 REG_SPI_CTRL_MTX_MODE_TOG, 0x0); 384 if (err < 0) 385 return err; 386 387 err = regmap_write(as_ctrl->regmap_ctrl, 388 REG_SPI_CTRL_MANUAL_EN, 0x0); 389 if (err < 0) 390 return err; 391 break; 392 case SPI_MODE_AUTO: 393 default: 394 break; 395 } 396 397 return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0); 398} 399 400static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd, 401 const u8 *data, int len) 402{ 403 int i, data_len; 404 405 for (i = 0; i < len; i += data_len) { 406 int err; 407 408 data_len = min(len, SPI_MAX_TRANSFER_SIZE); 409 err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len); 410 if (err) 411 return err; 412 413 err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i], 414 data_len); 415 if (err < 0) 416 return err; 417 } 418 419 return 0; 420} 421 422static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data, 423 int len) 424{ 425 int i, data_len; 426 427 for (i = 0; i < len; i += data_len) { 428 int err; 429 430 data_len = min(len, SPI_MAX_TRANSFER_SIZE); 431 err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len); 432 if (err) 433 return err; 434 435 err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i], 436 data_len); 437 if (err < 0) 438 return err; 439 } 440 441 return 0; 442} 443 444static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl) 445{ 446 int err; 447 448 /* switch to SNFI mode */ 449 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG, 450 SPI_NFI_SPI_MODE); 451 if (err) 452 return err; 453 454 /* Enable DMA */ 455 return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN, 456 SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN); 457} 458 459static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl) 460{ 461 int err; 462 u32 val; 463 464 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 465 SPI_NFI_FIFO_FLUSH | SPI_NFI_RST); 466 if (err) 467 return err; 468 469 /* auto FDM */ 470 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 471 SPI_NFI_AUTO_FDM_EN); 472 if (err) 473 return err; 474 475 /* HW ECC */ 476 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 477 SPI_NFI_HW_ECC_EN); 478 if (err) 479 return err; 480 481 /* DMA Burst */ 482 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 483 SPI_NFI_DMA_BURST_EN); 484 if (err) 485 return err; 486 487 /* page format */ 488 switch (as_ctrl->nfi_cfg.spare_size) { 489 case 26: 490 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1); 491 break; 492 case 27: 493 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2); 494 break; 495 case 28: 496 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3); 497 break; 498 default: 499 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0); 500 break; 501 } 502 503 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT, 504 SPI_NFI_SPARE_SIZE, val); 505 if (err) 506 return err; 507 508 switch (as_ctrl->nfi_cfg.page_size) { 509 case 2048: 510 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1); 511 break; 512 case 4096: 513 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2); 514 break; 515 default: 516 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0); 517 break; 518 } 519 520 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT, 521 SPI_NFI_PAGE_SIZE, val); 522 if (err) 523 return err; 524 525 /* sec num */ 526 val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num); 527 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 528 SPI_NFI_SEC_NUM, val); 529 if (err) 530 return err; 531 532 /* enable cust sec size */ 533 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, 534 SPI_NFI_CUS_SEC_SIZE_EN); 535 if (err) 536 return err; 537 538 /* set cust sec size */ 539 val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size); 540 return regmap_update_bits(as_ctrl->regmap_nfi, 541 REG_SPI_NFI_SECCUS_SIZE, 542 SPI_NFI_CUS_SEC_SIZE, val); 543} 544 545static bool airoha_snand_is_page_ops(const struct spi_mem_op *op) 546{ 547 if (op->addr.nbytes != 2) 548 return false; 549 550 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && 551 op->addr.buswidth != 4) 552 return false; 553 554 switch (op->data.dir) { 555 case SPI_MEM_DATA_IN: 556 if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf) 557 return false; 558 559 /* quad in / quad out */ 560 if (op->addr.buswidth == 4) 561 return op->data.buswidth == 4; 562 563 if (op->addr.buswidth == 2) 564 return op->data.buswidth == 2; 565 566 /* standard spi */ 567 return op->data.buswidth == 4 || op->data.buswidth == 2 || 568 op->data.buswidth == 1; 569 case SPI_MEM_DATA_OUT: 570 return !op->dummy.nbytes && op->addr.buswidth == 1 && 571 (op->data.buswidth == 4 || op->data.buswidth == 1); 572 default: 573 return false; 574 } 575} 576 577static int airoha_snand_adjust_op_size(struct spi_mem *mem, 578 struct spi_mem_op *op) 579{ 580 size_t max_len; 581 582 if (airoha_snand_is_page_ops(op)) { 583 struct airoha_snand_ctrl *as_ctrl; 584 585 as_ctrl = spi_controller_get_devdata(mem->spi->controller); 586 max_len = as_ctrl->nfi_cfg.sec_size; 587 max_len += as_ctrl->nfi_cfg.spare_size; 588 max_len *= as_ctrl->nfi_cfg.sec_num; 589 590 if (op->data.nbytes > max_len) 591 op->data.nbytes = max_len; 592 } else { 593 max_len = 1 + op->addr.nbytes + op->dummy.nbytes; 594 if (max_len >= 160) 595 return -EOPNOTSUPP; 596 597 if (op->data.nbytes > 160 - max_len) 598 op->data.nbytes = 160 - max_len; 599 } 600 601 return 0; 602} 603 604static bool airoha_snand_supports_op(struct spi_mem *mem, 605 const struct spi_mem_op *op) 606{ 607 if (!spi_mem_default_supports_op(mem, op)) 608 return false; 609 610 if (op->cmd.buswidth != 1) 611 return false; 612 613 if (airoha_snand_is_page_ops(op)) 614 return true; 615 616 return (!op->addr.nbytes || op->addr.buswidth == 1) && 617 (!op->dummy.nbytes || op->dummy.buswidth == 1) && 618 (!op->data.nbytes || op->data.buswidth == 1); 619} 620 621static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc) 622{ 623 struct airoha_snand_dev *as_dev = spi_get_ctldata(desc->mem->spi); 624 625 if (!as_dev->txrx_buf) 626 return -EINVAL; 627 628 if (desc->info.offset + desc->info.length > U32_MAX) 629 return -EINVAL; 630 631 if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl)) 632 return -EOPNOTSUPP; 633 634 return 0; 635} 636 637static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc, 638 u64 offs, size_t len, void *buf) 639{ 640 struct spi_device *spi = desc->mem->spi; 641 struct airoha_snand_dev *as_dev = spi_get_ctldata(spi); 642 struct spi_mem_op *op = &desc->info.op_tmpl; 643 struct airoha_snand_ctrl *as_ctrl; 644 u32 val, rd_mode; 645 int err; 646 647 if (!as_dev->data_need_update) 648 return len; 649 650 as_dev->data_need_update = false; 651 652 switch (op->cmd.opcode) { 653 case SPI_NAND_OP_READ_FROM_CACHE_DUAL: 654 rd_mode = 1; 655 break; 656 case SPI_NAND_OP_READ_FROM_CACHE_QUAD: 657 rd_mode = 2; 658 break; 659 default: 660 rd_mode = 0; 661 break; 662 } 663 664 as_ctrl = spi_controller_get_devdata(spi->controller); 665 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA); 666 if (err < 0) 667 return err; 668 669 err = airoha_snand_nfi_config(as_ctrl); 670 if (err) 671 return err; 672 673 dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr, 674 as_dev->buf_len, DMA_BIDIRECTIONAL); 675 676 /* set dma addr */ 677 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR, 678 as_dev->dma_addr); 679 if (err) 680 return err; 681 682 /* set cust sec size */ 683 val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num; 684 val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val); 685 err = regmap_update_bits(as_ctrl->regmap_nfi, 686 REG_SPI_NFI_SNF_MISC_CTL2, 687 SPI_NFI_READ_DATA_BYTE_NUM, val); 688 if (err) 689 return err; 690 691 /* set read command */ 692 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2, 693 op->cmd.opcode); 694 if (err) 695 return err; 696 697 /* set read mode */ 698 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL, 699 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode)); 700 if (err) 701 return err; 702 703 /* set read addr */ 704 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0); 705 if (err) 706 return err; 707 708 /* set nfi read */ 709 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 710 SPI_NFI_OPMODE, 711 FIELD_PREP(SPI_NFI_OPMODE, 6)); 712 if (err) 713 return err; 714 715 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 716 SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE); 717 if (err) 718 return err; 719 720 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0); 721 if (err) 722 return err; 723 724 /* trigger dma start read */ 725 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 726 SPI_NFI_RD_TRIG); 727 if (err) 728 return err; 729 730 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 731 SPI_NFI_RD_TRIG); 732 if (err) 733 return err; 734 735 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, 736 REG_SPI_NFI_SNF_STA_CTL1, val, 737 (val & SPI_NFI_READ_FROM_CACHE_DONE), 738 0, 1 * USEC_PER_SEC); 739 if (err) 740 return err; 741 742 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1, 743 SPI_NFI_READ_FROM_CACHE_DONE); 744 if (err) 745 return err; 746 747 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR, 748 val, (val & SPI_NFI_AHB_DONE), 0, 749 1 * USEC_PER_SEC); 750 if (err) 751 return err; 752 753 /* DMA read need delay for data ready from controller to DRAM */ 754 udelay(1); 755 756 dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr, 757 as_dev->buf_len, DMA_BIDIRECTIONAL); 758 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 759 if (err < 0) 760 return err; 761 762 memcpy(buf, as_dev->txrx_buf + offs, len); 763 764 return len; 765} 766 767static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc, 768 u64 offs, size_t len, const void *buf) 769{ 770 struct spi_device *spi = desc->mem->spi; 771 struct airoha_snand_dev *as_dev = spi_get_ctldata(spi); 772 struct spi_mem_op *op = &desc->info.op_tmpl; 773 struct airoha_snand_ctrl *as_ctrl; 774 u32 wr_mode, val; 775 int err; 776 777 as_ctrl = spi_controller_get_devdata(spi->controller); 778 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 779 if (err < 0) 780 return err; 781 782 dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr, 783 as_dev->buf_len, DMA_BIDIRECTIONAL); 784 memcpy(as_dev->txrx_buf + offs, buf, len); 785 dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr, 786 as_dev->buf_len, DMA_BIDIRECTIONAL); 787 788 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA); 789 if (err < 0) 790 return err; 791 792 err = airoha_snand_nfi_config(as_ctrl); 793 if (err) 794 return err; 795 796 if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD || 797 op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD) 798 wr_mode = BIT(1); 799 else 800 wr_mode = 0; 801 802 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR, 803 as_dev->dma_addr); 804 if (err) 805 return err; 806 807 val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, 808 as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num); 809 err = regmap_update_bits(as_ctrl->regmap_nfi, 810 REG_SPI_NFI_SNF_MISC_CTL2, 811 SPI_NFI_PROG_LOAD_BYTE_NUM, val); 812 if (err) 813 return err; 814 815 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1, 816 FIELD_PREP(SPI_NFI_PG_LOAD_CMD, 817 op->cmd.opcode)); 818 if (err) 819 return err; 820 821 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL, 822 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode)); 823 if (err) 824 return err; 825 826 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0); 827 if (err) 828 return err; 829 830 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 831 SPI_NFI_READ_MODE); 832 if (err) 833 return err; 834 835 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 836 SPI_NFI_OPMODE, 837 FIELD_PREP(SPI_NFI_OPMODE, 3)); 838 if (err) 839 return err; 840 841 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG, 842 SPI_NFI_DMA_MODE); 843 if (err) 844 return err; 845 846 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80); 847 if (err) 848 return err; 849 850 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 851 SPI_NFI_WR_TRIG); 852 if (err) 853 return err; 854 855 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, 856 SPI_NFI_WR_TRIG); 857 if (err) 858 return err; 859 860 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR, 861 val, (val & SPI_NFI_AHB_DONE), 0, 862 1 * USEC_PER_SEC); 863 if (err) 864 return err; 865 866 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, 867 REG_SPI_NFI_SNF_STA_CTL1, val, 868 (val & SPI_NFI_LOAD_TO_CACHE_DONE), 869 0, 1 * USEC_PER_SEC); 870 if (err) 871 return err; 872 873 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1, 874 SPI_NFI_LOAD_TO_CACHE_DONE); 875 if (err) 876 return err; 877 878 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 879 if (err < 0) 880 return err; 881 882 return len; 883} 884 885static int airoha_snand_exec_op(struct spi_mem *mem, 886 const struct spi_mem_op *op) 887{ 888 struct airoha_snand_dev *as_dev = spi_get_ctldata(mem->spi); 889 u8 data[8], cmd, opcode = op->cmd.opcode; 890 struct airoha_snand_ctrl *as_ctrl; 891 int i, err; 892 893 as_ctrl = spi_controller_get_devdata(mem->spi->controller); 894 if (opcode == SPI_NAND_OP_PROGRAM_EXECUTE && 895 op->addr.val == as_dev->cur_page_num) { 896 as_dev->data_need_update = true; 897 } else if (opcode == SPI_NAND_OP_PAGE_READ) { 898 if (!as_dev->data_need_update && 899 op->addr.val == as_dev->cur_page_num) 900 return 0; 901 902 as_dev->data_need_update = true; 903 as_dev->cur_page_num = op->addr.val; 904 } 905 906 /* switch to manual mode */ 907 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 908 if (err < 0) 909 return err; 910 911 err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW); 912 if (err < 0) 913 return err; 914 915 /* opcode */ 916 err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode)); 917 if (err) 918 return err; 919 920 /* addr part */ 921 cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8; 922 put_unaligned_be64(op->addr.val, data); 923 924 for (i = ARRAY_SIZE(data) - op->addr.nbytes; 925 i < ARRAY_SIZE(data); i++) { 926 err = airoha_snand_write_data(as_ctrl, cmd, &data[i], 927 sizeof(data[0])); 928 if (err) 929 return err; 930 } 931 932 /* dummy */ 933 data[0] = 0xff; 934 for (i = 0; i < op->dummy.nbytes; i++) { 935 err = airoha_snand_write_data(as_ctrl, 0x8, &data[0], 936 sizeof(data[0])); 937 if (err) 938 return err; 939 } 940 941 /* data */ 942 if (op->data.dir == SPI_MEM_DATA_IN) { 943 err = airoha_snand_read_data(as_ctrl, op->data.buf.in, 944 op->data.nbytes); 945 if (err) 946 return err; 947 } else { 948 err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out, 949 op->data.nbytes); 950 if (err) 951 return err; 952 } 953 954 return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH); 955} 956 957static const struct spi_controller_mem_ops airoha_snand_mem_ops = { 958 .adjust_op_size = airoha_snand_adjust_op_size, 959 .supports_op = airoha_snand_supports_op, 960 .exec_op = airoha_snand_exec_op, 961 .dirmap_create = airoha_snand_dirmap_create, 962 .dirmap_read = airoha_snand_dirmap_read, 963 .dirmap_write = airoha_snand_dirmap_write, 964}; 965 966static int airoha_snand_setup(struct spi_device *spi) 967{ 968 struct airoha_snand_ctrl *as_ctrl; 969 struct airoha_snand_dev *as_dev; 970 971 as_ctrl = spi_controller_get_devdata(spi->controller); 972 973 as_dev = devm_kzalloc(as_ctrl->dev, sizeof(*as_dev), GFP_KERNEL); 974 if (!as_dev) 975 return -ENOMEM; 976 977 /* prepare device buffer */ 978 as_dev->buf_len = SPI_NAND_CACHE_SIZE; 979 as_dev->txrx_buf = devm_kzalloc(as_ctrl->dev, as_dev->buf_len, 980 GFP_KERNEL); 981 if (!as_dev->txrx_buf) 982 return -ENOMEM; 983 984 as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf, 985 as_dev->buf_len, DMA_BIDIRECTIONAL); 986 if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr)) 987 return -ENOMEM; 988 989 as_dev->data_need_update = true; 990 spi_set_ctldata(spi, as_dev); 991 992 return 0; 993} 994 995static void airoha_snand_cleanup(struct spi_device *spi) 996{ 997 struct airoha_snand_dev *as_dev = spi_get_ctldata(spi); 998 struct airoha_snand_ctrl *as_ctrl; 999 1000 as_ctrl = spi_controller_get_devdata(spi->controller); 1001 dma_unmap_single(as_ctrl->dev, as_dev->dma_addr, 1002 as_dev->buf_len, DMA_BIDIRECTIONAL); 1003 spi_set_ctldata(spi, NULL); 1004} 1005 1006static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl) 1007{ 1008 u32 val, sec_size, sec_num; 1009 int err; 1010 1011 err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val); 1012 if (err) 1013 return err; 1014 1015 sec_num = FIELD_GET(SPI_NFI_SEC_NUM, val); 1016 1017 err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, &val); 1018 if (err) 1019 return err; 1020 1021 sec_size = FIELD_GET(SPI_NFI_CUS_SEC_SIZE, val); 1022 1023 /* init default value */ 1024 as_ctrl->nfi_cfg.sec_size = sec_size; 1025 as_ctrl->nfi_cfg.sec_num = sec_num; 1026 as_ctrl->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024); 1027 as_ctrl->nfi_cfg.spare_size = 16; 1028 1029 err = airoha_snand_nfi_init(as_ctrl); 1030 if (err) 1031 return err; 1032 1033 return airoha_snand_nfi_config(as_ctrl); 1034} 1035 1036static const struct regmap_config spi_ctrl_regmap_config = { 1037 .name = "ctrl", 1038 .reg_bits = 32, 1039 .val_bits = 32, 1040 .reg_stride = 4, 1041 .max_register = REG_SPI_CTRL_NFI2SPI_EN, 1042}; 1043 1044static const struct regmap_config spi_nfi_regmap_config = { 1045 .name = "nfi", 1046 .reg_bits = 32, 1047 .val_bits = 32, 1048 .reg_stride = 4, 1049 .max_register = REG_SPI_NFI_SNF_NFI_CNFG, 1050}; 1051 1052static const struct of_device_id airoha_snand_ids[] = { 1053 { .compatible = "airoha,en7581-snand" }, 1054 { /* sentinel */ } 1055}; 1056MODULE_DEVICE_TABLE(of, airoha_snand_ids); 1057 1058static int airoha_snand_probe(struct platform_device *pdev) 1059{ 1060 struct airoha_snand_ctrl *as_ctrl; 1061 struct device *dev = &pdev->dev; 1062 struct spi_controller *ctrl; 1063 void __iomem *base; 1064 int err; 1065 1066 ctrl = devm_spi_alloc_host(dev, sizeof(*as_ctrl)); 1067 if (!ctrl) 1068 return -ENOMEM; 1069 1070 as_ctrl = spi_controller_get_devdata(ctrl); 1071 as_ctrl->dev = dev; 1072 1073 base = devm_platform_ioremap_resource(pdev, 0); 1074 if (IS_ERR(base)) 1075 return PTR_ERR(base); 1076 1077 as_ctrl->regmap_ctrl = devm_regmap_init_mmio(dev, base, 1078 &spi_ctrl_regmap_config); 1079 if (IS_ERR(as_ctrl->regmap_ctrl)) 1080 return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_ctrl), 1081 "failed to init spi ctrl regmap\n"); 1082 1083 base = devm_platform_ioremap_resource(pdev, 1); 1084 if (IS_ERR(base)) 1085 return PTR_ERR(base); 1086 1087 as_ctrl->regmap_nfi = devm_regmap_init_mmio(dev, base, 1088 &spi_nfi_regmap_config); 1089 if (IS_ERR(as_ctrl->regmap_nfi)) 1090 return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_nfi), 1091 "failed to init spi nfi regmap\n"); 1092 1093 as_ctrl->spi_clk = devm_clk_get_enabled(dev, "spi"); 1094 if (IS_ERR(as_ctrl->spi_clk)) 1095 return dev_err_probe(dev, PTR_ERR(as_ctrl->spi_clk), 1096 "unable to get spi clk\n"); 1097 1098 err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32)); 1099 if (err) 1100 return err; 1101 1102 ctrl->num_chipselect = 2; 1103 ctrl->mem_ops = &airoha_snand_mem_ops; 1104 ctrl->bits_per_word_mask = SPI_BPW_MASK(8); 1105 ctrl->mode_bits = SPI_RX_DUAL; 1106 ctrl->setup = airoha_snand_setup; 1107 ctrl->cleanup = airoha_snand_cleanup; 1108 device_set_node(&ctrl->dev, dev_fwnode(dev)); 1109 1110 err = airoha_snand_nfi_setup(as_ctrl); 1111 if (err) 1112 return err; 1113 1114 return devm_spi_register_controller(dev, ctrl); 1115} 1116 1117static struct platform_driver airoha_snand_driver = { 1118 .driver = { 1119 .name = "airoha-spi", 1120 .of_match_table = airoha_snand_ids, 1121 }, 1122 .probe = airoha_snand_probe, 1123}; 1124module_platform_driver(airoha_snand_driver); 1125 1126MODULE_DESCRIPTION("Airoha SPI-NAND Flash Controller Driver"); 1127MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 1128MODULE_AUTHOR("Ray Liu <ray.liu@airoha.com>"); 1129MODULE_LICENSE("GPL"); 1130