1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright 2014 Cisco Systems, Inc.  All rights reserved. */
3
4#ifndef __SNIC_STATS_H
5#define __SNIC_STATS_H
6
7struct snic_io_stats {
8	atomic64_t active;		/* Active IOs */
9	atomic64_t max_active;		/* Max # active IOs */
10	atomic64_t max_sgl;		/* Max # SGLs for any IO */
11	atomic64_t max_time;		/* Max time to process IO */
12	atomic64_t max_qtime;		/* Max time to Queue the IO */
13	atomic64_t max_cmpl_time;	/* Max time to complete the IO */
14	atomic64_t sgl_cnt[SNIC_MAX_SG_DESC_CNT]; /* SGL Counters */
15	atomic64_t max_io_sz;		/* Max IO Size */
16	atomic64_t compl;		/* IO Completions */
17	atomic64_t fail;		/* IO Failures */
18	atomic64_t req_null;		/* req or req info is NULL */
19	atomic64_t alloc_fail;		/* Alloc Failures */
20	atomic64_t sc_null;
21	atomic64_t io_not_found;	/* IO Not Found */
22	atomic64_t num_ios;		/* Number of IOs */
23};
24
25struct snic_abort_stats {
26	atomic64_t num;		/* Abort counter */
27	atomic64_t fail;	/* Abort Failure Counter */
28	atomic64_t drv_tmo;	/* Abort Driver Timeouts */
29	atomic64_t fw_tmo;	/* Abort Firmware Timeouts */
30	atomic64_t io_not_found;/* Abort IO Not Found */
31	atomic64_t q_fail;	/* Abort Queuing Failed */
32};
33
34struct snic_reset_stats {
35	atomic64_t dev_resets;		/* Device Reset Counter */
36	atomic64_t dev_reset_fail;	/* Device Reset Failures */
37	atomic64_t dev_reset_aborts;	/* Device Reset Aborts */
38	atomic64_t dev_reset_tmo;	/* Device Reset Timeout */
39	atomic64_t dev_reset_terms;	/* Device Reset terminate */
40	atomic64_t hba_resets;		/* hba/firmware resets */
41	atomic64_t hba_reset_cmpl;	/* hba/firmware reset completions */
42	atomic64_t hba_reset_fail;	/* hba/firmware failures */
43	atomic64_t snic_resets;		/* snic resets */
44	atomic64_t snic_reset_compl;	/* snic reset completions */
45	atomic64_t snic_reset_fail;	/* snic reset failures */
46};
47
48struct snic_fw_stats {
49	atomic64_t actv_reqs;		/* Active Requests */
50	atomic64_t max_actv_reqs;	/* Max Active Requests */
51	atomic64_t out_of_res;		/* Firmware Out Of Resources */
52	atomic64_t io_errs;		/* Firmware IO Firmware Errors */
53	atomic64_t scsi_errs;		/* Target hits check condition */
54};
55
56struct snic_misc_stats {
57	u64	last_isr_time;
58	u64	last_ack_time;
59	atomic64_t ack_isr_cnt;
60	atomic64_t cmpl_isr_cnt;
61	atomic64_t errnotify_isr_cnt;
62	atomic64_t max_cq_ents;		/* Max CQ Entries */
63	atomic64_t data_cnt_mismat;	/* Data Count Mismatch */
64	atomic64_t io_tmo;
65	atomic64_t io_aborted;
66	atomic64_t sgl_inval;		/* SGL Invalid */
67	atomic64_t abts_wq_alloc_fail;	/* Abort Path WQ desc alloc failure */
68	atomic64_t devrst_wq_alloc_fail;/* Device Reset - WQ desc alloc fail */
69	atomic64_t wq_alloc_fail;	/* IO WQ desc alloc failure */
70	atomic64_t no_icmnd_itmf_cmpls;
71	atomic64_t io_under_run;
72	atomic64_t qfull;
73	atomic64_t qsz_rampup;
74	atomic64_t qsz_rampdown;
75	atomic64_t last_qsz;
76	atomic64_t tgt_not_rdy;
77};
78
79struct snic_stats {
80	struct snic_io_stats io;
81	struct snic_abort_stats abts;
82	struct snic_reset_stats reset;
83	struct snic_fw_stats fw;
84	struct snic_misc_stats misc;
85	atomic64_t io_cmpl_skip;
86};
87
88void snic_stats_debugfs_init(struct snic *);
89void snic_stats_debugfs_remove(struct snic *);
90
91/* Auxillary function to update active IO counter */
92static inline void
93snic_stats_update_active_ios(struct snic_stats *s_stats)
94{
95	struct snic_io_stats *io = &s_stats->io;
96	int nr_active_ios;
97
98	nr_active_ios = atomic64_read(&io->active);
99	if (atomic64_read(&io->max_active) < nr_active_ios)
100		atomic64_set(&io->max_active, nr_active_ios);
101
102	atomic64_inc(&io->num_ios);
103}
104
105/* Auxillary function to update IO completion counter */
106static inline void
107snic_stats_update_io_cmpl(struct snic_stats *s_stats)
108{
109	atomic64_dec(&s_stats->io.active);
110	if (unlikely(atomic64_read(&s_stats->io_cmpl_skip)))
111		atomic64_dec(&s_stats->io_cmpl_skip);
112	else
113		atomic64_inc(&s_stats->io.compl);
114}
115#endif /* __SNIC_STATS_H */
116