1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DesignWare PWM Controller driver
4 *
5 * Copyright (C) 2018-2020 Intel Corporation
6 *
7 * Author: Felipe Balbi (Intel)
8 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
9 * Author: Raymond Tan <raymond.tan@intel.com>
10 */
11
12MODULE_IMPORT_NS(dwc_pwm);
13
14#define DWC_TIM_LD_CNT(n)	((n) * 0x14)
15#define DWC_TIM_LD_CNT2(n)	(((n) * 4) + 0xb0)
16#define DWC_TIM_CUR_VAL(n)	(((n) * 0x14) + 0x04)
17#define DWC_TIM_CTRL(n)		(((n) * 0x14) + 0x08)
18#define DWC_TIM_EOI(n)		(((n) * 0x14) + 0x0c)
19#define DWC_TIM_INT_STS(n)	(((n) * 0x14) + 0x10)
20
21#define DWC_TIMERS_INT_STS	0xa0
22#define DWC_TIMERS_EOI		0xa4
23#define DWC_TIMERS_RAW_INT_STS	0xa8
24#define DWC_TIMERS_COMP_VERSION	0xac
25
26#define DWC_TIMERS_TOTAL	8
27
28/* Timer Control Register */
29#define DWC_TIM_CTRL_EN		BIT(0)
30#define DWC_TIM_CTRL_MODE	BIT(1)
31#define DWC_TIM_CTRL_MODE_FREE	(0 << 1)
32#define DWC_TIM_CTRL_MODE_USER	(1 << 1)
33#define DWC_TIM_CTRL_INT_MASK	BIT(2)
34#define DWC_TIM_CTRL_PWM	BIT(3)
35
36struct dwc_pwm_info {
37	unsigned int nr;
38	unsigned int size;
39};
40
41struct dwc_pwm_drvdata {
42	const struct dwc_pwm_info *info;
43	void __iomem *io_base;
44	struct pwm_chip *chips[];
45};
46
47struct dwc_pwm_ctx {
48	u32 cnt;
49	u32 cnt2;
50	u32 ctrl;
51};
52
53struct dwc_pwm {
54	void __iomem *base;
55	unsigned int clk_ns;
56	struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
57};
58
59static inline struct dwc_pwm *to_dwc_pwm(struct pwm_chip *chip)
60{
61	return pwmchip_get_drvdata(chip);
62}
63
64static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset)
65{
66	return readl(dwc->base + offset);
67}
68
69static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset)
70{
71	writel(value, dwc->base + offset);
72}
73
74extern struct pwm_chip *dwc_pwm_alloc(struct device *dev);
75