1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Intel Core SoC Power Management Controller Header File
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 * All Rights Reserved.
7 *
8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
9 *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
10 */
11
12#ifndef PMC_CORE_H
13#define PMC_CORE_H
14
15#include <linux/acpi.h>
16#include <linux/bits.h>
17#include <linux/platform_device.h>
18
19struct telem_endpoint;
20
21#define SLP_S0_RES_COUNTER_MASK			GENMASK(31, 0)
22
23#define PMC_BASE_ADDR_DEFAULT			0xFE000000
24#define MAX_NUM_PMC			3
25
26/* Sunrise Point Power Management Controller PCI Device ID */
27#define SPT_PMC_PCI_DEVICE_ID			0x9d21
28#define SPT_PMC_BASE_ADDR_OFFSET		0x48
29#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET	0x13c
30#define SPT_PMC_PM_CFG_OFFSET			0x18
31#define SPT_PMC_PM_STS_OFFSET			0x1c
32#define SPT_PMC_MTPMC_OFFSET			0x20
33#define SPT_PMC_MFPMC_OFFSET			0x38
34#define SPT_PMC_LTR_IGNORE_OFFSET		0x30C
35#define SPT_PMC_VRIC1_OFFSET			0x31c
36#define SPT_PMC_MPHY_CORE_STS_0			0x1143
37#define SPT_PMC_MPHY_CORE_STS_1			0x1142
38#define SPT_PMC_MPHY_COM_STS_0			0x1155
39#define SPT_PMC_MMIO_REG_LEN			0x1000
40#define SPT_PMC_SLP_S0_RES_COUNTER_STEP		0x68
41#define PMC_BASE_ADDR_MASK			~(SPT_PMC_MMIO_REG_LEN - 1)
42#define MTPMC_MASK				0xffff0000
43#define PPFEAR_MAX_NUM_ENTRIES			12
44#define SPT_PPFEAR_NUM_ENTRIES			5
45#define SPT_PMC_READ_DISABLE_BIT		0x16
46#define SPT_PMC_MSG_FULL_STS_BIT		0x18
47#define NUM_RETRIES				100
48#define SPT_NUM_IP_IGN_ALLOWED			17
49
50#define SPT_PMC_LTR_CUR_PLT			0x350
51#define SPT_PMC_LTR_CUR_ASLT			0x354
52#define SPT_PMC_LTR_SPA				0x360
53#define SPT_PMC_LTR_SPB				0x364
54#define SPT_PMC_LTR_SATA			0x368
55#define SPT_PMC_LTR_GBE				0x36C
56#define SPT_PMC_LTR_XHCI			0x370
57#define SPT_PMC_LTR_RESERVED			0x374
58#define SPT_PMC_LTR_ME				0x378
59#define SPT_PMC_LTR_EVA				0x37C
60#define SPT_PMC_LTR_SPC				0x380
61#define SPT_PMC_LTR_AZ				0x384
62#define SPT_PMC_LTR_LPSS			0x38C
63#define SPT_PMC_LTR_CAM				0x390
64#define SPT_PMC_LTR_SPD				0x394
65#define SPT_PMC_LTR_SPE				0x398
66#define SPT_PMC_LTR_ESPI			0x39C
67#define SPT_PMC_LTR_SCC				0x3A0
68#define SPT_PMC_LTR_ISH				0x3A4
69
70/* Sunrise Point: PGD PFET Enable Ack Status Registers */
71enum ppfear_regs {
72	SPT_PMC_XRAM_PPFEAR0A = 0x590,
73	SPT_PMC_XRAM_PPFEAR0B,
74	SPT_PMC_XRAM_PPFEAR0C,
75	SPT_PMC_XRAM_PPFEAR0D,
76	SPT_PMC_XRAM_PPFEAR1A,
77};
78
79#define SPT_PMC_BIT_PMC				BIT(0)
80#define SPT_PMC_BIT_OPI				BIT(1)
81#define SPT_PMC_BIT_SPI				BIT(2)
82#define SPT_PMC_BIT_XHCI			BIT(3)
83#define SPT_PMC_BIT_SPA				BIT(4)
84#define SPT_PMC_BIT_SPB				BIT(5)
85#define SPT_PMC_BIT_SPC				BIT(6)
86#define SPT_PMC_BIT_GBE				BIT(7)
87
88#define SPT_PMC_BIT_SATA			BIT(0)
89#define SPT_PMC_BIT_HDA_PGD0			BIT(1)
90#define SPT_PMC_BIT_HDA_PGD1			BIT(2)
91#define SPT_PMC_BIT_HDA_PGD2			BIT(3)
92#define SPT_PMC_BIT_HDA_PGD3			BIT(4)
93#define SPT_PMC_BIT_RSVD_0B			BIT(5)
94#define SPT_PMC_BIT_LPSS			BIT(6)
95#define SPT_PMC_BIT_LPC				BIT(7)
96
97#define SPT_PMC_BIT_SMB				BIT(0)
98#define SPT_PMC_BIT_ISH				BIT(1)
99#define SPT_PMC_BIT_P2SB			BIT(2)
100#define SPT_PMC_BIT_DFX				BIT(3)
101#define SPT_PMC_BIT_SCC				BIT(4)
102#define SPT_PMC_BIT_RSVD_0C			BIT(5)
103#define SPT_PMC_BIT_FUSE			BIT(6)
104#define SPT_PMC_BIT_CAMREA			BIT(7)
105
106#define SPT_PMC_BIT_RSVD_0D			BIT(0)
107#define SPT_PMC_BIT_USB3_OTG			BIT(1)
108#define SPT_PMC_BIT_EXI				BIT(2)
109#define SPT_PMC_BIT_CSE				BIT(3)
110#define SPT_PMC_BIT_CSME_KVM			BIT(4)
111#define SPT_PMC_BIT_CSME_PMT			BIT(5)
112#define SPT_PMC_BIT_CSME_CLINK			BIT(6)
113#define SPT_PMC_BIT_CSME_PTIO			BIT(7)
114
115#define SPT_PMC_BIT_CSME_USBR			BIT(0)
116#define SPT_PMC_BIT_CSME_SUSRAM			BIT(1)
117#define SPT_PMC_BIT_CSME_SMT			BIT(2)
118#define SPT_PMC_BIT_RSVD_1A			BIT(3)
119#define SPT_PMC_BIT_CSME_SMS2			BIT(4)
120#define SPT_PMC_BIT_CSME_SMS1			BIT(5)
121#define SPT_PMC_BIT_CSME_RTC			BIT(6)
122#define SPT_PMC_BIT_CSME_PSF			BIT(7)
123
124#define SPT_PMC_BIT_MPHY_LANE0			BIT(0)
125#define SPT_PMC_BIT_MPHY_LANE1			BIT(1)
126#define SPT_PMC_BIT_MPHY_LANE2			BIT(2)
127#define SPT_PMC_BIT_MPHY_LANE3			BIT(3)
128#define SPT_PMC_BIT_MPHY_LANE4			BIT(4)
129#define SPT_PMC_BIT_MPHY_LANE5			BIT(5)
130#define SPT_PMC_BIT_MPHY_LANE6			BIT(6)
131#define SPT_PMC_BIT_MPHY_LANE7			BIT(7)
132
133#define SPT_PMC_BIT_MPHY_LANE8			BIT(0)
134#define SPT_PMC_BIT_MPHY_LANE9			BIT(1)
135#define SPT_PMC_BIT_MPHY_LANE10			BIT(2)
136#define SPT_PMC_BIT_MPHY_LANE11			BIT(3)
137#define SPT_PMC_BIT_MPHY_LANE12			BIT(4)
138#define SPT_PMC_BIT_MPHY_LANE13			BIT(5)
139#define SPT_PMC_BIT_MPHY_LANE14			BIT(6)
140#define SPT_PMC_BIT_MPHY_LANE15			BIT(7)
141
142#define SPT_PMC_BIT_MPHY_CMN_LANE0		BIT(0)
143#define SPT_PMC_BIT_MPHY_CMN_LANE1		BIT(1)
144#define SPT_PMC_BIT_MPHY_CMN_LANE2		BIT(2)
145#define SPT_PMC_BIT_MPHY_CMN_LANE3		BIT(3)
146
147#define SPT_PMC_VRIC1_SLPS0LVEN			BIT(13)
148#define SPT_PMC_VRIC1_XTALSDQDIS		BIT(22)
149
150/* Cannonlake Power Management Controller register offsets */
151#define CNP_PMC_SLPS0_DBG_OFFSET		0x10B4
152#define CNP_PMC_PM_CFG_OFFSET			0x1818
153#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET	0x193C
154#define CNP_PMC_LTR_IGNORE_OFFSET		0x1B0C
155/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
156#define CNP_PMC_HOST_PPFEAR0A			0x1D90
157
158#define CNP_PMC_LATCH_SLPS0_EVENTS		BIT(31)
159
160#define CNP_PMC_MMIO_REG_LEN			0x2000
161#define CNP_PPFEAR_NUM_ENTRIES			8
162#define CNP_PMC_READ_DISABLE_BIT		22
163#define CNP_NUM_IP_IGN_ALLOWED			19
164#define CNP_PMC_LTR_CUR_PLT			0x1B50
165#define CNP_PMC_LTR_CUR_ASLT			0x1B54
166#define CNP_PMC_LTR_SPA				0x1B60
167#define CNP_PMC_LTR_SPB				0x1B64
168#define CNP_PMC_LTR_SATA			0x1B68
169#define CNP_PMC_LTR_GBE				0x1B6C
170#define CNP_PMC_LTR_XHCI			0x1B70
171#define CNP_PMC_LTR_RESERVED			0x1B74
172#define CNP_PMC_LTR_ME				0x1B78
173#define CNP_PMC_LTR_EVA				0x1B7C
174#define CNP_PMC_LTR_SPC				0x1B80
175#define CNP_PMC_LTR_AZ				0x1B84
176#define CNP_PMC_LTR_LPSS			0x1B8C
177#define CNP_PMC_LTR_CAM				0x1B90
178#define CNP_PMC_LTR_SPD				0x1B94
179#define CNP_PMC_LTR_SPE				0x1B98
180#define CNP_PMC_LTR_ESPI			0x1B9C
181#define CNP_PMC_LTR_SCC				0x1BA0
182#define CNP_PMC_LTR_ISH				0x1BA4
183#define CNP_PMC_LTR_CNV				0x1BF0
184#define CNP_PMC_LTR_EMMC			0x1BF4
185#define CNP_PMC_LTR_UFSX2			0x1BF8
186
187#define LTR_DECODED_VAL				GENMASK(9, 0)
188#define LTR_DECODED_SCALE			GENMASK(12, 10)
189#define LTR_REQ_SNOOP				BIT(15)
190#define LTR_REQ_NONSNOOP			BIT(31)
191
192#define ICL_PPFEAR_NUM_ENTRIES			9
193#define ICL_NUM_IP_IGN_ALLOWED			20
194#define ICL_PMC_LTR_WIGIG			0x1BFC
195#define ICL_PMC_SLP_S0_RES_COUNTER_STEP		0x64
196
197#define LPM_MAX_NUM_MODES			8
198#define LPM_DEFAULT_PRI				{ 7, 6, 2, 5, 4, 1, 3, 0 }
199
200#define GET_X2_COUNTER(v)			((v) >> 1)
201#define LPM_STS_LATCH_MODE			BIT(31)
202
203#define TGL_PMC_SLP_S0_RES_COUNTER_STEP		0x7A
204#define TGL_PMC_LTR_THC0			0x1C04
205#define TGL_PMC_LTR_THC1			0x1C08
206#define TGL_NUM_IP_IGN_ALLOWED			23
207#define TGL_PMC_LPM_RES_COUNTER_STEP_X2		61	/* 30.5us * 2 */
208
209#define ADL_PMC_LTR_SPF				0x1C00
210#define ADL_NUM_IP_IGN_ALLOWED			23
211#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET	0x1098
212
213/*
214 * Tigerlake Power Management Controller register offsets
215 */
216#define TGL_LPM_STS_LATCH_EN_OFFSET		0x1C34
217#define TGL_LPM_EN_OFFSET			0x1C78
218#define TGL_LPM_RESIDENCY_OFFSET		0x1C80
219
220/* Tigerlake Low Power Mode debug registers */
221#define TGL_LPM_STATUS_OFFSET			0x1C3C
222#define TGL_LPM_LIVE_STATUS_OFFSET		0x1C5C
223#define TGL_LPM_PRI_OFFSET			0x1C7C
224#define TGL_LPM_NUM_MAPS			6
225
226/* Tigerlake PSON residency register */
227#define TGL_PSON_RESIDENCY_OFFSET		0x18f8
228#define TGL_PSON_RES_COUNTER_STEP		0x7A
229
230/* Extended Test Mode Register 3 (CNL and later) */
231#define ETR3_OFFSET				0x1048
232#define ETR3_CF9GR				BIT(20)
233#define ETR3_CF9LOCK				BIT(31)
234
235/* Extended Test Mode Register LPM bits (TGL and later */
236#define ETR3_CLEAR_LPM_EVENTS			BIT(28)
237
238/* Alder Lake Power Management Controller register offsets */
239#define ADL_LPM_EN_OFFSET			0x179C
240#define ADL_LPM_RESIDENCY_OFFSET		0x17A4
241#define ADL_LPM_NUM_MODES			2
242#define ADL_LPM_NUM_MAPS			14
243
244/* Alder Lake Low Power Mode debug registers */
245#define ADL_LPM_STATUS_OFFSET			0x170C
246#define ADL_LPM_PRI_OFFSET			0x17A0
247#define ADL_LPM_STATUS_LATCH_EN_OFFSET		0x1704
248#define ADL_LPM_LIVE_STATUS_OFFSET		0x1764
249
250/* Meteor Lake Power Management Controller register offsets */
251#define MTL_LPM_EN_OFFSET			0x1798
252#define MTL_LPM_RESIDENCY_OFFSET		0x17A0
253
254/* Meteor Lake Low Power Mode debug registers */
255#define MTL_LPM_PRI_OFFSET			0x179C
256#define MTL_LPM_STATUS_LATCH_EN_OFFSET		0x16F8
257#define MTL_LPM_STATUS_OFFSET			0x1700
258#define MTL_LPM_LIVE_STATUS_OFFSET		0x175C
259#define MTL_PMC_LTR_IOE_PMC			0x1C0C
260#define MTL_PMC_LTR_ESE				0x1BAC
261#define MTL_PMC_LTR_RESERVED			0x1BA4
262#define MTL_IOE_PMC_MMIO_REG_LEN		0x23A4
263#define MTL_SOCM_NUM_IP_IGN_ALLOWED		25
264#define MTL_SOC_PMC_MMIO_REG_LEN		0x2708
265#define MTL_PMC_LTR_SPG				0x1B74
266#define ARL_SOCS_PMC_LTR_RESERVED		0x1B88
267#define ARL_SOCS_NUM_IP_IGN_ALLOWED		26
268#define ARL_PMC_LTR_DMI3			0x1BE4
269#define ARL_PCH_PMC_MMIO_REG_LEN		0x2720
270
271/* Meteor Lake PGD PFET Enable Ack Status */
272#define MTL_SOCM_PPFEAR_NUM_ENTRIES		8
273#define MTL_IOE_PPFEAR_NUM_ENTRIES		10
274#define ARL_SOCS_PPFEAR_NUM_ENTRIES		9
275
276/* Die C6 from PUNIT telemetry */
277#define MTL_PMT_DMU_DIE_C6_OFFSET		15
278#define MTL_PMT_DMU_GUID			0x1A067102
279#define ARL_PMT_DMU_GUID			0x1A06A000
280
281#define LNL_PMC_MMIO_REG_LEN			0x2708
282#define LNL_PMC_LTR_OSSE			0x1B88
283#define LNL_NUM_IP_IGN_ALLOWED			27
284#define LNL_PPFEAR_NUM_ENTRIES			12
285
286extern const char *pmc_lpm_modes[];
287
288struct pmc_bit_map {
289	const char *name;
290	u32 bit_mask;
291};
292
293/**
294 * struct pmc_reg_map - Structure used to define parameter unique to a
295			PCH family
296 * @pfear_sts:		Maps name of IP block to PPFEAR* bit
297 * @mphy_sts:		Maps name of MPHY lane to MPHY status lane status bit
298 * @pll_sts:		Maps name of PLL to corresponding bit status
299 * @slps0_dbg_maps:	Array of SLP_S0_DBG* registers containing debug info
300 * @ltr_show_sts:	Maps PCH IP Names to their MMIO register offsets
301 * @slp_s0_offset:	PWRMBASE offset to read SLP_S0 residency
302 * @ltr_ignore_offset:	PWRMBASE offset to read/write LTR ignore bit
303 * @regmap_length:	Length of memory to map from PWRMBASE address to access
304 * @ppfear0_offset:	PWRMBASE offset to read PPFEAR*
305 * @ppfear_buckets:	Number of 8 bits blocks to read all IP blocks from
306 *			PPFEAR
307 * @pm_cfg_offset:	PWRMBASE offset to PM_CFG register
308 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
309 * @slps0_dbg_offset:	PWRMBASE offset to SLP_S0_DEBUG_REG*
310 *
311 * Each PCH has unique set of register offsets and bit indexes. This structure
312 * captures them to have a common implementation.
313 */
314struct pmc_reg_map {
315	const struct pmc_bit_map **pfear_sts;
316	const struct pmc_bit_map *mphy_sts;
317	const struct pmc_bit_map *pll_sts;
318	const struct pmc_bit_map **slps0_dbg_maps;
319	const struct pmc_bit_map *ltr_show_sts;
320	const struct pmc_bit_map *msr_sts;
321	const struct pmc_bit_map **lpm_sts;
322	const u32 slp_s0_offset;
323	const int slp_s0_res_counter_step;
324	const u32 ltr_ignore_offset;
325	const int regmap_length;
326	const u32 ppfear0_offset;
327	const int ppfear_buckets;
328	const u32 pm_cfg_offset;
329	const int pm_read_disable_bit;
330	const u32 slps0_dbg_offset;
331	const u32 ltr_ignore_max;
332	const u32 pm_vric1_offset;
333	/* Low Power Mode registers */
334	const int lpm_num_maps;
335	const int lpm_num_modes;
336	const int lpm_res_counter_step_x2;
337	const u32 lpm_sts_latch_en_offset;
338	const u32 lpm_en_offset;
339	const u32 lpm_priority_offset;
340	const u32 lpm_residency_offset;
341	const u32 lpm_status_offset;
342	const u32 lpm_live_status_offset;
343	const u32 etr3_offset;
344	const u8  *lpm_reg_index;
345	const u32 pson_residency_offset;
346	const u32 pson_residency_counter_step;
347};
348
349/**
350 * struct pmc_info - Structure to keep pmc info
351 * @devid:		device id of the pmc device
352 * @map:		pointer to a pmc_reg_map struct that contains platform
353 *			specific attributes
354 */
355struct pmc_info {
356	u32 guid;
357	u16 devid;
358	const struct pmc_reg_map *map;
359};
360
361/**
362 * struct pmc - pmc private info structure
363 * @base_addr:		contains pmc base address
364 * @regbase:		pointer to io-remapped memory location
365 * @map:		pointer to pmc_reg_map struct that contains platform
366 *			specific attributes
367 * @lpm_req_regs:	List of substate requirements
368 *
369 * pmc contains info about one power management controller device.
370 */
371struct pmc {
372	u64 base_addr;
373	void __iomem *regbase;
374	const struct pmc_reg_map *map;
375	u32 *lpm_req_regs;
376};
377
378/**
379 * struct pmc_dev - pmc device structure
380 * @devs:		pointer to an array of pmc pointers
381 * @pdev:		pointer to platform_device struct
382 * @ssram_pcidev:	pointer to pci device struct for the PMC SSRAM
383 * @crystal_freq:	crystal frequency from cpuid
384 * @dbgfs_dir:		path to debugfs interface
385 * @pmc_xram_read_bit:	flag to indicate whether PMC XRAM shadow registers
386 *			used to read MPHY PG and PLL status are available
387 * @mutex_lock:		mutex to complete one transcation
388 * @pkgc_res_cnt:	Array of PKGC residency counters
389 * @num_of_pkgc:	Number of PKGC
390 * @s0ix_counter:	S0ix residency (step adjusted)
391 * @num_lpm_modes:	Count of enabled modes
392 * @lpm_en_modes:	Array of enabled modes from lowest to highest priority
393 * @suspend:		Function to perform platform specific suspend
394 * @resume:		Function to perform platform specific resume
395 *
396 * pmc_dev contains info about power management controller device.
397 */
398struct pmc_dev {
399	struct pmc *pmcs[MAX_NUM_PMC];
400	struct dentry *dbgfs_dir;
401	struct platform_device *pdev;
402	struct pci_dev *ssram_pcidev;
403	unsigned int crystal_freq;
404	int pmc_xram_read_bit;
405	struct mutex lock; /* generic mutex lock for PMC Core */
406
407	u64 s0ix_counter;
408	int num_lpm_modes;
409	int lpm_en_modes[LPM_MAX_NUM_MODES];
410	void (*suspend)(struct pmc_dev *pmcdev);
411	int (*resume)(struct pmc_dev *pmcdev);
412
413	u64 *pkgc_res_cnt;
414	u8 num_of_pkgc;
415
416	bool has_die_c6;
417	u32 die_c6_offset;
418	struct telem_endpoint *punit_ep;
419	struct pmc_info *regmap_list;
420};
421
422enum pmc_index {
423	PMC_IDX_MAIN,
424	PMC_IDX_SOC = PMC_IDX_MAIN,
425	PMC_IDX_IOE,
426	PMC_IDX_PCH,
427	PMC_IDX_MAX
428};
429
430extern const struct pmc_bit_map msr_map[];
431extern const struct pmc_bit_map spt_pll_map[];
432extern const struct pmc_bit_map spt_mphy_map[];
433extern const struct pmc_bit_map spt_pfear_map[];
434extern const struct pmc_bit_map *ext_spt_pfear_map[];
435extern const struct pmc_bit_map spt_ltr_show_map[];
436extern const struct pmc_reg_map spt_reg_map;
437extern const struct pmc_bit_map cnp_pfear_map[];
438extern const struct pmc_bit_map *ext_cnp_pfear_map[];
439extern const struct pmc_bit_map cnp_slps0_dbg0_map[];
440extern const struct pmc_bit_map cnp_slps0_dbg1_map[];
441extern const struct pmc_bit_map cnp_slps0_dbg2_map[];
442extern const struct pmc_bit_map *cnp_slps0_dbg_maps[];
443extern const struct pmc_bit_map cnp_ltr_show_map[];
444extern const struct pmc_reg_map cnp_reg_map;
445extern const struct pmc_bit_map icl_pfear_map[];
446extern const struct pmc_bit_map *ext_icl_pfear_map[];
447extern const struct pmc_reg_map icl_reg_map;
448extern const struct pmc_bit_map tgl_pfear_map[];
449extern const struct pmc_bit_map *ext_tgl_pfear_map[];
450extern const struct pmc_bit_map tgl_clocksource_status_map[];
451extern const struct pmc_bit_map tgl_power_gating_status_map[];
452extern const struct pmc_bit_map tgl_d3_status_map[];
453extern const struct pmc_bit_map tgl_vnn_req_status_map[];
454extern const struct pmc_bit_map tgl_vnn_misc_status_map[];
455extern const struct pmc_bit_map tgl_signal_status_map[];
456extern const struct pmc_bit_map *tgl_lpm_maps[];
457extern const struct pmc_reg_map tgl_reg_map;
458extern const struct pmc_reg_map tgl_h_reg_map;
459extern const struct pmc_bit_map adl_pfear_map[];
460extern const struct pmc_bit_map *ext_adl_pfear_map[];
461extern const struct pmc_bit_map adl_ltr_show_map[];
462extern const struct pmc_bit_map adl_clocksource_status_map[];
463extern const struct pmc_bit_map adl_power_gating_status_0_map[];
464extern const struct pmc_bit_map adl_power_gating_status_1_map[];
465extern const struct pmc_bit_map adl_power_gating_status_2_map[];
466extern const struct pmc_bit_map adl_d3_status_0_map[];
467extern const struct pmc_bit_map adl_d3_status_1_map[];
468extern const struct pmc_bit_map adl_d3_status_2_map[];
469extern const struct pmc_bit_map adl_d3_status_3_map[];
470extern const struct pmc_bit_map adl_vnn_req_status_0_map[];
471extern const struct pmc_bit_map adl_vnn_req_status_1_map[];
472extern const struct pmc_bit_map adl_vnn_req_status_2_map[];
473extern const struct pmc_bit_map adl_vnn_req_status_3_map[];
474extern const struct pmc_bit_map adl_vnn_misc_status_map[];
475extern const struct pmc_bit_map *adl_lpm_maps[];
476extern const struct pmc_reg_map adl_reg_map;
477extern const struct pmc_bit_map mtl_socm_pfear_map[];
478extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[];
479extern const struct pmc_bit_map mtl_socm_ltr_show_map[];
480extern const struct pmc_bit_map mtl_socm_clocksource_status_map[];
481extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[];
482extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[];
483extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[];
484extern const struct pmc_bit_map mtl_socm_d3_status_0_map[];
485extern const struct pmc_bit_map mtl_socm_d3_status_1_map[];
486extern const struct pmc_bit_map mtl_socm_d3_status_2_map[];
487extern const struct pmc_bit_map mtl_socm_d3_status_3_map[];
488extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[];
489extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[];
490extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[];
491extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[];
492extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[];
493extern const struct pmc_bit_map mtl_socm_signal_status_map[];
494extern const struct pmc_bit_map *mtl_socm_lpm_maps[];
495extern const struct pmc_reg_map mtl_socm_reg_map;
496extern const struct pmc_bit_map mtl_ioep_pfear_map[];
497extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[];
498extern const struct pmc_bit_map mtl_ioep_ltr_show_map[];
499extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[];
500extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[];
501extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[];
502extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[];
503extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[];
504extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[];
505extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[];
506extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[];
507extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[];
508extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[];
509extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[];
510extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[];
511extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[];
512extern const struct pmc_bit_map *mtl_ioep_lpm_maps[];
513extern const struct pmc_reg_map mtl_ioep_reg_map;
514extern const struct pmc_bit_map mtl_ioem_pfear_map[];
515extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[];
516extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[];
517extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[];
518extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
519extern const struct pmc_reg_map mtl_ioem_reg_map;
520extern const struct pmc_reg_map lnl_socm_reg_map;
521
522/* LNL */
523extern const struct pmc_bit_map lnl_ltr_show_map[];
524extern const struct pmc_bit_map lnl_clocksource_status_map[];
525extern const struct pmc_bit_map lnl_power_gating_status_0_map[];
526extern const struct pmc_bit_map lnl_power_gating_status_1_map[];
527extern const struct pmc_bit_map lnl_power_gating_status_2_map[];
528extern const struct pmc_bit_map lnl_d3_status_0_map[];
529extern const struct pmc_bit_map lnl_d3_status_1_map[];
530extern const struct pmc_bit_map lnl_d3_status_2_map[];
531extern const struct pmc_bit_map lnl_d3_status_3_map[];
532extern const struct pmc_bit_map lnl_vnn_req_status_0_map[];
533extern const struct pmc_bit_map lnl_vnn_req_status_1_map[];
534extern const struct pmc_bit_map lnl_vnn_req_status_2_map[];
535extern const struct pmc_bit_map lnl_vnn_req_status_3_map[];
536extern const struct pmc_bit_map lnl_vnn_misc_status_map[];
537extern const struct pmc_bit_map *lnl_lpm_maps[];
538extern const struct pmc_bit_map lnl_pfear_map[];
539extern const struct pmc_bit_map *ext_lnl_pfear_map[];
540
541/* ARL */
542extern const struct pmc_bit_map arl_socs_ltr_show_map[];
543extern const struct pmc_bit_map arl_socs_clocksource_status_map[];
544extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[];
545extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[];
546extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[];
547extern const struct pmc_bit_map arl_socs_d3_status_2_map[];
548extern const struct pmc_bit_map arl_socs_d3_status_3_map[];
549extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[];
550extern const struct pmc_bit_map *arl_socs_lpm_maps[];
551extern const struct pmc_bit_map arl_socs_pfear_map[];
552extern const struct pmc_bit_map *ext_arl_socs_pfear_map[];
553extern const struct pmc_reg_map arl_socs_reg_map;
554extern const struct pmc_bit_map arl_pchs_ltr_show_map[];
555extern const struct pmc_bit_map arl_pchs_clocksource_status_map[];
556extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[];
557extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[];
558extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[];
559extern const struct pmc_bit_map arl_pchs_d3_status_0_map[];
560extern const struct pmc_bit_map arl_pchs_d3_status_1_map[];
561extern const struct pmc_bit_map arl_pchs_d3_status_2_map[];
562extern const struct pmc_bit_map arl_pchs_d3_status_3_map[];
563extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[];
564extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[];
565extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[];
566extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[];
567extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[];
568extern const struct pmc_bit_map arl_pchs_signal_status_map[];
569extern const struct pmc_bit_map *arl_pchs_lpm_maps[];
570extern const struct pmc_reg_map arl_pchs_reg_map;
571
572extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
573extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);
574int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
575
576int pmc_core_resume_common(struct pmc_dev *pmcdev);
577int get_primary_reg_base(struct pmc *pmc);
578extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev);
579extern void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid);
580extern void pmc_core_set_device_d3(unsigned int device);
581
582extern int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func);
583
584int spt_core_init(struct pmc_dev *pmcdev);
585int cnp_core_init(struct pmc_dev *pmcdev);
586int icl_core_init(struct pmc_dev *pmcdev);
587int tgl_core_init(struct pmc_dev *pmcdev);
588int tgl_l_core_init(struct pmc_dev *pmcdev);
589int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp);
590int adl_core_init(struct pmc_dev *pmcdev);
591int mtl_core_init(struct pmc_dev *pmcdev);
592int arl_core_init(struct pmc_dev *pmcdev);
593int lnl_core_init(struct pmc_dev *pmcdev);
594
595void cnl_suspend(struct pmc_dev *pmcdev);
596int cnl_resume(struct pmc_dev *pmcdev);
597
598#define pmc_for_each_mode(i, mode, pmcdev)		\
599	for (i = 0, mode = pmcdev->lpm_en_modes[i];	\
600	     i < pmcdev->num_lpm_modes;			\
601	     i++, mode = pmcdev->lpm_en_modes[i])
602
603#define DEFINE_PMC_CORE_ATTR_WRITE(__name)				\
604static int __name ## _open(struct inode *inode, struct file *file)	\
605{									\
606	return single_open(file, __name ## _show, inode->i_private);	\
607}									\
608									\
609static const struct file_operations __name ## _fops = {			\
610	.owner		= THIS_MODULE,					\
611	.open		= __name ## _open,				\
612	.read		= seq_read,					\
613	.write		= __name ## _write,				\
614	.release	= single_release,				\
615}
616
617#endif /* PMC_CORE_H */
618