1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11#ifndef PMF_H 12#define PMF_H 13 14#include <linux/acpi.h> 15#include <linux/platform_profile.h> 16 17#define POLICY_BUF_MAX_SZ 0x4b000 18#define POLICY_SIGN_COOKIE 0x31535024 19#define POLICY_COOKIE_OFFSET 0x10 20 21struct cookie_header { 22 u32 sign; 23 u32 length; 24} __packed; 25 26/* APMF Functions */ 27#define APMF_FUNC_VERIFY_INTERFACE 0 28#define APMF_FUNC_GET_SYS_PARAMS 1 29#define APMF_FUNC_SBIOS_REQUESTS 2 30#define APMF_FUNC_SBIOS_HEARTBEAT 4 31#define APMF_FUNC_AUTO_MODE 5 32#define APMF_FUNC_SET_FAN_IDX 7 33#define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 34#define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 35#define APMF_FUNC_DYN_SLIDER_AC 11 36#define APMF_FUNC_DYN_SLIDER_DC 12 37#define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 38 39/* Message Definitions */ 40#define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 41#define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 42#define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 43#define GET_SPL 0x0B 44#define GET_SPPT 0x0D 45#define GET_FPPT 0x0F 46#define SET_DRAM_ADDR_HIGH 0x14 47#define SET_DRAM_ADDR_LOW 0x15 48#define SET_TRANSFER_TABLE 0x16 49#define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 50#define SET_STT_LIMIT_APU 0x19 51#define SET_STT_LIMIT_HS2 0x1A 52#define SET_SPPT_APU_ONLY 0x1D 53#define GET_SPPT_APU_ONLY 0x1E 54#define GET_STT_MIN_LIMIT 0x1F 55#define GET_STT_LIMIT_APU 0x20 56#define GET_STT_LIMIT_HS2 0x21 57#define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 58#define SET_PMF_PPT 0x25 59#define SET_PMF_PPT_APU_ONLY 0x26 60 61/* OS slider update notification */ 62#define DC_BEST_PERF 0 63#define DC_BETTER_PERF 1 64#define DC_BATTERY_SAVER 3 65#define AC_BEST_PERF 4 66#define AC_BETTER_PERF 5 67#define AC_BETTER_BATTERY 6 68 69/* Fan Index for Auto Mode */ 70#define FAN_INDEX_AUTO 0xFFFFFFFF 71 72#define ARG_NONE 0 73#define AVG_SAMPLE_SIZE 3 74 75/* Policy Actions */ 76#define PMF_POLICY_SPL 2 77#define PMF_POLICY_SPPT 3 78#define PMF_POLICY_FPPT 4 79#define PMF_POLICY_SPPT_APU_ONLY 5 80#define PMF_POLICY_STT_MIN 6 81#define PMF_POLICY_STT_SKINTEMP_APU 7 82#define PMF_POLICY_STT_SKINTEMP_HS2 8 83#define PMF_POLICY_SYSTEM_STATE 9 84#define PMF_POLICY_P3T 38 85 86/* TA macros */ 87#define PMF_TA_IF_VERSION_MAJOR 1 88#define TA_PMF_ACTION_MAX 32 89#define TA_PMF_UNDO_MAX 8 90#define TA_OUTPUT_RESERVED_MEM 906 91#define MAX_OPERATION_PARAMS 4 92 93#define PMF_IF_V1 1 94#define PMF_IF_V2 2 95 96#define APTS_MAX_STATES 16 97 98/* APTS PMF BIOS Interface */ 99struct amd_pmf_apts_output { 100 u16 table_version; 101 u32 fan_table_idx; 102 u32 pmf_ppt; 103 u32 ppt_pmf_apu_only; 104 u32 stt_min_limit; 105 u8 stt_skin_temp_limit_apu; 106 u8 stt_skin_temp_limit_hs2; 107} __packed; 108 109struct amd_pmf_apts_granular_output { 110 u16 size; 111 struct amd_pmf_apts_output val; 112} __packed; 113 114struct amd_pmf_apts_granular { 115 u16 size; 116 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 117}; 118 119struct sbios_hb_event_v2 { 120 u16 size; 121 u8 load; 122 u8 unload; 123 u8 suspend; 124 u8 resume; 125} __packed; 126 127enum sbios_hb_v2 { 128 ON_LOAD, 129 ON_UNLOAD, 130 ON_SUSPEND, 131 ON_RESUME, 132}; 133 134/* AMD PMF BIOS interfaces */ 135struct apmf_verify_interface { 136 u16 size; 137 u16 version; 138 u32 notification_mask; 139 u32 supported_functions; 140} __packed; 141 142struct apmf_system_params { 143 u16 size; 144 u32 valid_mask; 145 u32 flags; 146 u8 command_code; 147 u32 heartbeat_int; 148} __packed; 149 150struct apmf_sbios_req { 151 u16 size; 152 u32 pending_req; 153 u8 rsd; 154 u8 cql_event; 155 u8 amt_event; 156 u32 fppt; 157 u32 sppt; 158 u32 fppt_apu_only; 159 u32 spl; 160 u32 stt_min_limit; 161 u8 skin_temp_apu; 162 u8 skin_temp_hs2; 163} __packed; 164 165struct apmf_sbios_req_v2 { 166 u16 size; 167 u32 pending_req; 168 u8 rsd; 169 u32 ppt_pmf; 170 u32 ppt_pmf_apu_only; 171 u32 stt_min_limit; 172 u8 skin_temp_apu; 173 u8 skin_temp_hs2; 174 u32 custom_policy[10]; 175} __packed; 176 177struct apmf_fan_idx { 178 u16 size; 179 u8 fan_ctl_mode; 180 u32 fan_ctl_idx; 181} __packed; 182 183struct smu_pmf_metrics { 184 u16 gfxclk_freq; /* in MHz */ 185 u16 socclk_freq; /* in MHz */ 186 u16 vclk_freq; /* in MHz */ 187 u16 dclk_freq; /* in MHz */ 188 u16 memclk_freq; /* in MHz */ 189 u16 spare; 190 u16 gfx_activity; /* in Centi */ 191 u16 uvd_activity; /* in Centi */ 192 u16 voltage[2]; /* in mV */ 193 u16 currents[2]; /* in mA */ 194 u16 power[2];/* in mW */ 195 u16 core_freq[8]; /* in MHz */ 196 u16 core_power[8]; /* in mW */ 197 u16 core_temp[8]; /* in centi-Celsius */ 198 u16 l3_freq; /* in MHz */ 199 u16 l3_temp; /* in centi-Celsius */ 200 u16 gfx_temp; /* in centi-Celsius */ 201 u16 soc_temp; /* in centi-Celsius */ 202 u16 throttler_status; 203 u16 current_socketpower; /* in mW */ 204 u16 stapm_orig_limit; /* in W */ 205 u16 stapm_cur_limit; /* in W */ 206 u32 apu_power; /* in mW */ 207 u32 dgpu_power; /* in mW */ 208 u16 vdd_tdc_val; /* in mA */ 209 u16 soc_tdc_val; /* in mA */ 210 u16 vdd_edc_val; /* in mA */ 211 u16 soc_edcv_al; /* in mA */ 212 u16 infra_cpu_maxfreq; /* in MHz */ 213 u16 infra_gfx_maxfreq; /* in MHz */ 214 u16 skin_temp; /* in centi-Celsius */ 215 u16 device_state; 216 u16 curtemp; /* in centi-Celsius */ 217 u16 filter_alpha_value; 218 u16 avg_gfx_clkfrequency; 219 u16 avg_fclk_frequency; 220 u16 avg_gfx_activity; 221 u16 avg_socclk_frequency; 222 u16 avg_vclk_frequency; 223 u16 avg_vcn_activity; 224 u16 avg_dram_reads; 225 u16 avg_dram_writes; 226 u16 avg_socket_power; 227 u16 avg_core_power[2]; 228 u16 avg_core_c0residency[16]; 229 u16 spare1; 230 u32 metrics_counter; 231} __packed; 232 233enum amd_stt_skin_temp { 234 STT_TEMP_APU, 235 STT_TEMP_HS2, 236 STT_TEMP_COUNT, 237}; 238 239enum amd_slider_op { 240 SLIDER_OP_GET, 241 SLIDER_OP_SET, 242}; 243 244enum power_source { 245 POWER_SOURCE_AC, 246 POWER_SOURCE_DC, 247 POWER_SOURCE_MAX, 248}; 249 250enum power_modes { 251 POWER_MODE_PERFORMANCE, 252 POWER_MODE_BALANCED_POWER, 253 POWER_MODE_POWER_SAVER, 254 POWER_MODE_MAX, 255}; 256 257enum power_modes_v2 { 258 POWER_MODE_BEST_PERFORMANCE, 259 POWER_MODE_BALANCED, 260 POWER_MODE_BEST_POWER_EFFICIENCY, 261 POWER_MODE_ENERGY_SAVE, 262 POWER_MODE_V2_MAX, 263}; 264 265struct amd_pmf_dev { 266 void __iomem *regbase; 267 void __iomem *smu_virt_addr; 268 void *buf; 269 u32 base_addr; 270 u32 cpu_id; 271 struct device *dev; 272 struct mutex lock; /* protects the PMF interface */ 273 u32 supported_func; 274 enum platform_profile_option current_profile; 275 struct platform_profile_handler pprof; 276 struct dentry *dbgfs_dir; 277 int hb_interval; /* SBIOS heartbeat interval */ 278 struct delayed_work heart_beat; 279 struct smu_pmf_metrics m_table; 280 struct delayed_work work_buffer; 281 ktime_t start_time; 282 int socket_power_history[AVG_SAMPLE_SIZE]; 283 int socket_power_history_idx; 284 bool amt_enabled; 285 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 286 bool cnqf_enabled; 287 bool cnqf_supported; 288 struct notifier_block pwr_src_notifier; 289 /* Smart PC solution builder */ 290 struct dentry *esbin; 291 unsigned char *policy_buf; 292 u32 policy_sz; 293 struct tee_context *tee_ctx; 294 struct tee_shm *fw_shm_pool; 295 u32 session_id; 296 void *shbuf; 297 struct delayed_work pb_work; 298 struct pmf_action_table *prev_data; 299 u64 policy_addr; 300 void __iomem *policy_base; 301 bool smart_pc_enabled; 302 u16 pmf_if_version; 303}; 304 305struct apmf_sps_prop_granular_v2 { 306 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 307} __packed; 308 309struct apmf_sps_prop_granular { 310 u32 fppt; 311 u32 sppt; 312 u32 sppt_apu_only; 313 u32 spl; 314 u32 stt_min; 315 u8 stt_skin_temp[STT_TEMP_COUNT]; 316 u32 fan_id; 317} __packed; 318 319/* Static Slider */ 320struct apmf_static_slider_granular_output { 321 u16 size; 322 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 323} __packed; 324 325struct amd_pmf_static_slider_granular { 326 u16 size; 327 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 328}; 329 330struct apmf_static_slider_granular_output_v2 { 331 u16 size; 332 struct apmf_sps_prop_granular_v2 sps_idx; 333} __packed; 334 335struct amd_pmf_static_slider_granular_v2 { 336 u16 size; 337 struct apmf_sps_prop_granular_v2 sps_idx; 338}; 339 340struct os_power_slider { 341 u16 size; 342 u8 slider_event; 343} __packed; 344 345struct fan_table_control { 346 bool manual; 347 unsigned long fan_id; 348}; 349 350struct power_table_control { 351 u32 spl; 352 u32 sppt; 353 u32 fppt; 354 u32 sppt_apu_only; 355 u32 stt_min; 356 u32 stt_skin_temp[STT_TEMP_COUNT]; 357 u32 reserved[16]; 358}; 359 360/* Auto Mode Layer */ 361enum auto_mode_transition_priority { 362 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 363 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 364 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 365 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 366 AUTO_TRANSITION_MAX, 367}; 368 369enum auto_mode_mode { 370 AUTO_QUIET, 371 AUTO_BALANCE, 372 AUTO_PERFORMANCE_ON_LAP, 373 AUTO_PERFORMANCE, 374 AUTO_MODE_MAX, 375}; 376 377struct auto_mode_trans_params { 378 u32 time_constant; /* minimum time required to switch to next mode */ 379 u32 power_delta; /* delta power to shift mode */ 380 u32 power_threshold; 381 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 382 u32 applied; 383 enum auto_mode_mode target_mode; 384 u32 shifting_up; 385}; 386 387struct auto_mode_mode_settings { 388 struct power_table_control power_control; 389 struct fan_table_control fan_control; 390 u32 power_floor; 391}; 392 393struct auto_mode_mode_config { 394 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 395 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 396 enum auto_mode_mode current_mode; 397}; 398 399struct apmf_auto_mode { 400 u16 size; 401 /* time constant */ 402 u32 balanced_to_perf; 403 u32 perf_to_balanced; 404 u32 quiet_to_balanced; 405 u32 balanced_to_quiet; 406 /* power floor */ 407 u32 pfloor_perf; 408 u32 pfloor_balanced; 409 u32 pfloor_quiet; 410 /* Power delta for mode change */ 411 u32 pd_balanced_to_perf; 412 u32 pd_perf_to_balanced; 413 u32 pd_quiet_to_balanced; 414 u32 pd_balanced_to_quiet; 415 /* skin temperature limits */ 416 u8 stt_apu_perf_on_lap; /* CQL ON */ 417 u8 stt_hs2_perf_on_lap; /* CQL ON */ 418 u8 stt_apu_perf; 419 u8 stt_hs2_perf; 420 u8 stt_apu_balanced; 421 u8 stt_hs2_balanced; 422 u8 stt_apu_quiet; 423 u8 stt_hs2_quiet; 424 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 425 u32 stt_min_limit_perf; 426 u32 stt_min_limit_balanced; 427 u32 stt_min_limit_quiet; 428 /* SPL based */ 429 u32 fppt_perf_on_lap; /* CQL ON */ 430 u32 sppt_perf_on_lap; /* CQL ON */ 431 u32 spl_perf_on_lap; /* CQL ON */ 432 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 433 u32 fppt_perf; 434 u32 sppt_perf; 435 u32 spl_perf; 436 u32 sppt_apu_only_perf; 437 u32 fppt_balanced; 438 u32 sppt_balanced; 439 u32 spl_balanced; 440 u32 sppt_apu_only_balanced; 441 u32 fppt_quiet; 442 u32 sppt_quiet; 443 u32 spl_quiet; 444 u32 sppt_apu_only_quiet; 445 /* Fan ID */ 446 u32 fan_id_perf; 447 u32 fan_id_balanced; 448 u32 fan_id_quiet; 449} __packed; 450 451/* CnQF Layer */ 452enum cnqf_trans_priority { 453 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 454 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 455 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 456 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 457 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 458 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 459 CNQF_TRANSITION_MAX, 460}; 461 462enum cnqf_mode { 463 CNQF_MODE_QUIET, 464 CNQF_MODE_BALANCE, 465 CNQF_MODE_PERFORMANCE, 466 CNQF_MODE_TURBO, 467 CNQF_MODE_MAX, 468}; 469 470enum apmf_cnqf_pos { 471 APMF_CNQF_TURBO, 472 APMF_CNQF_PERFORMANCE, 473 APMF_CNQF_BALANCE, 474 APMF_CNQF_QUIET, 475 APMF_CNQF_MAX, 476}; 477 478struct cnqf_mode_settings { 479 struct power_table_control power_control; 480 struct fan_table_control fan_control; 481 u32 power_floor; 482}; 483 484struct cnqf_tran_params { 485 u32 time_constant; /* minimum time required to switch to next mode */ 486 u32 power_threshold; 487 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 488 u32 total_power; 489 u32 count; 490 bool priority; 491 bool shifting_up; 492 enum cnqf_mode target_mode; 493}; 494 495struct cnqf_config { 496 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 497 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 498 struct power_table_control defaults; 499 enum cnqf_mode current_mode; 500 u32 power_src; 501 u32 avg_power; 502}; 503 504struct apmf_cnqf_power_set { 505 u32 pfloor; 506 u32 fppt; 507 u32 sppt; 508 u32 sppt_apu_only; 509 u32 spl; 510 u32 stt_min_limit; 511 u8 stt_skintemp[STT_TEMP_COUNT]; 512 u32 fan_id; 513} __packed; 514 515struct apmf_dyn_slider_output { 516 u16 size; 517 u16 flags; 518 u32 t_perf_to_turbo; 519 u32 t_balanced_to_perf; 520 u32 t_quiet_to_balanced; 521 u32 t_balanced_to_quiet; 522 u32 t_perf_to_balanced; 523 u32 t_turbo_to_perf; 524 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 525} __packed; 526 527/* Smart PC - TA internals */ 528enum system_state { 529 SYSTEM_STATE_S0i3, 530 SYSTEM_STATE_S4, 531 SYSTEM_STATE_SCREEN_LOCK, 532 SYSTEM_STATE_MAX, 533}; 534 535enum ta_slider { 536 TA_BEST_BATTERY, 537 TA_BETTER_BATTERY, 538 TA_BETTER_PERFORMANCE, 539 TA_BEST_PERFORMANCE, 540 TA_MAX, 541}; 542 543/* Command ids for TA communication */ 544enum ta_pmf_command { 545 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 546 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 547}; 548 549enum ta_pmf_error_type { 550 TA_PMF_TYPE_SUCCESS, 551 TA_PMF_ERROR_TYPE_GENERIC, 552 TA_PMF_ERROR_TYPE_CRYPTO, 553 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 554 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 555 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 556 TA_PMF_ERROR_TYPE_PB_CONVERT, 557 TA_PMF_ERROR_TYPE_PB_SETUP, 558 TA_PMF_ERROR_TYPE_PB_ENACT, 559 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 560 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 561 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 562 TA_PMF_ERROR_TYPE_MAX, 563}; 564 565struct pmf_action_table { 566 enum system_state system_state; 567 u32 spl; /* in mW */ 568 u32 sppt; /* in mW */ 569 u32 sppt_apuonly; /* in mW */ 570 u32 fppt; /* in mW */ 571 u32 stt_minlimit; /* in mW */ 572 u32 stt_skintemp_apu; /* in C */ 573 u32 stt_skintemp_hs2; /* in C */ 574 u32 p3t_limit; /* in mW */ 575}; 576 577/* Input conditions */ 578struct ta_pmf_condition_info { 579 u32 power_source; 580 u32 bat_percentage; 581 u32 power_slider; 582 u32 lid_state; 583 bool user_present; 584 u32 rsvd1[2]; 585 u32 monitor_count; 586 u32 rsvd2[2]; 587 u32 bat_design; 588 u32 full_charge_capacity; 589 int drain_rate; 590 bool user_engaged; 591 u32 device_state; 592 u32 socket_power; 593 u32 skin_temperature; 594 u32 rsvd3[5]; 595 u32 ambient_light; 596 u32 length; 597 u32 avg_c0residency; 598 u32 max_c0residency; 599 u32 s0i3_entry; 600 u32 gfx_busy; 601 u32 rsvd4[7]; 602 bool camera_state; 603 u32 workload_type; 604 u32 display_type; 605 u32 display_state; 606 u32 rsvd5[150]; 607}; 608 609struct ta_pmf_load_policy_table { 610 u32 table_size; 611 u8 table[POLICY_BUF_MAX_SZ]; 612}; 613 614/* TA initialization params */ 615struct ta_pmf_init_table { 616 u32 frequency; /* SMU sampling frequency */ 617 bool validate; 618 bool sku_check; 619 bool metadata_macrocheck; 620 struct ta_pmf_load_policy_table policies_table; 621}; 622 623/* Everything the TA needs to Enact Policies */ 624struct ta_pmf_enact_table { 625 struct ta_pmf_condition_info ev_info; 626 u32 name; 627}; 628 629struct ta_pmf_action { 630 u32 action_index; 631 u32 value; 632}; 633 634/* Output actions from TA */ 635struct ta_pmf_enact_result { 636 u32 actions_count; 637 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 638 u32 undo_count; 639 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 640}; 641 642union ta_pmf_input { 643 struct ta_pmf_enact_table enact_table; 644 struct ta_pmf_init_table init_table; 645}; 646 647union ta_pmf_output { 648 struct ta_pmf_enact_result policy_apply_table; 649 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 650}; 651 652struct ta_pmf_shared_memory { 653 int command_id; 654 int resp_id; 655 u32 pmf_result; 656 u32 if_version; 657 union ta_pmf_output pmf_output; 658 union ta_pmf_input pmf_input; 659}; 660 661/* Core Layer */ 662int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 663void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 664int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 665int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 666int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 667int amd_pmf_get_power_source(void); 668int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 669int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 670int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 671int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 672 673/* SPS Layer */ 674int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 675void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 676 struct amd_pmf_static_slider_granular *table); 677int amd_pmf_init_sps(struct amd_pmf_dev *dev); 678void amd_pmf_deinit_sps(struct amd_pmf_dev *dev); 679int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 680 struct apmf_static_slider_granular_output *output); 681bool is_pprof_balanced(struct amd_pmf_dev *pmf); 682int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 683const char *amd_pmf_source_as_str(unsigned int state); 684 685const char *amd_pmf_source_as_str(unsigned int state); 686 687int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 688int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 689int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 690 struct apmf_static_slider_granular_output_v2 *data); 691int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 692 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 693 694/* Auto Mode Layer */ 695int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 696void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 697void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 698void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 699int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 700int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 701 702void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 703int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 704void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 705 706/* CnQF Layer */ 707int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 708int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 709int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 710void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 711int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 712extern const struct attribute_group cnqf_feature_attribute_group; 713 714/* Smart PC builder Layer */ 715int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 716void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 717int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 718 719/* Smart PC - TA interfaces */ 720void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 721void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 722 723/* Quirk infrastructure */ 724void amd_pmf_quirks_init(struct amd_pmf_dev *dev); 725 726#endif /* PMF_H */ 727