1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SuperH Pin Function Controller pinmux support. 4 * 5 * Copyright (C) 2012 Paul Mundt 6 */ 7 8#define DRV_NAME "sh-pfc" 9 10#include <linux/device.h> 11#include <linux/err.h> 12#include <linux/io.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/seq_file.h> 16#include <linux/slab.h> 17#include <linux/spinlock.h> 18 19#include <linux/pinctrl/consumer.h> 20#include <linux/pinctrl/machine.h> 21#include <linux/pinctrl/pinconf-generic.h> 22#include <linux/pinctrl/pinconf.h> 23#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinmux.h> 25 26#include "core.h" 27#include "../core.h" 28#include "../pinconf.h" 29 30struct sh_pfc_pin_config { 31 u16 gpio_enabled:1; 32 u16 mux_mark:15; 33}; 34 35struct sh_pfc_pinctrl { 36 struct pinctrl_dev *pctl; 37 struct pinctrl_desc pctl_desc; 38 39 struct sh_pfc *pfc; 40 41 struct pinctrl_pin_desc *pins; 42 struct sh_pfc_pin_config *configs; 43}; 44 45static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) 46{ 47 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 48 49 return pmx->pfc->info->nr_groups; 50} 51 52static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, 53 unsigned selector) 54{ 55 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 56 57 return pmx->pfc->info->groups[selector].name; 58} 59 60static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 61 const unsigned **pins, unsigned *num_pins) 62{ 63 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 64 65 *pins = pmx->pfc->info->groups[selector].pins; 66 *num_pins = pmx->pfc->info->groups[selector].nr_pins; 67 68 return 0; 69} 70 71static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 72 unsigned offset) 73{ 74 seq_puts(s, DRV_NAME); 75} 76 77#ifdef CONFIG_OF 78static int sh_pfc_map_add_config(struct pinctrl_map *map, 79 const char *group_or_pin, 80 enum pinctrl_map_type type, 81 unsigned long *configs, 82 unsigned int num_configs) 83{ 84 unsigned long *cfgs; 85 86 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 87 GFP_KERNEL); 88 if (cfgs == NULL) 89 return -ENOMEM; 90 91 map->type = type; 92 map->data.configs.group_or_pin = group_or_pin; 93 map->data.configs.configs = cfgs; 94 map->data.configs.num_configs = num_configs; 95 96 return 0; 97} 98 99static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, 100 struct device_node *np, 101 struct pinctrl_map **map, 102 unsigned int *num_maps, unsigned int *index) 103{ 104 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 105 struct device *dev = pmx->pfc->dev; 106 struct pinctrl_map *maps = *map; 107 unsigned int nmaps = *num_maps; 108 unsigned int idx = *index; 109 unsigned int num_configs; 110 const char *function = NULL; 111 unsigned long *configs; 112 struct property *prop; 113 unsigned int num_groups; 114 unsigned int num_pins; 115 const char *group; 116 const char *pin; 117 int ret; 118 119 /* Parse the function and configuration properties. At least a function 120 * or one configuration must be specified. 121 */ 122 ret = of_property_read_string(np, "function", &function); 123 if (ret < 0 && ret != -EINVAL) { 124 dev_err(dev, "Invalid function in DT\n"); 125 return ret; 126 } 127 128 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 129 if (ret < 0) 130 return ret; 131 132 if (!function && num_configs == 0) { 133 dev_err(dev, 134 "DT node must contain at least a function or config\n"); 135 ret = -ENODEV; 136 goto done; 137 } 138 139 /* Count the number of pins and groups and reallocate mappings. */ 140 ret = of_property_count_strings(np, "pins"); 141 if (ret == -EINVAL) { 142 num_pins = 0; 143 } else if (ret < 0) { 144 dev_err(dev, "Invalid pins list in DT\n"); 145 goto done; 146 } else { 147 num_pins = ret; 148 } 149 150 ret = of_property_count_strings(np, "groups"); 151 if (ret == -EINVAL) { 152 num_groups = 0; 153 } else if (ret < 0) { 154 dev_err(dev, "Invalid pin groups list in DT\n"); 155 goto done; 156 } else { 157 num_groups = ret; 158 } 159 160 if (!num_pins && !num_groups) { 161 dev_err(dev, "No pin or group provided in DT node\n"); 162 ret = -ENODEV; 163 goto done; 164 } 165 166 if (function) 167 nmaps += num_groups; 168 if (configs) 169 nmaps += num_pins + num_groups; 170 171 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); 172 if (maps == NULL) { 173 ret = -ENOMEM; 174 goto done; 175 } 176 177 *map = maps; 178 *num_maps = nmaps; 179 180 /* Iterate over pins and groups and create the mappings. */ 181 of_property_for_each_string(np, "groups", prop, group) { 182 if (function) { 183 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 184 maps[idx].data.mux.group = group; 185 maps[idx].data.mux.function = function; 186 idx++; 187 } 188 189 if (configs) { 190 ret = sh_pfc_map_add_config(&maps[idx], group, 191 PIN_MAP_TYPE_CONFIGS_GROUP, 192 configs, num_configs); 193 if (ret < 0) 194 goto done; 195 196 idx++; 197 } 198 } 199 200 if (!configs) { 201 ret = 0; 202 goto done; 203 } 204 205 of_property_for_each_string(np, "pins", prop, pin) { 206 ret = sh_pfc_map_add_config(&maps[idx], pin, 207 PIN_MAP_TYPE_CONFIGS_PIN, 208 configs, num_configs); 209 if (ret < 0) 210 goto done; 211 212 idx++; 213 } 214 215done: 216 *index = idx; 217 kfree(configs); 218 return ret; 219} 220 221static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, 222 struct pinctrl_map *map, unsigned num_maps) 223{ 224 unsigned int i; 225 226 if (map == NULL) 227 return; 228 229 for (i = 0; i < num_maps; ++i) { 230 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 231 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 232 kfree(map[i].data.configs.configs); 233 } 234 235 kfree(map); 236} 237 238static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, 239 struct device_node *np, 240 struct pinctrl_map **map, unsigned *num_maps) 241{ 242 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 243 struct device *dev = pmx->pfc->dev; 244 struct device_node *child; 245 unsigned int index; 246 int ret; 247 248 *map = NULL; 249 *num_maps = 0; 250 index = 0; 251 252 for_each_child_of_node(np, child) { 253 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, 254 &index); 255 if (ret < 0) { 256 of_node_put(child); 257 goto done; 258 } 259 } 260 261 /* If no mapping has been found in child nodes try the config node. */ 262 if (*num_maps == 0) { 263 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps, 264 &index); 265 if (ret < 0) 266 goto done; 267 } 268 269 if (*num_maps) 270 return 0; 271 272 dev_err(dev, "no mapping found in node %pOF\n", np); 273 ret = -EINVAL; 274 275done: 276 if (ret < 0) 277 sh_pfc_dt_free_map(pctldev, *map, *num_maps); 278 279 return ret; 280} 281#endif /* CONFIG_OF */ 282 283static const struct pinctrl_ops sh_pfc_pinctrl_ops = { 284 .get_groups_count = sh_pfc_get_groups_count, 285 .get_group_name = sh_pfc_get_group_name, 286 .get_group_pins = sh_pfc_get_group_pins, 287 .pin_dbg_show = sh_pfc_pin_dbg_show, 288#ifdef CONFIG_OF 289 .dt_node_to_map = sh_pfc_dt_node_to_map, 290 .dt_free_map = sh_pfc_dt_free_map, 291#endif 292}; 293 294static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) 295{ 296 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 297 298 return pmx->pfc->info->nr_functions; 299} 300 301static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, 302 unsigned selector) 303{ 304 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 305 306 return pmx->pfc->info->functions[selector].name; 307} 308 309static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, 310 unsigned selector, 311 const char * const **groups, 312 unsigned * const num_groups) 313{ 314 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 315 316 *groups = pmx->pfc->info->functions[selector].groups; 317 *num_groups = pmx->pfc->info->functions[selector].nr_groups; 318 319 return 0; 320} 321 322static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, 323 unsigned group) 324{ 325 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 326 struct sh_pfc *pfc = pmx->pfc; 327 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; 328 unsigned long flags; 329 unsigned int i; 330 int ret = 0; 331 332 dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name); 333 334 spin_lock_irqsave(&pfc->lock, flags); 335 336 for (i = 0; i < grp->nr_pins; ++i) { 337 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 338 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 339 340 /* 341 * This driver cannot manage both gpio and mux when the gpio 342 * pin is already enabled. So, this function fails. 343 */ 344 if (cfg->gpio_enabled) { 345 ret = -EBUSY; 346 goto done; 347 } 348 349 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 350 if (ret < 0) 351 goto done; 352 } 353 354 /* All group pins are configured, mark the pins as muxed */ 355 for (i = 0; i < grp->nr_pins; ++i) { 356 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 357 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 358 359 cfg->mux_mark = grp->mux[i]; 360 } 361 362done: 363 spin_unlock_irqrestore(&pfc->lock, flags); 364 return ret; 365} 366 367static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 368 struct pinctrl_gpio_range *range, 369 unsigned offset) 370{ 371 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 372 struct sh_pfc *pfc = pmx->pfc; 373 int idx = sh_pfc_get_pin_index(pfc, offset); 374 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 375 unsigned long flags; 376 int ret; 377 378 spin_lock_irqsave(&pfc->lock, flags); 379 380 if (!pfc->gpio && !cfg->mux_mark) { 381 /* If GPIOs are handled externally the pin mux type needs to be 382 * set to GPIO here. 383 */ 384 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 385 386 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 387 if (ret < 0) 388 goto done; 389 } 390 391 cfg->gpio_enabled = true; 392 393 ret = 0; 394 395done: 396 spin_unlock_irqrestore(&pfc->lock, flags); 397 398 return ret; 399} 400 401static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, 402 struct pinctrl_gpio_range *range, 403 unsigned offset) 404{ 405 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 406 struct sh_pfc *pfc = pmx->pfc; 407 int idx = sh_pfc_get_pin_index(pfc, offset); 408 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 409 unsigned long flags; 410 411 spin_lock_irqsave(&pfc->lock, flags); 412 cfg->gpio_enabled = false; 413 /* If mux is already set, this configures it here */ 414 if (cfg->mux_mark) 415 sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); 416 spin_unlock_irqrestore(&pfc->lock, flags); 417} 418 419#ifdef CONFIG_PINCTRL_SH_PFC_GPIO 420static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, 421 struct pinctrl_gpio_range *range, 422 unsigned offset, bool input) 423{ 424 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 425 struct sh_pfc *pfc = pmx->pfc; 426 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; 427 int idx = sh_pfc_get_pin_index(pfc, offset); 428 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 429 unsigned long flags; 430 unsigned int dir; 431 int ret; 432 433 /* Check if the requested direction is supported by the pin. Not all 434 * SoCs provide pin config data, so perform the check conditionally. 435 */ 436 if (pin->configs) { 437 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; 438 if (!(pin->configs & dir)) 439 return -EINVAL; 440 } 441 442 spin_lock_irqsave(&pfc->lock, flags); 443 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); 444 spin_unlock_irqrestore(&pfc->lock, flags); 445 return ret; 446} 447#else 448#define sh_pfc_gpio_set_direction NULL 449#endif 450 451static const struct pinmux_ops sh_pfc_pinmux_ops = { 452 .get_functions_count = sh_pfc_get_functions_count, 453 .get_function_name = sh_pfc_get_function_name, 454 .get_function_groups = sh_pfc_get_function_groups, 455 .set_mux = sh_pfc_func_set_mux, 456 .gpio_request_enable = sh_pfc_gpio_request_enable, 457 .gpio_disable_free = sh_pfc_gpio_disable_free, 458 .gpio_set_direction = sh_pfc_gpio_set_direction, 459}; 460 461static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, 462 unsigned int pin, unsigned int *offset, unsigned int *size) 463{ 464 const struct pinmux_drive_reg_field *field; 465 const struct pinmux_drive_reg *reg; 466 unsigned int i; 467 468 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 469 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 470 field = ®->fields[i]; 471 472 if (field->size && field->pin == pin) { 473 *offset = field->offset; 474 *size = field->size; 475 476 return reg->reg; 477 } 478 } 479 } 480 481 return 0; 482} 483 484static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, 485 unsigned int pin) 486{ 487 unsigned int offset; 488 unsigned int size; 489 u32 reg; 490 u32 val; 491 492 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 493 if (!reg) 494 return -EINVAL; 495 496 val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0); 497 498 /* Convert the value to mA based on a full drive strength value of 24mA. 499 * We can make the full value configurable later if needed. 500 */ 501 return (val + 1) * (size == 2 ? 6 : 3); 502} 503 504static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 505 unsigned int pin, u16 strength) 506{ 507 unsigned long flags; 508 unsigned int offset; 509 unsigned int size; 510 unsigned int step; 511 u32 reg; 512 u32 val; 513 514 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 515 if (!reg) 516 return -EINVAL; 517 518 step = size == 2 ? 6 : 3; 519 520 if (strength < step || strength > 24) 521 return -EINVAL; 522 523 /* Convert the value from mA based on a full drive strength value of 524 * 24mA. We can make the full value configurable later if needed. 525 */ 526 strength = strength / step - 1; 527 528 spin_lock_irqsave(&pfc->lock, flags); 529 530 val = sh_pfc_read(pfc, reg); 531 val &= ~GENMASK(offset + size - 1, offset); 532 val |= strength << offset; 533 534 sh_pfc_write(pfc, reg, val); 535 536 spin_unlock_irqrestore(&pfc->lock, flags); 537 538 return 0; 539} 540 541/* Check whether the requested parameter is supported for a pin. */ 542static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 543 enum pin_config_param param) 544{ 545 int idx = sh_pfc_get_pin_index(pfc, _pin); 546 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 547 548 switch (param) { 549 case PIN_CONFIG_BIAS_DISABLE: 550 return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN; 551 552 case PIN_CONFIG_BIAS_PULL_UP: 553 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 554 555 case PIN_CONFIG_BIAS_PULL_DOWN: 556 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 557 558 case PIN_CONFIG_DRIVE_STRENGTH: 559 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 560 561 case PIN_CONFIG_POWER_SOURCE: 562 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 563 564 default: 565 return false; 566 } 567} 568 569static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, 570 unsigned long *config) 571{ 572 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 573 struct sh_pfc *pfc = pmx->pfc; 574 enum pin_config_param param = pinconf_to_config_param(*config); 575 unsigned long flags; 576 unsigned int arg; 577 578 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 579 return -ENOTSUPP; 580 581 switch (param) { 582 case PIN_CONFIG_BIAS_DISABLE: 583 case PIN_CONFIG_BIAS_PULL_UP: 584 case PIN_CONFIG_BIAS_PULL_DOWN: { 585 unsigned int bias; 586 587 if (!pfc->info->ops || !pfc->info->ops->get_bias) 588 return -ENOTSUPP; 589 590 spin_lock_irqsave(&pfc->lock, flags); 591 bias = pfc->info->ops->get_bias(pfc, _pin); 592 spin_unlock_irqrestore(&pfc->lock, flags); 593 594 if (bias != param) 595 return -EINVAL; 596 597 arg = 0; 598 break; 599 } 600 601 case PIN_CONFIG_DRIVE_STRENGTH: { 602 int ret; 603 604 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin); 605 if (ret < 0) 606 return ret; 607 608 arg = ret; 609 break; 610 } 611 612 case PIN_CONFIG_POWER_SOURCE: { 613 int idx = sh_pfc_get_pin_index(pfc, _pin); 614 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 615 unsigned int mode, lo, hi; 616 u32 pocctrl, val; 617 int bit; 618 619 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 620 return -ENOTSUPP; 621 622 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); 623 if (WARN(bit < 0, "invalid pin %#x", _pin)) 624 return bit; 625 626 val = sh_pfc_read(pfc, pocctrl); 627 628 mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 629 lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; 630 hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; 631 632 arg = (val & BIT(bit)) ? hi : lo; 633 break; 634 } 635 636 default: 637 return -ENOTSUPP; 638 } 639 640 *config = pinconf_to_config_packed(param, arg); 641 return 0; 642} 643 644static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, 645 unsigned long *configs, unsigned num_configs) 646{ 647 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 648 struct sh_pfc *pfc = pmx->pfc; 649 enum pin_config_param param; 650 unsigned long flags; 651 unsigned int i; 652 653 for (i = 0; i < num_configs; i++) { 654 param = pinconf_to_config_param(configs[i]); 655 656 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 657 return -ENOTSUPP; 658 659 switch (param) { 660 case PIN_CONFIG_BIAS_PULL_UP: 661 case PIN_CONFIG_BIAS_PULL_DOWN: 662 case PIN_CONFIG_BIAS_DISABLE: 663 if (!pfc->info->ops || !pfc->info->ops->set_bias) 664 return -ENOTSUPP; 665 666 spin_lock_irqsave(&pfc->lock, flags); 667 pfc->info->ops->set_bias(pfc, _pin, param); 668 spin_unlock_irqrestore(&pfc->lock, flags); 669 670 break; 671 672 case PIN_CONFIG_DRIVE_STRENGTH: { 673 unsigned int arg = 674 pinconf_to_config_argument(configs[i]); 675 int ret; 676 677 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 678 if (ret < 0) 679 return ret; 680 681 break; 682 } 683 684 case PIN_CONFIG_POWER_SOURCE: { 685 unsigned int mV = pinconf_to_config_argument(configs[i]); 686 int idx = sh_pfc_get_pin_index(pfc, _pin); 687 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 688 unsigned int mode, lo, hi; 689 u32 pocctrl, val; 690 int bit; 691 692 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 693 return -ENOTSUPP; 694 695 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); 696 if (WARN(bit < 0, "invalid pin %#x", _pin)) 697 return bit; 698 699 mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 700 lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; 701 hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; 702 703 if (mV != lo && mV != hi) 704 return -EINVAL; 705 706 spin_lock_irqsave(&pfc->lock, flags); 707 val = sh_pfc_read(pfc, pocctrl); 708 if (mV == hi) 709 val |= BIT(bit); 710 else 711 val &= ~BIT(bit); 712 sh_pfc_write(pfc, pocctrl, val); 713 spin_unlock_irqrestore(&pfc->lock, flags); 714 715 break; 716 } 717 718 default: 719 return -ENOTSUPP; 720 } 721 } /* for each config */ 722 723 return 0; 724} 725 726static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 727 unsigned long *configs, 728 unsigned num_configs) 729{ 730 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 731 const unsigned int *pins; 732 unsigned int num_pins; 733 unsigned int i, ret; 734 735 pins = pmx->pfc->info->groups[group].pins; 736 num_pins = pmx->pfc->info->groups[group].nr_pins; 737 738 for (i = 0; i < num_pins; ++i) { 739 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); 740 if (ret) 741 return ret; 742 } 743 744 return 0; 745} 746 747static const struct pinconf_ops sh_pfc_pinconf_ops = { 748 .is_generic = true, 749 .pin_config_get = sh_pfc_pinconf_get, 750 .pin_config_set = sh_pfc_pinconf_set, 751 .pin_config_group_set = sh_pfc_pinconf_group_set, 752 .pin_config_config_dbg_show = pinconf_generic_dump_config, 753}; 754 755/* PFC ranges -> pinctrl pin descs */ 756static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 757{ 758 unsigned int i; 759 760 /* Allocate and initialize the pins and configs arrays. */ 761 pmx->pins = devm_kcalloc(pfc->dev, 762 pfc->info->nr_pins, sizeof(*pmx->pins), 763 GFP_KERNEL); 764 if (unlikely(!pmx->pins)) 765 return -ENOMEM; 766 767 pmx->configs = devm_kcalloc(pfc->dev, 768 pfc->info->nr_pins, sizeof(*pmx->configs), 769 GFP_KERNEL); 770 if (unlikely(!pmx->configs)) 771 return -ENOMEM; 772 773 for (i = 0; i < pfc->info->nr_pins; ++i) { 774 const struct sh_pfc_pin *info = &pfc->info->pins[i]; 775 struct pinctrl_pin_desc *pin = &pmx->pins[i]; 776 777 /* If the pin number is equal to -1 all pins are considered */ 778 pin->number = info->pin != (u16)-1 ? info->pin : i; 779 pin->name = info->name; 780 } 781 782 return 0; 783} 784 785int sh_pfc_register_pinctrl(struct sh_pfc *pfc) 786{ 787 struct sh_pfc_pinctrl *pmx; 788 int ret; 789 790 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); 791 if (unlikely(!pmx)) 792 return -ENOMEM; 793 794 pmx->pfc = pfc; 795 796 ret = sh_pfc_map_pins(pfc, pmx); 797 if (ret < 0) 798 return ret; 799 800 pmx->pctl_desc.name = DRV_NAME; 801 pmx->pctl_desc.owner = THIS_MODULE; 802 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; 803 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; 804 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; 805 pmx->pctl_desc.pins = pmx->pins; 806 pmx->pctl_desc.npins = pfc->info->nr_pins; 807 808 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx, 809 &pmx->pctl); 810 if (ret) { 811 dev_err(pfc->dev, "could not register: %i\n", ret); 812 813 return ret; 814 } 815 816 return pinctrl_enable(pmx->pctl); 817} 818 819const struct pinmux_bias_reg * 820rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, 821 unsigned int *bit) 822{ 823 unsigned int i, j; 824 825 for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) { 826 for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) { 827 if (info->bias_regs[i].pins[j] == pin) { 828 *bit = j; 829 return &info->bias_regs[i]; 830 } 831 } 832 } 833 834 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); 835 836 return NULL; 837} 838 839unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 840{ 841 const struct pinmux_bias_reg *reg; 842 unsigned int bit; 843 844 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 845 if (!reg) 846 return PIN_CONFIG_BIAS_DISABLE; 847 848 if (reg->puen) { 849 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 850 return PIN_CONFIG_BIAS_DISABLE; 851 else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) 852 return PIN_CONFIG_BIAS_PULL_UP; 853 else 854 return PIN_CONFIG_BIAS_PULL_DOWN; 855 } else { 856 if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 857 return PIN_CONFIG_BIAS_PULL_DOWN; 858 else 859 return PIN_CONFIG_BIAS_DISABLE; 860 } 861} 862 863void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 864 unsigned int bias) 865{ 866 const struct pinmux_bias_reg *reg; 867 u32 enable, updown; 868 unsigned int bit; 869 870 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 871 if (!reg) 872 return; 873 874 if (reg->puen) { 875 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 876 if (bias != PIN_CONFIG_BIAS_DISABLE) { 877 enable |= BIT(bit); 878 879 if (reg->pud) { 880 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 881 if (bias == PIN_CONFIG_BIAS_PULL_UP) 882 updown |= BIT(bit); 883 884 sh_pfc_write(pfc, reg->pud, updown); 885 } 886 } 887 sh_pfc_write(pfc, reg->puen, enable); 888 } else { 889 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 890 if (bias == PIN_CONFIG_BIAS_PULL_DOWN) 891 enable |= BIT(bit); 892 893 sh_pfc_write(pfc, reg->pud, enable); 894 } 895} 896 897#define PORTnCR_PULMD_OFF (0 << 6) 898#define PORTnCR_PULMD_DOWN (2 << 6) 899#define PORTnCR_PULMD_UP (3 << 6) 900#define PORTnCR_PULMD_MASK (3 << 6) 901 902unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 903{ 904 void __iomem *reg = pfc->windows->virt + 905 pfc->info->ops->pin_to_portcr(pin); 906 u32 value = ioread8(reg) & PORTnCR_PULMD_MASK; 907 908 switch (value) { 909 case PORTnCR_PULMD_UP: 910 return PIN_CONFIG_BIAS_PULL_UP; 911 case PORTnCR_PULMD_DOWN: 912 return PIN_CONFIG_BIAS_PULL_DOWN; 913 case PORTnCR_PULMD_OFF: 914 default: 915 return PIN_CONFIG_BIAS_DISABLE; 916 } 917} 918 919void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 920 unsigned int bias) 921{ 922 void __iomem *reg = pfc->windows->virt + 923 pfc->info->ops->pin_to_portcr(pin); 924 u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK; 925 926 switch (bias) { 927 case PIN_CONFIG_BIAS_PULL_UP: 928 value |= PORTnCR_PULMD_UP; 929 break; 930 case PIN_CONFIG_BIAS_PULL_DOWN: 931 value |= PORTnCR_PULMD_DOWN; 932 break; 933 } 934 935 iowrite8(value, reg); 936} 937