1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC 4 * 5 * Copyright (C) 2017 Jacopo Mondi 6 */ 7 8/* 9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1 10 * family. 11 * This includes SoCs which are sub- or super- sets of this particular line, 12 * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020). 13 */ 14 15#include <linux/bitops.h> 16#include <linux/err.h> 17#include <linux/gpio/driver.h> 18#include <linux/init.h> 19#include <linux/ioport.h> 20#include <linux/module.h> 21#include <linux/of.h> 22#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinmux.h> 25#include <linux/platform_device.h> 26#include <linux/property.h> 27#include <linux/slab.h> 28 29#include "../core.h" 30#include "../devicetree.h" 31#include "../pinconf.h" 32#include "../pinmux.h" 33 34#define DRIVER_NAME "pinctrl-rza1" 35 36#define RZA1_P_REG 0x0000 37#define RZA1_PPR_REG 0x0200 38#define RZA1_PM_REG 0x0300 39#define RZA1_PMC_REG 0x0400 40#define RZA1_PFC_REG 0x0500 41#define RZA1_PFCE_REG 0x0600 42#define RZA1_PFCEA_REG 0x0a00 43#define RZA1_PIBC_REG 0x4000 44#define RZA1_PBDC_REG 0x4100 45#define RZA1_PIPC_REG 0x4200 46 47#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4)) 48 49#define RZA1_NPORTS 12 50#define RZA1_PINS_PER_PORT 16 51#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS) 52#define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT) 53#define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT) 54 55/* 56 * Use 16 lower bits [15:0] for pin identifier 57 * Use 16 higher bits [31:16] for pin mux function 58 */ 59#define MUX_PIN_ID_MASK GENMASK(15, 0) 60#define MUX_FUNC_MASK GENMASK(31, 16) 61 62#define MUX_FUNC_OFFS 16 63#define MUX_FUNC(pinconf) \ 64 ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 65#define MUX_FUNC_PFC_MASK BIT(0) 66#define MUX_FUNC_PFCE_MASK BIT(1) 67#define MUX_FUNC_PFCEA_MASK BIT(2) 68 69/* Pin mux flags */ 70#define MUX_FLAGS_BIDIR BIT(0) 71#define MUX_FLAGS_SWIO_INPUT BIT(1) 72#define MUX_FLAGS_SWIO_OUTPUT BIT(2) 73 74/* ---------------------------------------------------------------------------- 75 * RZ/A1 pinmux flags 76 */ 77 78/* 79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied. 80 */ 81struct rza1_bidir_pin { 82 u8 pin: 4; 83 u8 func: 4; 84}; 85 86/* 87 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied. 88 * Each struct rza1_bidir_entry describes a port. 89 */ 90struct rza1_bidir_entry { 91 const unsigned int npins; 92 const struct rza1_bidir_pin *pins; 93}; 94 95/* 96 * rza1_swio_pin - describe a single pin that needs swio flag applied. 97 */ 98struct rza1_swio_pin { 99 u16 pin: 4; 100 u16 port: 4; 101 u16 func: 4; 102 u16 input: 1; 103}; 104 105/* 106 * rza1_swio_entry - describe a list of pins that needs swio flag applied 107 */ 108struct rza1_swio_entry { 109 const unsigned int npins; 110 const struct rza1_swio_pin *pins; 111}; 112 113/* 114 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables 115 */ 116struct rza1_pinmux_conf { 117 const struct rza1_bidir_entry *bidir_entries; 118 const struct rza1_swio_entry *swio_entries; 119}; 120 121/* ---------------------------------------------------------------------------- 122 * RZ/A1H (r7s72100) pinmux flags 123 */ 124 125static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = { 126 { .pin = 0, .func = 1 }, 127 { .pin = 1, .func = 1 }, 128 { .pin = 2, .func = 1 }, 129 { .pin = 3, .func = 1 }, 130 { .pin = 4, .func = 1 }, 131 { .pin = 5, .func = 1 }, 132 { .pin = 6, .func = 1 }, 133 { .pin = 7, .func = 1 }, 134}; 135 136static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = { 137 { .pin = 0, .func = 1 }, 138 { .pin = 1, .func = 1 }, 139 { .pin = 2, .func = 1 }, 140 { .pin = 3, .func = 1 }, 141 { .pin = 4, .func = 1 }, 142 { .pin = 0, .func = 4 }, 143 { .pin = 1, .func = 4 }, 144 { .pin = 2, .func = 4 }, 145 { .pin = 3, .func = 4 }, 146 { .pin = 5, .func = 1 }, 147 { .pin = 6, .func = 1 }, 148 { .pin = 7, .func = 1 }, 149 { .pin = 8, .func = 1 }, 150 { .pin = 9, .func = 1 }, 151 { .pin = 10, .func = 1 }, 152 { .pin = 11, .func = 1 }, 153 { .pin = 12, .func = 1 }, 154 { .pin = 13, .func = 1 }, 155 { .pin = 14, .func = 1 }, 156 { .pin = 15, .func = 1 }, 157 { .pin = 12, .func = 4 }, 158 { .pin = 13, .func = 4 }, 159 { .pin = 14, .func = 4 }, 160 { .pin = 15, .func = 4 }, 161}; 162 163static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = { 164 { .pin = 3, .func = 2 }, 165 { .pin = 10, .func = 7 }, 166 { .pin = 11, .func = 7 }, 167 { .pin = 13, .func = 7 }, 168 { .pin = 14, .func = 7 }, 169 { .pin = 15, .func = 7 }, 170 { .pin = 10, .func = 8 }, 171 { .pin = 11, .func = 8 }, 172 { .pin = 13, .func = 8 }, 173 { .pin = 14, .func = 8 }, 174 { .pin = 15, .func = 8 }, 175}; 176 177static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = { 178 { .pin = 0, .func = 8 }, 179 { .pin = 1, .func = 8 }, 180 { .pin = 2, .func = 8 }, 181 { .pin = 3, .func = 8 }, 182 { .pin = 10, .func = 3 }, 183 { .pin = 11, .func = 3 }, 184 { .pin = 13, .func = 3 }, 185 { .pin = 14, .func = 3 }, 186 { .pin = 15, .func = 3 }, 187 { .pin = 10, .func = 4 }, 188 { .pin = 11, .func = 4 }, 189 { .pin = 13, .func = 4 }, 190 { .pin = 14, .func = 4 }, 191 { .pin = 15, .func = 4 }, 192 { .pin = 12, .func = 5 }, 193 { .pin = 13, .func = 5 }, 194 { .pin = 14, .func = 5 }, 195 { .pin = 15, .func = 5 }, 196}; 197 198static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = { 199 { .pin = 0, .func = 1 }, 200 { .pin = 1, .func = 1 }, 201 { .pin = 2, .func = 1 }, 202 { .pin = 3, .func = 1 }, 203 { .pin = 4, .func = 1 }, 204 { .pin = 5, .func = 1 }, 205 { .pin = 6, .func = 1 }, 206 { .pin = 7, .func = 1 }, 207 { .pin = 8, .func = 1 }, 208 { .pin = 9, .func = 1 }, 209 { .pin = 10, .func = 1 }, 210 { .pin = 11, .func = 1 }, 211 { .pin = 12, .func = 1 }, 212 { .pin = 13, .func = 1 }, 213 { .pin = 14, .func = 1 }, 214 { .pin = 15, .func = 1 }, 215}; 216 217static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = { 218 { .pin = 13, .func = 3 }, 219}; 220 221static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = { 222 { .pin = 8, .func = 3 }, 223 { .pin = 9, .func = 3 }, 224 { .pin = 10, .func = 3 }, 225 { .pin = 11, .func = 3 }, 226 { .pin = 14, .func = 2 }, 227 { .pin = 15, .func = 2 }, 228 { .pin = 14, .func = 3 }, 229 { .pin = 15, .func = 3 }, 230}; 231 232static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = { 233 { .pin = 0, .func = 2 }, 234 { .pin = 1, .func = 2 }, 235 { .pin = 4, .func = 2 }, 236 { .pin = 5, .func = 2 }, 237 { .pin = 6, .func = 2 }, 238 { .pin = 7, .func = 2 }, 239}; 240 241static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = { 242 { .pin = 6, .func = 2 }, 243 { .pin = 7, .func = 2 }, 244 { .pin = 9, .func = 2 }, 245 { .pin = 6, .func = 4 }, 246 { .pin = 7, .func = 4 }, 247 { .pin = 9, .func = 4 }, 248 { .pin = 10, .func = 2 }, 249 { .pin = 11, .func = 2 }, 250 { .pin = 10, .func = 4 }, 251 { .pin = 11, .func = 4 }, 252 { .pin = 12, .func = 4 }, 253 { .pin = 13, .func = 4 }, 254 { .pin = 14, .func = 4 }, 255 { .pin = 15, .func = 4 }, 256}; 257 258static const struct rza1_swio_pin rza1h_swio_pins[] = { 259 { .port = 2, .pin = 7, .func = 4, .input = 0 }, 260 { .port = 2, .pin = 11, .func = 4, .input = 0 }, 261 { .port = 3, .pin = 7, .func = 3, .input = 0 }, 262 { .port = 3, .pin = 7, .func = 8, .input = 0 }, 263 { .port = 4, .pin = 7, .func = 5, .input = 0 }, 264 { .port = 4, .pin = 7, .func = 11, .input = 0 }, 265 { .port = 4, .pin = 15, .func = 6, .input = 0 }, 266 { .port = 5, .pin = 0, .func = 1, .input = 1 }, 267 { .port = 5, .pin = 1, .func = 1, .input = 1 }, 268 { .port = 5, .pin = 2, .func = 1, .input = 1 }, 269 { .port = 5, .pin = 3, .func = 1, .input = 1 }, 270 { .port = 5, .pin = 4, .func = 1, .input = 1 }, 271 { .port = 5, .pin = 5, .func = 1, .input = 1 }, 272 { .port = 5, .pin = 6, .func = 1, .input = 1 }, 273 { .port = 5, .pin = 7, .func = 1, .input = 1 }, 274 { .port = 7, .pin = 4, .func = 6, .input = 0 }, 275 { .port = 7, .pin = 11, .func = 2, .input = 0 }, 276 { .port = 8, .pin = 10, .func = 8, .input = 0 }, 277 { .port = 10, .pin = 15, .func = 2, .input = 0 }, 278}; 279 280static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = { 281 [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 }, 282 [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 }, 283 [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 }, 284 [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 }, 285 [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 }, 286 [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 }, 287 [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 }, 288 [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 }, 289 [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 }, 290}; 291 292static const struct rza1_swio_entry rza1h_swio_entries[] = { 293 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, 294}; 295 296/* RZ/A1H (r7s72100x) pinmux flags table */ 297static const struct rza1_pinmux_conf rza1h_pmx_conf = { 298 .bidir_entries = rza1h_bidir_entries, 299 .swio_entries = rza1h_swio_entries, 300}; 301 302/* ---------------------------------------------------------------------------- 303 * RZ/A1L (r7s72102) pinmux flags 304 */ 305 306static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = { 307 { .pin = 0, .func = 1 }, 308 { .pin = 1, .func = 1 }, 309 { .pin = 2, .func = 1 }, 310 { .pin = 3, .func = 1 }, 311 { .pin = 4, .func = 1 }, 312 { .pin = 5, .func = 1 }, 313 { .pin = 6, .func = 1 }, 314 { .pin = 7, .func = 1 }, 315}; 316 317static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = { 318 { .pin = 0, .func = 2 }, 319 { .pin = 1, .func = 2 }, 320 { .pin = 2, .func = 2 }, 321 { .pin = 4, .func = 2 }, 322 { .pin = 5, .func = 2 }, 323 { .pin = 10, .func = 2 }, 324 { .pin = 11, .func = 2 }, 325 { .pin = 12, .func = 2 }, 326 { .pin = 13, .func = 2 }, 327}; 328 329static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = { 330 { .pin = 1, .func = 4 }, 331 { .pin = 2, .func = 2 }, 332 { .pin = 3, .func = 2 }, 333 { .pin = 6, .func = 2 }, 334 { .pin = 7, .func = 2 }, 335}; 336 337static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = { 338 { .pin = 0, .func = 1 }, 339 { .pin = 1, .func = 1 }, 340 { .pin = 2, .func = 1 }, 341 { .pin = 3, .func = 1 }, 342 { .pin = 4, .func = 1 }, 343 { .pin = 5, .func = 1 }, 344 { .pin = 6, .func = 1 }, 345 { .pin = 7, .func = 1 }, 346 { .pin = 8, .func = 1 }, 347 { .pin = 9, .func = 1 }, 348 { .pin = 10, .func = 1 }, 349 { .pin = 11, .func = 1 }, 350 { .pin = 12, .func = 1 }, 351 { .pin = 13, .func = 1 }, 352 { .pin = 14, .func = 1 }, 353 { .pin = 15, .func = 1 }, 354 { .pin = 0, .func = 2 }, 355 { .pin = 1, .func = 2 }, 356 { .pin = 2, .func = 2 }, 357 { .pin = 3, .func = 2 }, 358}; 359 360static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = { 361 { .pin = 0, .func = 1 }, 362 { .pin = 1, .func = 1 }, 363 { .pin = 2, .func = 1 }, 364 { .pin = 3, .func = 1 }, 365 { .pin = 4, .func = 1 }, 366 { .pin = 5, .func = 1 }, 367 { .pin = 6, .func = 1 }, 368 { .pin = 7, .func = 1 }, 369 { .pin = 8, .func = 1 }, 370 { .pin = 9, .func = 1 }, 371 { .pin = 10, .func = 1 }, 372 { .pin = 11, .func = 1 }, 373 { .pin = 12, .func = 1 }, 374 { .pin = 13, .func = 1 }, 375 { .pin = 14, .func = 1 }, 376 { .pin = 15, .func = 1 }, 377}; 378 379static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = { 380 { .pin = 2, .func = 2 }, 381 { .pin = 3, .func = 2 }, 382 { .pin = 5, .func = 2 }, 383 { .pin = 6, .func = 2 }, 384 { .pin = 7, .func = 2 }, 385 { .pin = 2, .func = 3 }, 386 { .pin = 3, .func = 3 }, 387 { .pin = 5, .func = 3 }, 388 { .pin = 6, .func = 3 }, 389 { .pin = 7, .func = 3 }, 390}; 391 392static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = { 393 { .pin = 1, .func = 2 }, 394 { .pin = 0, .func = 3 }, 395 { .pin = 1, .func = 3 }, 396 { .pin = 3, .func = 3 }, 397 { .pin = 4, .func = 3 }, 398 { .pin = 5, .func = 3 }, 399}; 400 401static const struct rza1_swio_pin rza1l_swio_pins[] = { 402 { .port = 2, .pin = 8, .func = 2, .input = 0 }, 403 { .port = 5, .pin = 6, .func = 3, .input = 0 }, 404 { .port = 6, .pin = 6, .func = 3, .input = 0 }, 405 { .port = 6, .pin = 10, .func = 3, .input = 0 }, 406 { .port = 7, .pin = 10, .func = 2, .input = 0 }, 407 { .port = 8, .pin = 2, .func = 3, .input = 0 }, 408}; 409 410static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { 411 [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 }, 412 [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 }, 413 [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 }, 414 [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 }, 415 [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 }, 416 [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 }, 417 [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 }, 418}; 419 420static const struct rza1_swio_entry rza1l_swio_entries[] = { 421 [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins }, 422}; 423 424/* RZ/A1L (r7s72102x) pinmux flags table */ 425static const struct rza1_pinmux_conf rza1l_pmx_conf = { 426 .bidir_entries = rza1l_bidir_entries, 427 .swio_entries = rza1l_swio_entries, 428}; 429 430/* ---------------------------------------------------------------------------- 431 * RZ/A1 types 432 */ 433/** 434 * struct rza1_mux_conf - describes a pin multiplexing operation 435 * 436 * @id: the pin identifier from 0 to RZA1_NPINS 437 * @port: the port where pin sits on 438 * @pin: pin id 439 * @mux_func: alternate function id number 440 * @mux_flags: alternate function flags 441 * @value: output value to set the pin to 442 */ 443struct rza1_mux_conf { 444 u16 id; 445 u8 port; 446 u8 pin; 447 u8 mux_func; 448 u8 mux_flags; 449 u8 value; 450}; 451 452/** 453 * struct rza1_port - describes a pin port 454 * 455 * This is mostly useful to lock register writes per-bank and not globally. 456 * 457 * @lock: protect access to HW registers 458 * @id: port number 459 * @base: logical address base 460 * @pins: pins sitting on this port 461 */ 462struct rza1_port { 463 spinlock_t lock; 464 unsigned int id; 465 void __iomem *base; 466 struct pinctrl_pin_desc *pins; 467}; 468 469/** 470 * struct rza1_pinctrl - RZ pincontroller device 471 * 472 * @dev: parent device structure 473 * @mutex: protect [pinctrl|pinmux]_generic functions 474 * @base: logical address base 475 * @nport: number of pin controller ports 476 * @ports: pin controller banks 477 * @pins: pin array for pinctrl core 478 * @desc: pincontroller desc for pinctrl core 479 * @pctl: pinctrl device 480 * @data: device specific data 481 */ 482struct rza1_pinctrl { 483 struct device *dev; 484 485 struct mutex mutex; 486 487 void __iomem *base; 488 489 unsigned int nport; 490 struct rza1_port *ports; 491 492 struct pinctrl_pin_desc *pins; 493 struct pinctrl_desc desc; 494 struct pinctrl_dev *pctl; 495 496 const void *data; 497}; 498 499/* ---------------------------------------------------------------------------- 500 * RZ/A1 pinmux flags 501 */ 502static inline bool rza1_pinmux_get_bidir(unsigned int port, 503 unsigned int pin, 504 unsigned int func, 505 const struct rza1_bidir_entry *table) 506{ 507 const struct rza1_bidir_entry *entry = &table[port]; 508 const struct rza1_bidir_pin *bidir_pin; 509 unsigned int i; 510 511 for (i = 0; i < entry->npins; ++i) { 512 bidir_pin = &entry->pins[i]; 513 if (bidir_pin->pin == pin && bidir_pin->func == func) 514 return true; 515 } 516 517 return false; 518} 519 520static inline int rza1_pinmux_get_swio(unsigned int port, 521 unsigned int pin, 522 unsigned int func, 523 const struct rza1_swio_entry *table) 524{ 525 const struct rza1_swio_pin *swio_pin; 526 unsigned int i; 527 528 529 for (i = 0; i < table->npins; ++i) { 530 swio_pin = &table->pins[i]; 531 if (swio_pin->port == port && swio_pin->pin == pin && 532 swio_pin->func == func) 533 return swio_pin->input; 534 } 535 536 return -ENOENT; 537} 538 539/* 540 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin 541 */ 542static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, 543 unsigned int func, 544 struct rza1_pinctrl *rza1_pctl) 545 546{ 547 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data; 548 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries; 549 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries; 550 unsigned int pmx_flags = 0; 551 int ret; 552 553 if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries)) 554 pmx_flags |= MUX_FLAGS_BIDIR; 555 556 ret = rza1_pinmux_get_swio(port, pin, func, swio_entries); 557 if (ret == 0) 558 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT; 559 else if (ret > 0) 560 pmx_flags |= MUX_FLAGS_SWIO_INPUT; 561 562 return pmx_flags; 563} 564 565/* ---------------------------------------------------------------------------- 566 * RZ/A1 SoC operations 567 */ 568 569/* 570 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration 571 * registers 572 */ 573static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg, 574 unsigned int bit, bool set) 575{ 576 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); 577 u16 val = ioread16(mem); 578 579 if (set) 580 val |= BIT(bit); 581 else 582 val &= ~BIT(bit); 583 584 iowrite16(val, mem); 585} 586 587static inline unsigned int rza1_get_bit(struct rza1_port *port, 588 unsigned int reg, unsigned int bit) 589{ 590 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); 591 592 return ioread16(mem) & BIT(bit); 593} 594 595/** 596 * rza1_pin_reset() - reset a pin to default initial state 597 * 598 * Reset pin state disabling input buffer and bi-directional control, 599 * and configure it as input port. 600 * Note that pin is now configured with direction as input but with input 601 * buffer disabled. This implies the pin value cannot be read in this state. 602 * 603 * @port: port where pin sits on 604 * @pin: pin offset 605 */ 606static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) 607{ 608 unsigned long irqflags; 609 610 spin_lock_irqsave(&port->lock, irqflags); 611 rza1_set_bit(port, RZA1_PIBC_REG, pin, 0); 612 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); 613 614 rza1_set_bit(port, RZA1_PM_REG, pin, 1); 615 rza1_set_bit(port, RZA1_PMC_REG, pin, 0); 616 rza1_set_bit(port, RZA1_PIPC_REG, pin, 0); 617 spin_unlock_irqrestore(&port->lock, irqflags); 618} 619 620/** 621 * rza1_pin_set_direction() - set I/O direction on a pin in port mode 622 * 623 * When running in output port mode keep PBDC enabled to allow reading the 624 * pin value from PPR. 625 * 626 * @port: port where pin sits on 627 * @pin: pin offset 628 * @input: input enable/disable flag 629 */ 630static inline void rza1_pin_set_direction(struct rza1_port *port, 631 unsigned int pin, bool input) 632{ 633 unsigned long irqflags; 634 635 spin_lock_irqsave(&port->lock, irqflags); 636 637 rza1_set_bit(port, RZA1_PIBC_REG, pin, 1); 638 if (input) { 639 rza1_set_bit(port, RZA1_PM_REG, pin, 1); 640 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); 641 } else { 642 rza1_set_bit(port, RZA1_PM_REG, pin, 0); 643 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); 644 } 645 646 spin_unlock_irqrestore(&port->lock, irqflags); 647} 648 649static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, 650 unsigned int value) 651{ 652 unsigned long irqflags; 653 654 spin_lock_irqsave(&port->lock, irqflags); 655 rza1_set_bit(port, RZA1_P_REG, pin, !!value); 656 spin_unlock_irqrestore(&port->lock, irqflags); 657} 658 659static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) 660{ 661 return rza1_get_bit(port, RZA1_PPR_REG, pin); 662} 663 664/** 665 * rza1_pin_mux_single() - configure pin multiplexing on a single pin 666 * 667 * @rza1_pctl: RZ/A1 pin controller device 668 * @mux_conf: pin multiplexing descriptor 669 */ 670static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, 671 struct rza1_mux_conf *mux_conf) 672{ 673 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port]; 674 unsigned int pin = mux_conf->pin; 675 u8 mux_func = mux_conf->mux_func; 676 u8 mux_flags = mux_conf->mux_flags; 677 u8 mux_flags_from_table; 678 679 rza1_pin_reset(port, pin); 680 681 /* SWIO pinmux flags coming from DT are high precedence */ 682 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func, 683 rza1_pctl); 684 if (mux_flags) 685 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR); 686 else 687 mux_flags = mux_flags_from_table; 688 689 if (mux_flags & MUX_FLAGS_BIDIR) 690 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); 691 692 /* 693 * Enable alternate function mode and select it. 694 * 695 * Be careful here: the pin mux sub-nodes in device tree 696 * enumerate alternate functions from 1 to 8; 697 * subtract 1 before using macros to match registers configuration 698 * which expects numbers from 0 to 7 instead. 699 * 700 * ---------------------------------------------------- 701 * Alternate mode selection table: 702 * 703 * PMC PFC PFCE PFCAE (mux_func - 1) 704 * 1 0 0 0 0 705 * 1 1 0 0 1 706 * 1 0 1 0 2 707 * 1 1 1 0 3 708 * 1 0 0 1 4 709 * 1 1 0 1 5 710 * 1 0 1 1 6 711 * 1 1 1 1 7 712 * ---------------------------------------------------- 713 */ 714 mux_func -= 1; 715 rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK); 716 rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK); 717 rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK); 718 719 /* 720 * All alternate functions except a few need PIPCn = 1. 721 * If PIPCn has to stay disabled (SW IO mode), configure PMn according 722 * to I/O direction specified by pin configuration -after- PMC has been 723 * set to one. 724 */ 725 if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT)) 726 rza1_set_bit(port, RZA1_PM_REG, pin, 727 mux_flags & MUX_FLAGS_SWIO_INPUT); 728 else 729 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1); 730 731 rza1_set_bit(port, RZA1_PMC_REG, pin, 1); 732 733 return 0; 734} 735 736/* ---------------------------------------------------------------------------- 737 * gpio operations 738 */ 739 740/** 741 * rza1_gpio_request() - configure pin in port mode 742 * 743 * Configure a pin as gpio (port mode). 744 * After reset, the pin is in input mode with input buffer disabled. 745 * To use the pin as input or output, set_direction shall be called first 746 * 747 * @chip: gpio chip where the gpio sits on 748 * @gpio: gpio offset 749 */ 750static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio) 751{ 752 struct rza1_port *port = gpiochip_get_data(chip); 753 754 rza1_pin_reset(port, gpio); 755 756 return 0; 757} 758 759/** 760 * rza1_gpio_free() - reset a pin 761 * 762 * Surprisingly, freeing a gpio is equivalent to requesting it. 763 * Reset pin to port mode, with input buffer disabled. This overwrites all 764 * port direction settings applied with set_direction 765 * 766 * @chip: gpio chip where the gpio sits on 767 * @gpio: gpio offset 768 */ 769static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio) 770{ 771 struct rza1_port *port = gpiochip_get_data(chip); 772 773 rza1_pin_reset(port, gpio); 774} 775 776static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 777{ 778 struct rza1_port *port = gpiochip_get_data(chip); 779 780 if (rza1_get_bit(port, RZA1_PM_REG, gpio)) 781 return GPIO_LINE_DIRECTION_IN; 782 783 return GPIO_LINE_DIRECTION_OUT; 784} 785 786static int rza1_gpio_direction_input(struct gpio_chip *chip, 787 unsigned int gpio) 788{ 789 struct rza1_port *port = gpiochip_get_data(chip); 790 791 rza1_pin_set_direction(port, gpio, true); 792 793 return 0; 794} 795 796static int rza1_gpio_direction_output(struct gpio_chip *chip, 797 unsigned int gpio, 798 int value) 799{ 800 struct rza1_port *port = gpiochip_get_data(chip); 801 802 /* Set value before driving pin direction */ 803 rza1_pin_set(port, gpio, value); 804 rza1_pin_set_direction(port, gpio, false); 805 806 return 0; 807} 808 809/** 810 * rza1_gpio_get() - read a gpio pin value 811 * 812 * Read gpio pin value through PPR register. 813 * Requires bi-directional mode to work when reading the value of a pin 814 * in output mode 815 * 816 * @chip: gpio chip where the gpio sits on 817 * @gpio: gpio offset 818 */ 819static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio) 820{ 821 struct rza1_port *port = gpiochip_get_data(chip); 822 823 return rza1_pin_get(port, gpio); 824} 825 826static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio, 827 int value) 828{ 829 struct rza1_port *port = gpiochip_get_data(chip); 830 831 rza1_pin_set(port, gpio, value); 832} 833 834static const struct gpio_chip rza1_gpiochip_template = { 835 .request = rza1_gpio_request, 836 .free = rza1_gpio_free, 837 .get_direction = rza1_gpio_get_direction, 838 .direction_input = rza1_gpio_direction_input, 839 .direction_output = rza1_gpio_direction_output, 840 .get = rza1_gpio_get, 841 .set = rza1_gpio_set, 842}; 843/* ---------------------------------------------------------------------------- 844 * pinctrl operations 845 */ 846 847/** 848 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its 849 * children sub-nodes 850 * 851 * @np: device tree node to parse 852 */ 853static int rza1_dt_node_pin_count(struct device_node *np) 854{ 855 struct device_node *child; 856 struct property *of_pins; 857 unsigned int npins; 858 859 of_pins = of_find_property(np, "pinmux", NULL); 860 if (of_pins) 861 return of_pins->length / sizeof(u32); 862 863 npins = 0; 864 for_each_child_of_node(np, child) { 865 of_pins = of_find_property(child, "pinmux", NULL); 866 if (!of_pins) { 867 of_node_put(child); 868 return -EINVAL; 869 } 870 871 npins += of_pins->length / sizeof(u32); 872 } 873 874 return npins; 875} 876 877/** 878 * rza1_parse_pinmux_node() - parse a pin mux sub-node 879 * 880 * @rza1_pctl: RZ/A1 pin controller device 881 * @np: of pmx sub-node 882 * @mux_confs: array of pin mux configurations to fill with parsed info 883 * @grpins: array of pin ids to mux 884 */ 885static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, 886 struct device_node *np, 887 struct rza1_mux_conf *mux_confs, 888 unsigned int *grpins) 889{ 890 struct pinctrl_dev *pctldev = rza1_pctl->pctl; 891 char const *prop_name = "pinmux"; 892 unsigned long *pin_configs; 893 unsigned int npin_configs; 894 struct property *of_pins; 895 unsigned int npins; 896 u8 pinmux_flags; 897 unsigned int i; 898 int ret; 899 900 of_pins = of_find_property(np, prop_name, NULL); 901 if (!of_pins) { 902 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name); 903 return -ENOENT; 904 } 905 npins = of_pins->length / sizeof(u32); 906 907 /* 908 * Collect pin configuration properties: they apply to all pins in 909 * this sub-node 910 */ 911 ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs, 912 &npin_configs); 913 if (ret) { 914 dev_err(rza1_pctl->dev, 915 "Unable to parse pin configuration options for %pOFn\n", 916 np); 917 return ret; 918 } 919 920 /* 921 * Create a mask with pinmux flags from pin configuration; 922 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction 923 * specified in device tree. 924 */ 925 pinmux_flags = 0; 926 for (i = 0; i < npin_configs && pinmux_flags == 0; i++) 927 switch (pinconf_to_config_param(pin_configs[i])) { 928 case PIN_CONFIG_INPUT_ENABLE: 929 pinmux_flags |= MUX_FLAGS_SWIO_INPUT; 930 break; 931 case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */ 932 case PIN_CONFIG_OUTPUT_ENABLE: 933 pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT; 934 break; 935 default: 936 break; 937 938 } 939 940 kfree(pin_configs); 941 942 /* Collect pin positions and their mux settings. */ 943 for (i = 0; i < npins; ++i) { 944 u32 of_pinconf; 945 struct rza1_mux_conf *mux_conf = &mux_confs[i]; 946 947 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf); 948 if (ret) 949 return ret; 950 951 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK; 952 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id); 953 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id); 954 mux_conf->mux_func = MUX_FUNC(of_pinconf); 955 mux_conf->mux_flags = pinmux_flags; 956 957 if (mux_conf->port >= RZA1_NPORTS || 958 mux_conf->pin >= RZA1_PINS_PER_PORT) { 959 dev_err(rza1_pctl->dev, 960 "Wrong port %u pin %u for %s property\n", 961 mux_conf->port, mux_conf->pin, prop_name); 962 return -EINVAL; 963 } 964 965 grpins[i] = mux_conf->id; 966 } 967 968 return npins; 969} 970 971/** 972 * rza1_dt_node_to_map() - map a pin mux node to a function/group 973 * 974 * Parse and register a pin mux function. 975 * 976 * @pctldev: pin controller device 977 * @np: device tree node to parse 978 * @map: pointer to pin map (output) 979 * @num_maps: number of collected maps (output) 980 */ 981static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev, 982 struct device_node *np, 983 struct pinctrl_map **map, 984 unsigned int *num_maps) 985{ 986 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev); 987 struct rza1_mux_conf *mux_confs, *mux_conf; 988 unsigned int *grpins, *grpin; 989 struct device_node *child; 990 const char *grpname; 991 const char **fngrps; 992 int ret, npins; 993 int gsel, fsel; 994 995 npins = rza1_dt_node_pin_count(np); 996 if (npins < 0) { 997 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n"); 998 return -EINVAL; 999 } 1000 1001 /* 1002 * Functions are made of 1 group only; 1003 * in fact, functions and groups are identical for this pin controller 1004 * except that functions carry an array of per-pin mux configuration 1005 * settings. 1006 */ 1007 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs), 1008 GFP_KERNEL); 1009 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins), 1010 GFP_KERNEL); 1011 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL); 1012 1013 if (!mux_confs || !grpins || !fngrps) 1014 return -ENOMEM; 1015 1016 /* 1017 * Parse the pinmux node. 1018 * If the node does not contain "pinmux" property (-ENOENT) 1019 * that property shall be specified in all its children sub-nodes. 1020 */ 1021 mux_conf = &mux_confs[0]; 1022 grpin = &grpins[0]; 1023 1024 ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin); 1025 if (ret == -ENOENT) 1026 for_each_child_of_node(np, child) { 1027 ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf, 1028 grpin); 1029 if (ret < 0) { 1030 of_node_put(child); 1031 return ret; 1032 } 1033 1034 grpin += ret; 1035 mux_conf += ret; 1036 } 1037 else if (ret < 0) 1038 return ret; 1039 1040 /* Register pin group and function name to pinctrl_generic */ 1041 grpname = np->name; 1042 fngrps[0] = grpname; 1043 1044 mutex_lock(&rza1_pctl->mutex); 1045 gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins, 1046 NULL); 1047 if (gsel < 0) { 1048 mutex_unlock(&rza1_pctl->mutex); 1049 return gsel; 1050 } 1051 1052 fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1, 1053 mux_confs); 1054 if (fsel < 0) { 1055 ret = fsel; 1056 goto remove_group; 1057 } 1058 1059 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n", 1060 grpname, npins); 1061 1062 /* Create map where to retrieve function and mux settings from */ 1063 *num_maps = 0; 1064 *map = kzalloc(sizeof(**map), GFP_KERNEL); 1065 if (!*map) { 1066 ret = -ENOMEM; 1067 goto remove_function; 1068 } 1069 1070 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 1071 (*map)->data.mux.group = np->name; 1072 (*map)->data.mux.function = np->name; 1073 *num_maps = 1; 1074 mutex_unlock(&rza1_pctl->mutex); 1075 1076 return 0; 1077 1078remove_function: 1079 pinmux_generic_remove_function(pctldev, fsel); 1080 1081remove_group: 1082 pinctrl_generic_remove_group(pctldev, gsel); 1083 mutex_unlock(&rza1_pctl->mutex); 1084 1085 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n", 1086 grpname); 1087 1088 return ret; 1089} 1090 1091static void rza1_dt_free_map(struct pinctrl_dev *pctldev, 1092 struct pinctrl_map *map, unsigned int num_maps) 1093{ 1094 kfree(map); 1095} 1096 1097static const struct pinctrl_ops rza1_pinctrl_ops = { 1098 .get_groups_count = pinctrl_generic_get_group_count, 1099 .get_group_name = pinctrl_generic_get_group_name, 1100 .get_group_pins = pinctrl_generic_get_group_pins, 1101 .dt_node_to_map = rza1_dt_node_to_map, 1102 .dt_free_map = rza1_dt_free_map, 1103}; 1104 1105/* ---------------------------------------------------------------------------- 1106 * pinmux operations 1107 */ 1108 1109/** 1110 * rza1_set_mux() - retrieve pins from a group and apply their mux settings 1111 * 1112 * @pctldev: pin controller device 1113 * @selector: function selector 1114 * @group: group selector 1115 */ 1116static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1117 unsigned int group) 1118{ 1119 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev); 1120 struct rza1_mux_conf *mux_confs; 1121 struct function_desc *func; 1122 struct group_desc *grp; 1123 int i; 1124 1125 grp = pinctrl_generic_get_group(pctldev, group); 1126 if (!grp) 1127 return -EINVAL; 1128 1129 func = pinmux_generic_get_function(pctldev, selector); 1130 if (!func) 1131 return -EINVAL; 1132 1133 mux_confs = (struct rza1_mux_conf *)func->data; 1134 for (i = 0; i < grp->grp.npins; ++i) { 1135 int ret; 1136 1137 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]); 1138 if (ret) 1139 return ret; 1140 } 1141 1142 return 0; 1143} 1144 1145static const struct pinmux_ops rza1_pinmux_ops = { 1146 .get_functions_count = pinmux_generic_get_function_count, 1147 .get_function_name = pinmux_generic_get_function_name, 1148 .get_function_groups = pinmux_generic_get_function_groups, 1149 .set_mux = rza1_set_mux, 1150 .strict = true, 1151}; 1152 1153/* ---------------------------------------------------------------------------- 1154 * RZ/A1 pin controller driver operations 1155 */ 1156 1157/** 1158 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range 1159 * 1160 * The gpio controller subnode shall provide a "gpio-ranges" list property as 1161 * defined by gpio device tree binding documentation. 1162 * 1163 * @rza1_pctl: RZ/A1 pin controller device 1164 * @fwnode: gpio-controller firmware node 1165 * @chip: gpio chip to register to gpiolib 1166 * @range: pin range to register to pinctrl core 1167 */ 1168static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, 1169 struct fwnode_handle *fwnode, 1170 struct gpio_chip *chip, 1171 struct pinctrl_gpio_range *range) 1172{ 1173 const char *list_name = "gpio-ranges"; 1174 struct fwnode_reference_args args; 1175 unsigned int gpioport; 1176 u32 pinctrl_base; 1177 int ret; 1178 1179 ret = fwnode_property_get_reference_args(fwnode, list_name, NULL, 3, 0, &args); 1180 if (ret) { 1181 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n", 1182 list_name); 1183 return ret; 1184 } 1185 1186 /* 1187 * Find out on which port this gpio-chip maps to by inspecting the 1188 * second argument of the "gpio-ranges" property. 1189 */ 1190 pinctrl_base = args.args[1]; 1191 gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base); 1192 if (gpioport >= RZA1_NPORTS) { 1193 dev_err(rza1_pctl->dev, 1194 "Invalid values in property %s\n", list_name); 1195 return -EINVAL; 1196 } 1197 1198 *chip = rza1_gpiochip_template; 1199 chip->base = -1; 1200 chip->ngpio = args.args[2]; 1201 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pfwP", fwnode); 1202 if (!chip->label) 1203 return -ENOMEM; 1204 1205 chip->fwnode = fwnode; 1206 chip->parent = rza1_pctl->dev; 1207 1208 range->id = gpioport; 1209 range->name = chip->label; 1210 range->pin_base = range->base = pinctrl_base; 1211 range->npins = args.args[2]; 1212 range->gc = chip; 1213 1214 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip, 1215 &rza1_pctl->ports[gpioport]); 1216 if (ret) 1217 return ret; 1218 1219 pinctrl_add_gpio_range(rza1_pctl->pctl, range); 1220 1221 dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", 1222 chip->label, chip->ngpio); 1223 1224 return 0; 1225} 1226 1227/** 1228 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges 1229 * 1230 * @rza1_pctl: RZ/A1 pin controller device 1231 */ 1232static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl) 1233{ 1234 struct pinctrl_gpio_range *gpio_ranges; 1235 struct gpio_chip *gpio_chips; 1236 struct fwnode_handle *child; 1237 unsigned int ngpiochips; 1238 unsigned int i; 1239 int ret; 1240 1241 ngpiochips = gpiochip_node_count(rza1_pctl->dev); 1242 if (ngpiochips == 0) { 1243 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n"); 1244 return 0; 1245 } 1246 1247 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips, 1248 sizeof(*gpio_chips), GFP_KERNEL); 1249 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips, 1250 sizeof(*gpio_ranges), GFP_KERNEL); 1251 if (!gpio_chips || !gpio_ranges) 1252 return -ENOMEM; 1253 1254 i = 0; 1255 for_each_gpiochip_node(rza1_pctl->dev, child) { 1256 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i], 1257 &gpio_ranges[i]); 1258 if (ret) { 1259 fwnode_handle_put(child); 1260 return ret; 1261 } 1262 1263 ++i; 1264 } 1265 1266 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i); 1267 1268 return 0; 1269} 1270 1271/** 1272 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register 1273 * them to pinctrl and gpio cores. 1274 * 1275 * @rza1_pctl: RZ/A1 pin controller device 1276 */ 1277static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl) 1278{ 1279 struct pinctrl_pin_desc *pins; 1280 struct rza1_port *ports; 1281 unsigned int i; 1282 int ret; 1283 1284 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins), 1285 GFP_KERNEL); 1286 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports), 1287 GFP_KERNEL); 1288 if (!pins || !ports) 1289 return -ENOMEM; 1290 1291 rza1_pctl->pins = pins; 1292 rza1_pctl->desc.pins = pins; 1293 rza1_pctl->desc.npins = RZA1_NPINS; 1294 rza1_pctl->ports = ports; 1295 1296 for (i = 0; i < RZA1_NPINS; ++i) { 1297 unsigned int pin = RZA1_PIN_ID_TO_PIN(i); 1298 unsigned int port = RZA1_PIN_ID_TO_PORT(i); 1299 1300 pins[i].number = i; 1301 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, 1302 "P%u-%u", port, pin); 1303 if (!pins[i].name) 1304 return -ENOMEM; 1305 1306 if (i % RZA1_PINS_PER_PORT == 0) { 1307 /* 1308 * Setup ports; 1309 * they provide per-port lock and logical base address. 1310 */ 1311 unsigned int port_id = RZA1_PIN_ID_TO_PORT(i); 1312 1313 ports[port_id].id = port_id; 1314 ports[port_id].base = rza1_pctl->base; 1315 ports[port_id].pins = &pins[i]; 1316 spin_lock_init(&ports[port_id].lock); 1317 } 1318 } 1319 1320 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc, 1321 rza1_pctl, &rza1_pctl->pctl); 1322 if (ret) { 1323 dev_err(rza1_pctl->dev, 1324 "RZ/A1 pin controller registration failed\n"); 1325 return ret; 1326 } 1327 1328 ret = pinctrl_enable(rza1_pctl->pctl); 1329 if (ret) { 1330 dev_err(rza1_pctl->dev, 1331 "RZ/A1 pin controller failed to start\n"); 1332 return ret; 1333 } 1334 1335 ret = rza1_gpio_register(rza1_pctl); 1336 if (ret) { 1337 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n"); 1338 return ret; 1339 } 1340 1341 return 0; 1342} 1343 1344static int rza1_pinctrl_probe(struct platform_device *pdev) 1345{ 1346 struct rza1_pinctrl *rza1_pctl; 1347 int ret; 1348 1349 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL); 1350 if (!rza1_pctl) 1351 return -ENOMEM; 1352 1353 rza1_pctl->dev = &pdev->dev; 1354 1355 rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0); 1356 if (IS_ERR(rza1_pctl->base)) 1357 return PTR_ERR(rza1_pctl->base); 1358 1359 mutex_init(&rza1_pctl->mutex); 1360 1361 platform_set_drvdata(pdev, rza1_pctl); 1362 1363 rza1_pctl->desc.name = DRIVER_NAME; 1364 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops; 1365 rza1_pctl->desc.pmxops = &rza1_pinmux_ops; 1366 rza1_pctl->desc.owner = THIS_MODULE; 1367 rza1_pctl->data = of_device_get_match_data(&pdev->dev); 1368 1369 ret = rza1_pinctrl_register(rza1_pctl); 1370 if (ret) 1371 return ret; 1372 1373 dev_info(&pdev->dev, 1374 "RZ/A1 pin controller and gpio successfully registered\n"); 1375 1376 return 0; 1377} 1378 1379static const struct of_device_id rza1_pinctrl_of_match[] = { 1380 { 1381 /* RZ/A1H, RZ/A1M */ 1382 .compatible = "renesas,r7s72100-ports", 1383 .data = &rza1h_pmx_conf, 1384 }, 1385 { 1386 /* RZ/A1L */ 1387 .compatible = "renesas,r7s72102-ports", 1388 .data = &rza1l_pmx_conf, 1389 }, 1390 { /* sentinel */ } 1391}; 1392 1393static struct platform_driver rza1_pinctrl_driver = { 1394 .driver = { 1395 .name = DRIVER_NAME, 1396 .of_match_table = rza1_pinctrl_of_match, 1397 }, 1398 .probe = rza1_pinctrl_probe, 1399}; 1400 1401static int __init rza1_pinctrl_init(void) 1402{ 1403 return platform_driver_register(&rza1_pinctrl_driver); 1404} 1405core_initcall(rza1_pinctrl_init); 1406 1407MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org"); 1408MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC"); 1409