1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Bitmain BM1880 SoC Pinctrl driver 4 * 5 * Copyright (c) 2019 Linaro Ltd. 6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7 */ 8 9#include <linux/io.h> 10#include <linux/of.h> 11#include <linux/platform_device.h> 12#include <linux/slab.h> 13 14#include <linux/pinctrl/pinconf-generic.h> 15#include <linux/pinctrl/pinconf.h> 16#include <linux/pinctrl/pinctrl.h> 17#include <linux/pinctrl/pinmux.h> 18 19#include "core.h" 20#include "pinctrl-utils.h" 21 22#define BM1880_REG_MUX 0x20 23 24/** 25 * struct bm1880_pinctrl - driver data 26 * @base: Pinctrl base address 27 * @pctrldev: Pinctrl device 28 * @groups: Pingroups 29 * @ngroups: Number of @groups 30 * @funcs: Pinmux functions 31 * @nfuncs: Number of @funcs 32 * @pinconf: Pinconf data 33 */ 34struct bm1880_pinctrl { 35 void __iomem *base; 36 struct pinctrl_dev *pctrldev; 37 const struct bm1880_pctrl_group *groups; 38 unsigned int ngroups; 39 const struct bm1880_pinmux_function *funcs; 40 unsigned int nfuncs; 41 const struct bm1880_pinconf_data *pinconf; 42}; 43 44/** 45 * struct bm1880_pctrl_group - pinctrl group 46 * @name: Name of the group 47 * @pins: Array of pins belonging to this group 48 * @npins: Number of @pins 49 */ 50struct bm1880_pctrl_group { 51 const char *name; 52 const unsigned int *pins; 53 const unsigned int npins; 54}; 55 56/** 57 * struct bm1880_pinmux_function - a pinmux function 58 * @name: Name of the pinmux function. 59 * @groups: List of pingroups for this function. 60 * @ngroups: Number of entries in @groups. 61 * @mux_val: Selector for this function 62 * @mux: Offset of function specific mux 63 * @mux_shift: Shift for function specific selector 64 */ 65struct bm1880_pinmux_function { 66 const char *name; 67 const char * const *groups; 68 unsigned int ngroups; 69 u32 mux_val; 70 u32 mux; 71 u8 mux_shift; 72}; 73 74/** 75 * struct bm1880_pinconf_data - pinconf data 76 * @drv_bits: Drive strength bit width 77 */ 78struct bm1880_pinconf_data { 79 u32 drv_bits; 80}; 81 82static const struct pinctrl_pin_desc bm1880_pins[] = { 83 PINCTRL_PIN(0, "MIO0"), 84 PINCTRL_PIN(1, "MIO1"), 85 PINCTRL_PIN(2, "MIO2"), 86 PINCTRL_PIN(3, "MIO3"), 87 PINCTRL_PIN(4, "MIO4"), 88 PINCTRL_PIN(5, "MIO5"), 89 PINCTRL_PIN(6, "MIO6"), 90 PINCTRL_PIN(7, "MIO7"), 91 PINCTRL_PIN(8, "MIO8"), 92 PINCTRL_PIN(9, "MIO9"), 93 PINCTRL_PIN(10, "MIO10"), 94 PINCTRL_PIN(11, "MIO11"), 95 PINCTRL_PIN(12, "MIO12"), 96 PINCTRL_PIN(13, "MIO13"), 97 PINCTRL_PIN(14, "MIO14"), 98 PINCTRL_PIN(15, "MIO15"), 99 PINCTRL_PIN(16, "MIO16"), 100 PINCTRL_PIN(17, "MIO17"), 101 PINCTRL_PIN(18, "MIO18"), 102 PINCTRL_PIN(19, "MIO19"), 103 PINCTRL_PIN(20, "MIO20"), 104 PINCTRL_PIN(21, "MIO21"), 105 PINCTRL_PIN(22, "MIO22"), 106 PINCTRL_PIN(23, "MIO23"), 107 PINCTRL_PIN(24, "MIO24"), 108 PINCTRL_PIN(25, "MIO25"), 109 PINCTRL_PIN(26, "MIO26"), 110 PINCTRL_PIN(27, "MIO27"), 111 PINCTRL_PIN(28, "MIO28"), 112 PINCTRL_PIN(29, "MIO29"), 113 PINCTRL_PIN(30, "MIO30"), 114 PINCTRL_PIN(31, "MIO31"), 115 PINCTRL_PIN(32, "MIO32"), 116 PINCTRL_PIN(33, "MIO33"), 117 PINCTRL_PIN(34, "MIO34"), 118 PINCTRL_PIN(35, "MIO35"), 119 PINCTRL_PIN(36, "MIO36"), 120 PINCTRL_PIN(37, "MIO37"), 121 PINCTRL_PIN(38, "MIO38"), 122 PINCTRL_PIN(39, "MIO39"), 123 PINCTRL_PIN(40, "MIO40"), 124 PINCTRL_PIN(41, "MIO41"), 125 PINCTRL_PIN(42, "MIO42"), 126 PINCTRL_PIN(43, "MIO43"), 127 PINCTRL_PIN(44, "MIO44"), 128 PINCTRL_PIN(45, "MIO45"), 129 PINCTRL_PIN(46, "MIO46"), 130 PINCTRL_PIN(47, "MIO47"), 131 PINCTRL_PIN(48, "MIO48"), 132 PINCTRL_PIN(49, "MIO49"), 133 PINCTRL_PIN(50, "MIO50"), 134 PINCTRL_PIN(51, "MIO51"), 135 PINCTRL_PIN(52, "MIO52"), 136 PINCTRL_PIN(53, "MIO53"), 137 PINCTRL_PIN(54, "MIO54"), 138 PINCTRL_PIN(55, "MIO55"), 139 PINCTRL_PIN(56, "MIO56"), 140 PINCTRL_PIN(57, "MIO57"), 141 PINCTRL_PIN(58, "MIO58"), 142 PINCTRL_PIN(59, "MIO59"), 143 PINCTRL_PIN(60, "MIO60"), 144 PINCTRL_PIN(61, "MIO61"), 145 PINCTRL_PIN(62, "MIO62"), 146 PINCTRL_PIN(63, "MIO63"), 147 PINCTRL_PIN(64, "MIO64"), 148 PINCTRL_PIN(65, "MIO65"), 149 PINCTRL_PIN(66, "MIO66"), 150 PINCTRL_PIN(67, "MIO67"), 151 PINCTRL_PIN(68, "MIO68"), 152 PINCTRL_PIN(69, "MIO69"), 153 PINCTRL_PIN(70, "MIO70"), 154 PINCTRL_PIN(71, "MIO71"), 155 PINCTRL_PIN(72, "MIO72"), 156 PINCTRL_PIN(73, "MIO73"), 157 PINCTRL_PIN(74, "MIO74"), 158 PINCTRL_PIN(75, "MIO75"), 159 PINCTRL_PIN(76, "MIO76"), 160 PINCTRL_PIN(77, "MIO77"), 161 PINCTRL_PIN(78, "MIO78"), 162 PINCTRL_PIN(79, "MIO79"), 163 PINCTRL_PIN(80, "MIO80"), 164 PINCTRL_PIN(81, "MIO81"), 165 PINCTRL_PIN(82, "MIO82"), 166 PINCTRL_PIN(83, "MIO83"), 167 PINCTRL_PIN(84, "MIO84"), 168 PINCTRL_PIN(85, "MIO85"), 169 PINCTRL_PIN(86, "MIO86"), 170 PINCTRL_PIN(87, "MIO87"), 171 PINCTRL_PIN(88, "MIO88"), 172 PINCTRL_PIN(89, "MIO89"), 173 PINCTRL_PIN(90, "MIO90"), 174 PINCTRL_PIN(91, "MIO91"), 175 PINCTRL_PIN(92, "MIO92"), 176 PINCTRL_PIN(93, "MIO93"), 177 PINCTRL_PIN(94, "MIO94"), 178 PINCTRL_PIN(95, "MIO95"), 179 PINCTRL_PIN(96, "MIO96"), 180 PINCTRL_PIN(97, "MIO97"), 181 PINCTRL_PIN(98, "MIO98"), 182 PINCTRL_PIN(99, "MIO99"), 183 PINCTRL_PIN(100, "MIO100"), 184 PINCTRL_PIN(101, "MIO101"), 185 PINCTRL_PIN(102, "MIO102"), 186 PINCTRL_PIN(103, "MIO103"), 187 PINCTRL_PIN(104, "MIO104"), 188 PINCTRL_PIN(105, "MIO105"), 189 PINCTRL_PIN(106, "MIO106"), 190 PINCTRL_PIN(107, "MIO107"), 191 PINCTRL_PIN(108, "MIO108"), 192 PINCTRL_PIN(109, "MIO109"), 193 PINCTRL_PIN(110, "MIO110"), 194 PINCTRL_PIN(111, "MIO111"), 195}; 196 197enum bm1880_pinmux_functions { 198 F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2, 199 F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10, 200 F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17, 201 F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24, 202 F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31, 203 F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1, 204 F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4, 205 F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11, 206 F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2, 207 F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10, 208 F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17, 209 F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24, 210 F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31, 211 F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38, 212 F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45, 213 F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52, 214 F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59, 215 F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66, 216 F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0, 217 F_max 218}; 219 220static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 221 10, 11, 12, 13, 14, 15, 16 }; 222static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 }; 223static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 }; 224static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24, 225 25, 26 }; 226static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35, 227 36, 37, 38, 39, 40, 41, 42 }; 228static const unsigned int pwm0_pins[] = { 29 }; 229static const unsigned int pwm1_pins[] = { 30 }; 230static const unsigned int pwm2_pins[] = { 34 }; 231static const unsigned int pwm3_pins[] = { 35 }; 232static const unsigned int pwm4_pins[] = { 43 }; 233static const unsigned int pwm5_pins[] = { 44 }; 234static const unsigned int pwm6_pins[] = { 45 }; 235static const unsigned int pwm7_pins[] = { 46 }; 236static const unsigned int pwm8_pins[] = { 47 }; 237static const unsigned int pwm9_pins[] = { 48 }; 238static const unsigned int pwm10_pins[] = { 49 }; 239static const unsigned int pwm11_pins[] = { 50 }; 240static const unsigned int pwm12_pins[] = { 51 }; 241static const unsigned int pwm13_pins[] = { 52 }; 242static const unsigned int pwm14_pins[] = { 53 }; 243static const unsigned int pwm15_pins[] = { 54 }; 244static const unsigned int pwm16_pins[] = { 55 }; 245static const unsigned int pwm17_pins[] = { 56 }; 246static const unsigned int pwm18_pins[] = { 57 }; 247static const unsigned int pwm19_pins[] = { 58 }; 248static const unsigned int pwm20_pins[] = { 59 }; 249static const unsigned int pwm21_pins[] = { 60 }; 250static const unsigned int pwm22_pins[] = { 61 }; 251static const unsigned int pwm23_pins[] = { 62 }; 252static const unsigned int pwm24_pins[] = { 97 }; 253static const unsigned int pwm25_pins[] = { 98 }; 254static const unsigned int pwm26_pins[] = { 99 }; 255static const unsigned int pwm27_pins[] = { 100 }; 256static const unsigned int pwm28_pins[] = { 101 }; 257static const unsigned int pwm29_pins[] = { 102 }; 258static const unsigned int pwm30_pins[] = { 103 }; 259static const unsigned int pwm31_pins[] = { 104 }; 260static const unsigned int pwm32_pins[] = { 105 }; 261static const unsigned int pwm33_pins[] = { 106 }; 262static const unsigned int pwm34_pins[] = { 107 }; 263static const unsigned int pwm35_pins[] = { 108 }; 264static const unsigned int pwm36_pins[] = { 109 }; 265static const unsigned int pwm37_pins[] = { 110 }; 266static const unsigned int i2c0_pins[] = { 63, 64 }; 267static const unsigned int i2c1_pins[] = { 65, 66 }; 268static const unsigned int i2c2_pins[] = { 67, 68 }; 269static const unsigned int i2c3_pins[] = { 69, 70 }; 270static const unsigned int i2c4_pins[] = { 71, 72 }; 271static const unsigned int uart0_pins[] = { 73, 74 }; 272static const unsigned int uart1_pins[] = { 75, 76 }; 273static const unsigned int uart2_pins[] = { 77, 78 }; 274static const unsigned int uart3_pins[] = { 79, 80 }; 275static const unsigned int uart4_pins[] = { 81, 82 }; 276static const unsigned int uart5_pins[] = { 83, 84 }; 277static const unsigned int uart6_pins[] = { 85, 86 }; 278static const unsigned int uart7_pins[] = { 87, 88 }; 279static const unsigned int uart8_pins[] = { 89, 90 }; 280static const unsigned int uart9_pins[] = { 91, 92 }; 281static const unsigned int uart10_pins[] = { 93, 94 }; 282static const unsigned int uart11_pins[] = { 95, 96 }; 283static const unsigned int uart12_pins[] = { 73, 74, 75, 76 }; 284static const unsigned int uart13_pins[] = { 77, 78, 83, 84 }; 285static const unsigned int uart14_pins[] = { 79, 80, 85, 86 }; 286static const unsigned int uart15_pins[] = { 81, 82, 87, 88 }; 287static const unsigned int gpio0_pins[] = { 97 }; 288static const unsigned int gpio1_pins[] = { 98 }; 289static const unsigned int gpio2_pins[] = { 99 }; 290static const unsigned int gpio3_pins[] = { 100 }; 291static const unsigned int gpio4_pins[] = { 101 }; 292static const unsigned int gpio5_pins[] = { 102 }; 293static const unsigned int gpio6_pins[] = { 103 }; 294static const unsigned int gpio7_pins[] = { 104 }; 295static const unsigned int gpio8_pins[] = { 105 }; 296static const unsigned int gpio9_pins[] = { 106 }; 297static const unsigned int gpio10_pins[] = { 107 }; 298static const unsigned int gpio11_pins[] = { 108 }; 299static const unsigned int gpio12_pins[] = { 109 }; 300static const unsigned int gpio13_pins[] = { 110 }; 301static const unsigned int gpio14_pins[] = { 43 }; 302static const unsigned int gpio15_pins[] = { 44 }; 303static const unsigned int gpio16_pins[] = { 45 }; 304static const unsigned int gpio17_pins[] = { 46 }; 305static const unsigned int gpio18_pins[] = { 47 }; 306static const unsigned int gpio19_pins[] = { 48 }; 307static const unsigned int gpio20_pins[] = { 49 }; 308static const unsigned int gpio21_pins[] = { 50 }; 309static const unsigned int gpio22_pins[] = { 51 }; 310static const unsigned int gpio23_pins[] = { 52 }; 311static const unsigned int gpio24_pins[] = { 53 }; 312static const unsigned int gpio25_pins[] = { 54 }; 313static const unsigned int gpio26_pins[] = { 55 }; 314static const unsigned int gpio27_pins[] = { 56 }; 315static const unsigned int gpio28_pins[] = { 57 }; 316static const unsigned int gpio29_pins[] = { 58 }; 317static const unsigned int gpio30_pins[] = { 59 }; 318static const unsigned int gpio31_pins[] = { 60 }; 319static const unsigned int gpio32_pins[] = { 61 }; 320static const unsigned int gpio33_pins[] = { 62 }; 321static const unsigned int gpio34_pins[] = { 63 }; 322static const unsigned int gpio35_pins[] = { 64 }; 323static const unsigned int gpio36_pins[] = { 65 }; 324static const unsigned int gpio37_pins[] = { 66 }; 325static const unsigned int gpio38_pins[] = { 67 }; 326static const unsigned int gpio39_pins[] = { 68 }; 327static const unsigned int gpio40_pins[] = { 69 }; 328static const unsigned int gpio41_pins[] = { 70 }; 329static const unsigned int gpio42_pins[] = { 71 }; 330static const unsigned int gpio43_pins[] = { 72 }; 331static const unsigned int gpio44_pins[] = { 73 }; 332static const unsigned int gpio45_pins[] = { 74 }; 333static const unsigned int gpio46_pins[] = { 75 }; 334static const unsigned int gpio47_pins[] = { 76 }; 335static const unsigned int gpio48_pins[] = { 77 }; 336static const unsigned int gpio49_pins[] = { 78 }; 337static const unsigned int gpio50_pins[] = { 79 }; 338static const unsigned int gpio51_pins[] = { 80 }; 339static const unsigned int gpio52_pins[] = { 81 }; 340static const unsigned int gpio53_pins[] = { 82 }; 341static const unsigned int gpio54_pins[] = { 83 }; 342static const unsigned int gpio55_pins[] = { 84 }; 343static const unsigned int gpio56_pins[] = { 85 }; 344static const unsigned int gpio57_pins[] = { 86 }; 345static const unsigned int gpio58_pins[] = { 87 }; 346static const unsigned int gpio59_pins[] = { 88 }; 347static const unsigned int gpio60_pins[] = { 89 }; 348static const unsigned int gpio61_pins[] = { 90 }; 349static const unsigned int gpio62_pins[] = { 91 }; 350static const unsigned int gpio63_pins[] = { 92 }; 351static const unsigned int gpio64_pins[] = { 93 }; 352static const unsigned int gpio65_pins[] = { 94 }; 353static const unsigned int gpio66_pins[] = { 95 }; 354static const unsigned int gpio67_pins[] = { 96 }; 355static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51, 356 52, 53, 54, 55, 56, 57, 58 }; 357static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 }; 358static const unsigned int i2s0_mclkin_pins[] = { 97 }; 359static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 }; 360static const unsigned int i2s1_mclkin_pins[] = { 98 }; 361static const unsigned int spi0_pins[] = { 59, 60, 61, 62 }; 362 363#define BM1880_PINCTRL_GRP(nm) \ 364 { \ 365 .name = #nm "_grp", \ 366 .pins = nm ## _pins, \ 367 .npins = ARRAY_SIZE(nm ## _pins), \ 368 } 369 370static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = { 371 BM1880_PINCTRL_GRP(nand), 372 BM1880_PINCTRL_GRP(spi), 373 BM1880_PINCTRL_GRP(emmc), 374 BM1880_PINCTRL_GRP(sdio), 375 BM1880_PINCTRL_GRP(eth0), 376 BM1880_PINCTRL_GRP(pwm0), 377 BM1880_PINCTRL_GRP(pwm1), 378 BM1880_PINCTRL_GRP(pwm2), 379 BM1880_PINCTRL_GRP(pwm3), 380 BM1880_PINCTRL_GRP(pwm4), 381 BM1880_PINCTRL_GRP(pwm5), 382 BM1880_PINCTRL_GRP(pwm6), 383 BM1880_PINCTRL_GRP(pwm7), 384 BM1880_PINCTRL_GRP(pwm8), 385 BM1880_PINCTRL_GRP(pwm9), 386 BM1880_PINCTRL_GRP(pwm10), 387 BM1880_PINCTRL_GRP(pwm11), 388 BM1880_PINCTRL_GRP(pwm12), 389 BM1880_PINCTRL_GRP(pwm13), 390 BM1880_PINCTRL_GRP(pwm14), 391 BM1880_PINCTRL_GRP(pwm15), 392 BM1880_PINCTRL_GRP(pwm16), 393 BM1880_PINCTRL_GRP(pwm17), 394 BM1880_PINCTRL_GRP(pwm18), 395 BM1880_PINCTRL_GRP(pwm19), 396 BM1880_PINCTRL_GRP(pwm20), 397 BM1880_PINCTRL_GRP(pwm21), 398 BM1880_PINCTRL_GRP(pwm22), 399 BM1880_PINCTRL_GRP(pwm23), 400 BM1880_PINCTRL_GRP(pwm24), 401 BM1880_PINCTRL_GRP(pwm25), 402 BM1880_PINCTRL_GRP(pwm26), 403 BM1880_PINCTRL_GRP(pwm27), 404 BM1880_PINCTRL_GRP(pwm28), 405 BM1880_PINCTRL_GRP(pwm29), 406 BM1880_PINCTRL_GRP(pwm30), 407 BM1880_PINCTRL_GRP(pwm31), 408 BM1880_PINCTRL_GRP(pwm32), 409 BM1880_PINCTRL_GRP(pwm33), 410 BM1880_PINCTRL_GRP(pwm34), 411 BM1880_PINCTRL_GRP(pwm35), 412 BM1880_PINCTRL_GRP(pwm36), 413 BM1880_PINCTRL_GRP(pwm37), 414 BM1880_PINCTRL_GRP(i2c0), 415 BM1880_PINCTRL_GRP(i2c1), 416 BM1880_PINCTRL_GRP(i2c2), 417 BM1880_PINCTRL_GRP(i2c3), 418 BM1880_PINCTRL_GRP(i2c4), 419 BM1880_PINCTRL_GRP(uart0), 420 BM1880_PINCTRL_GRP(uart1), 421 BM1880_PINCTRL_GRP(uart2), 422 BM1880_PINCTRL_GRP(uart3), 423 BM1880_PINCTRL_GRP(uart4), 424 BM1880_PINCTRL_GRP(uart5), 425 BM1880_PINCTRL_GRP(uart6), 426 BM1880_PINCTRL_GRP(uart7), 427 BM1880_PINCTRL_GRP(uart8), 428 BM1880_PINCTRL_GRP(uart9), 429 BM1880_PINCTRL_GRP(uart10), 430 BM1880_PINCTRL_GRP(uart11), 431 BM1880_PINCTRL_GRP(uart12), 432 BM1880_PINCTRL_GRP(uart13), 433 BM1880_PINCTRL_GRP(uart14), 434 BM1880_PINCTRL_GRP(uart15), 435 BM1880_PINCTRL_GRP(gpio0), 436 BM1880_PINCTRL_GRP(gpio1), 437 BM1880_PINCTRL_GRP(gpio2), 438 BM1880_PINCTRL_GRP(gpio3), 439 BM1880_PINCTRL_GRP(gpio4), 440 BM1880_PINCTRL_GRP(gpio5), 441 BM1880_PINCTRL_GRP(gpio6), 442 BM1880_PINCTRL_GRP(gpio7), 443 BM1880_PINCTRL_GRP(gpio8), 444 BM1880_PINCTRL_GRP(gpio9), 445 BM1880_PINCTRL_GRP(gpio10), 446 BM1880_PINCTRL_GRP(gpio11), 447 BM1880_PINCTRL_GRP(gpio12), 448 BM1880_PINCTRL_GRP(gpio13), 449 BM1880_PINCTRL_GRP(gpio14), 450 BM1880_PINCTRL_GRP(gpio15), 451 BM1880_PINCTRL_GRP(gpio16), 452 BM1880_PINCTRL_GRP(gpio17), 453 BM1880_PINCTRL_GRP(gpio18), 454 BM1880_PINCTRL_GRP(gpio19), 455 BM1880_PINCTRL_GRP(gpio20), 456 BM1880_PINCTRL_GRP(gpio21), 457 BM1880_PINCTRL_GRP(gpio22), 458 BM1880_PINCTRL_GRP(gpio23), 459 BM1880_PINCTRL_GRP(gpio24), 460 BM1880_PINCTRL_GRP(gpio25), 461 BM1880_PINCTRL_GRP(gpio26), 462 BM1880_PINCTRL_GRP(gpio27), 463 BM1880_PINCTRL_GRP(gpio28), 464 BM1880_PINCTRL_GRP(gpio29), 465 BM1880_PINCTRL_GRP(gpio30), 466 BM1880_PINCTRL_GRP(gpio31), 467 BM1880_PINCTRL_GRP(gpio32), 468 BM1880_PINCTRL_GRP(gpio33), 469 BM1880_PINCTRL_GRP(gpio34), 470 BM1880_PINCTRL_GRP(gpio35), 471 BM1880_PINCTRL_GRP(gpio36), 472 BM1880_PINCTRL_GRP(gpio37), 473 BM1880_PINCTRL_GRP(gpio38), 474 BM1880_PINCTRL_GRP(gpio39), 475 BM1880_PINCTRL_GRP(gpio40), 476 BM1880_PINCTRL_GRP(gpio41), 477 BM1880_PINCTRL_GRP(gpio42), 478 BM1880_PINCTRL_GRP(gpio43), 479 BM1880_PINCTRL_GRP(gpio44), 480 BM1880_PINCTRL_GRP(gpio45), 481 BM1880_PINCTRL_GRP(gpio46), 482 BM1880_PINCTRL_GRP(gpio47), 483 BM1880_PINCTRL_GRP(gpio48), 484 BM1880_PINCTRL_GRP(gpio49), 485 BM1880_PINCTRL_GRP(gpio50), 486 BM1880_PINCTRL_GRP(gpio51), 487 BM1880_PINCTRL_GRP(gpio52), 488 BM1880_PINCTRL_GRP(gpio53), 489 BM1880_PINCTRL_GRP(gpio54), 490 BM1880_PINCTRL_GRP(gpio55), 491 BM1880_PINCTRL_GRP(gpio56), 492 BM1880_PINCTRL_GRP(gpio57), 493 BM1880_PINCTRL_GRP(gpio58), 494 BM1880_PINCTRL_GRP(gpio59), 495 BM1880_PINCTRL_GRP(gpio60), 496 BM1880_PINCTRL_GRP(gpio61), 497 BM1880_PINCTRL_GRP(gpio62), 498 BM1880_PINCTRL_GRP(gpio63), 499 BM1880_PINCTRL_GRP(gpio64), 500 BM1880_PINCTRL_GRP(gpio65), 501 BM1880_PINCTRL_GRP(gpio66), 502 BM1880_PINCTRL_GRP(gpio67), 503 BM1880_PINCTRL_GRP(eth1), 504 BM1880_PINCTRL_GRP(i2s0), 505 BM1880_PINCTRL_GRP(i2s0_mclkin), 506 BM1880_PINCTRL_GRP(i2s1), 507 BM1880_PINCTRL_GRP(i2s1_mclkin), 508 BM1880_PINCTRL_GRP(spi0), 509}; 510 511static const char * const nand_group[] = { "nand_grp" }; 512static const char * const spi_group[] = { "spi_grp" }; 513static const char * const emmc_group[] = { "emmc_grp" }; 514static const char * const sdio_group[] = { "sdio_grp" }; 515static const char * const eth0_group[] = { "eth0_grp" }; 516static const char * const pwm0_group[] = { "pwm0_grp" }; 517static const char * const pwm1_group[] = { "pwm1_grp" }; 518static const char * const pwm2_group[] = { "pwm2_grp" }; 519static const char * const pwm3_group[] = { "pwm3_grp" }; 520static const char * const pwm4_group[] = { "pwm4_grp" }; 521static const char * const pwm5_group[] = { "pwm5_grp" }; 522static const char * const pwm6_group[] = { "pwm6_grp" }; 523static const char * const pwm7_group[] = { "pwm7_grp" }; 524static const char * const pwm8_group[] = { "pwm8_grp" }; 525static const char * const pwm9_group[] = { "pwm9_grp" }; 526static const char * const pwm10_group[] = { "pwm10_grp" }; 527static const char * const pwm11_group[] = { "pwm11_grp" }; 528static const char * const pwm12_group[] = { "pwm12_grp" }; 529static const char * const pwm13_group[] = { "pwm13_grp" }; 530static const char * const pwm14_group[] = { "pwm14_grp" }; 531static const char * const pwm15_group[] = { "pwm15_grp" }; 532static const char * const pwm16_group[] = { "pwm16_grp" }; 533static const char * const pwm17_group[] = { "pwm17_grp" }; 534static const char * const pwm18_group[] = { "pwm18_grp" }; 535static const char * const pwm19_group[] = { "pwm19_grp" }; 536static const char * const pwm20_group[] = { "pwm20_grp" }; 537static const char * const pwm21_group[] = { "pwm21_grp" }; 538static const char * const pwm22_group[] = { "pwm22_grp" }; 539static const char * const pwm23_group[] = { "pwm23_grp" }; 540static const char * const pwm24_group[] = { "pwm24_grp" }; 541static const char * const pwm25_group[] = { "pwm25_grp" }; 542static const char * const pwm26_group[] = { "pwm26_grp" }; 543static const char * const pwm27_group[] = { "pwm27_grp" }; 544static const char * const pwm28_group[] = { "pwm28_grp" }; 545static const char * const pwm29_group[] = { "pwm29_grp" }; 546static const char * const pwm30_group[] = { "pwm30_grp" }; 547static const char * const pwm31_group[] = { "pwm31_grp" }; 548static const char * const pwm32_group[] = { "pwm32_grp" }; 549static const char * const pwm33_group[] = { "pwm33_grp" }; 550static const char * const pwm34_group[] = { "pwm34_grp" }; 551static const char * const pwm35_group[] = { "pwm35_grp" }; 552static const char * const pwm36_group[] = { "pwm36_grp" }; 553static const char * const pwm37_group[] = { "pwm37_grp" }; 554static const char * const i2c0_group[] = { "i2c0_grp" }; 555static const char * const i2c1_group[] = { "i2c1_grp" }; 556static const char * const i2c2_group[] = { "i2c2_grp" }; 557static const char * const i2c3_group[] = { "i2c3_grp" }; 558static const char * const i2c4_group[] = { "i2c4_grp" }; 559static const char * const uart0_group[] = { "uart0_grp" }; 560static const char * const uart1_group[] = { "uart1_grp" }; 561static const char * const uart2_group[] = { "uart2_grp" }; 562static const char * const uart3_group[] = { "uart3_grp" }; 563static const char * const uart4_group[] = { "uart4_grp" }; 564static const char * const uart5_group[] = { "uart5_grp" }; 565static const char * const uart6_group[] = { "uart6_grp" }; 566static const char * const uart7_group[] = { "uart7_grp" }; 567static const char * const uart8_group[] = { "uart8_grp" }; 568static const char * const uart9_group[] = { "uart9_grp" }; 569static const char * const uart10_group[] = { "uart10_grp" }; 570static const char * const uart11_group[] = { "uart11_grp" }; 571static const char * const uart12_group[] = { "uart12_grp" }; 572static const char * const uart13_group[] = { "uart13_grp" }; 573static const char * const uart14_group[] = { "uart14_grp" }; 574static const char * const uart15_group[] = { "uart15_grp" }; 575static const char * const gpio0_group[] = { "gpio0_grp" }; 576static const char * const gpio1_group[] = { "gpio1_grp" }; 577static const char * const gpio2_group[] = { "gpio2_grp" }; 578static const char * const gpio3_group[] = { "gpio3_grp" }; 579static const char * const gpio4_group[] = { "gpio4_grp" }; 580static const char * const gpio5_group[] = { "gpio5_grp" }; 581static const char * const gpio6_group[] = { "gpio6_grp" }; 582static const char * const gpio7_group[] = { "gpio7_grp" }; 583static const char * const gpio8_group[] = { "gpio8_grp" }; 584static const char * const gpio9_group[] = { "gpio9_grp" }; 585static const char * const gpio10_group[] = { "gpio10_grp" }; 586static const char * const gpio11_group[] = { "gpio11_grp" }; 587static const char * const gpio12_group[] = { "gpio12_grp" }; 588static const char * const gpio13_group[] = { "gpio13_grp" }; 589static const char * const gpio14_group[] = { "gpio14_grp" }; 590static const char * const gpio15_group[] = { "gpio15_grp" }; 591static const char * const gpio16_group[] = { "gpio16_grp" }; 592static const char * const gpio17_group[] = { "gpio17_grp" }; 593static const char * const gpio18_group[] = { "gpio18_grp" }; 594static const char * const gpio19_group[] = { "gpio19_grp" }; 595static const char * const gpio20_group[] = { "gpio20_grp" }; 596static const char * const gpio21_group[] = { "gpio21_grp" }; 597static const char * const gpio22_group[] = { "gpio22_grp" }; 598static const char * const gpio23_group[] = { "gpio23_grp" }; 599static const char * const gpio24_group[] = { "gpio24_grp" }; 600static const char * const gpio25_group[] = { "gpio25_grp" }; 601static const char * const gpio26_group[] = { "gpio26_grp" }; 602static const char * const gpio27_group[] = { "gpio27_grp" }; 603static const char * const gpio28_group[] = { "gpio28_grp" }; 604static const char * const gpio29_group[] = { "gpio29_grp" }; 605static const char * const gpio30_group[] = { "gpio30_grp" }; 606static const char * const gpio31_group[] = { "gpio31_grp" }; 607static const char * const gpio32_group[] = { "gpio32_grp" }; 608static const char * const gpio33_group[] = { "gpio33_grp" }; 609static const char * const gpio34_group[] = { "gpio34_grp" }; 610static const char * const gpio35_group[] = { "gpio35_grp" }; 611static const char * const gpio36_group[] = { "gpio36_grp" }; 612static const char * const gpio37_group[] = { "gpio37_grp" }; 613static const char * const gpio38_group[] = { "gpio38_grp" }; 614static const char * const gpio39_group[] = { "gpio39_grp" }; 615static const char * const gpio40_group[] = { "gpio40_grp" }; 616static const char * const gpio41_group[] = { "gpio41_grp" }; 617static const char * const gpio42_group[] = { "gpio42_grp" }; 618static const char * const gpio43_group[] = { "gpio43_grp" }; 619static const char * const gpio44_group[] = { "gpio44_grp" }; 620static const char * const gpio45_group[] = { "gpio45_grp" }; 621static const char * const gpio46_group[] = { "gpio46_grp" }; 622static const char * const gpio47_group[] = { "gpio47_grp" }; 623static const char * const gpio48_group[] = { "gpio48_grp" }; 624static const char * const gpio49_group[] = { "gpio49_grp" }; 625static const char * const gpio50_group[] = { "gpio50_grp" }; 626static const char * const gpio51_group[] = { "gpio51_grp" }; 627static const char * const gpio52_group[] = { "gpio52_grp" }; 628static const char * const gpio53_group[] = { "gpio53_grp" }; 629static const char * const gpio54_group[] = { "gpio54_grp" }; 630static const char * const gpio55_group[] = { "gpio55_grp" }; 631static const char * const gpio56_group[] = { "gpio56_grp" }; 632static const char * const gpio57_group[] = { "gpio57_grp" }; 633static const char * const gpio58_group[] = { "gpio58_grp" }; 634static const char * const gpio59_group[] = { "gpio59_grp" }; 635static const char * const gpio60_group[] = { "gpio60_grp" }; 636static const char * const gpio61_group[] = { "gpio61_grp" }; 637static const char * const gpio62_group[] = { "gpio62_grp" }; 638static const char * const gpio63_group[] = { "gpio63_grp" }; 639static const char * const gpio64_group[] = { "gpio64_grp" }; 640static const char * const gpio65_group[] = { "gpio65_grp" }; 641static const char * const gpio66_group[] = { "gpio66_grp" }; 642static const char * const gpio67_group[] = { "gpio67_grp" }; 643static const char * const eth1_group[] = { "eth1_grp" }; 644static const char * const i2s0_group[] = { "i2s0_grp" }; 645static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" }; 646static const char * const i2s1_group[] = { "i2s1_grp" }; 647static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" }; 648static const char * const spi0_group[] = { "spi0_grp" }; 649 650#define BM1880_PINMUX_FUNCTION(fname, mval) \ 651 [F_##fname] = { \ 652 .name = #fname, \ 653 .groups = fname##_group, \ 654 .ngroups = ARRAY_SIZE(fname##_group), \ 655 .mux_val = mval, \ 656 } 657 658static const struct bm1880_pinmux_function bm1880_pmux_functions[] = { 659 BM1880_PINMUX_FUNCTION(nand, 2), 660 BM1880_PINMUX_FUNCTION(spi, 0), 661 BM1880_PINMUX_FUNCTION(emmc, 1), 662 BM1880_PINMUX_FUNCTION(sdio, 0), 663 BM1880_PINMUX_FUNCTION(eth0, 0), 664 BM1880_PINMUX_FUNCTION(pwm0, 2), 665 BM1880_PINMUX_FUNCTION(pwm1, 2), 666 BM1880_PINMUX_FUNCTION(pwm2, 2), 667 BM1880_PINMUX_FUNCTION(pwm3, 2), 668 BM1880_PINMUX_FUNCTION(pwm4, 2), 669 BM1880_PINMUX_FUNCTION(pwm5, 2), 670 BM1880_PINMUX_FUNCTION(pwm6, 2), 671 BM1880_PINMUX_FUNCTION(pwm7, 2), 672 BM1880_PINMUX_FUNCTION(pwm8, 2), 673 BM1880_PINMUX_FUNCTION(pwm9, 2), 674 BM1880_PINMUX_FUNCTION(pwm10, 2), 675 BM1880_PINMUX_FUNCTION(pwm11, 2), 676 BM1880_PINMUX_FUNCTION(pwm12, 2), 677 BM1880_PINMUX_FUNCTION(pwm13, 2), 678 BM1880_PINMUX_FUNCTION(pwm14, 2), 679 BM1880_PINMUX_FUNCTION(pwm15, 2), 680 BM1880_PINMUX_FUNCTION(pwm16, 2), 681 BM1880_PINMUX_FUNCTION(pwm17, 2), 682 BM1880_PINMUX_FUNCTION(pwm18, 2), 683 BM1880_PINMUX_FUNCTION(pwm19, 2), 684 BM1880_PINMUX_FUNCTION(pwm20, 2), 685 BM1880_PINMUX_FUNCTION(pwm21, 2), 686 BM1880_PINMUX_FUNCTION(pwm22, 2), 687 BM1880_PINMUX_FUNCTION(pwm23, 2), 688 BM1880_PINMUX_FUNCTION(pwm24, 2), 689 BM1880_PINMUX_FUNCTION(pwm25, 2), 690 BM1880_PINMUX_FUNCTION(pwm26, 2), 691 BM1880_PINMUX_FUNCTION(pwm27, 2), 692 BM1880_PINMUX_FUNCTION(pwm28, 2), 693 BM1880_PINMUX_FUNCTION(pwm29, 2), 694 BM1880_PINMUX_FUNCTION(pwm30, 2), 695 BM1880_PINMUX_FUNCTION(pwm31, 2), 696 BM1880_PINMUX_FUNCTION(pwm32, 2), 697 BM1880_PINMUX_FUNCTION(pwm33, 2), 698 BM1880_PINMUX_FUNCTION(pwm34, 2), 699 BM1880_PINMUX_FUNCTION(pwm35, 2), 700 BM1880_PINMUX_FUNCTION(pwm36, 2), 701 BM1880_PINMUX_FUNCTION(pwm37, 2), 702 BM1880_PINMUX_FUNCTION(i2c0, 1), 703 BM1880_PINMUX_FUNCTION(i2c1, 1), 704 BM1880_PINMUX_FUNCTION(i2c2, 1), 705 BM1880_PINMUX_FUNCTION(i2c3, 1), 706 BM1880_PINMUX_FUNCTION(i2c4, 1), 707 BM1880_PINMUX_FUNCTION(uart0, 3), 708 BM1880_PINMUX_FUNCTION(uart1, 3), 709 BM1880_PINMUX_FUNCTION(uart2, 3), 710 BM1880_PINMUX_FUNCTION(uart3, 3), 711 BM1880_PINMUX_FUNCTION(uart4, 1), 712 BM1880_PINMUX_FUNCTION(uart5, 1), 713 BM1880_PINMUX_FUNCTION(uart6, 1), 714 BM1880_PINMUX_FUNCTION(uart7, 1), 715 BM1880_PINMUX_FUNCTION(uart8, 1), 716 BM1880_PINMUX_FUNCTION(uart9, 1), 717 BM1880_PINMUX_FUNCTION(uart10, 1), 718 BM1880_PINMUX_FUNCTION(uart11, 1), 719 BM1880_PINMUX_FUNCTION(uart12, 3), 720 BM1880_PINMUX_FUNCTION(uart13, 3), 721 BM1880_PINMUX_FUNCTION(uart14, 3), 722 BM1880_PINMUX_FUNCTION(uart15, 3), 723 BM1880_PINMUX_FUNCTION(gpio0, 0), 724 BM1880_PINMUX_FUNCTION(gpio1, 0), 725 BM1880_PINMUX_FUNCTION(gpio2, 0), 726 BM1880_PINMUX_FUNCTION(gpio3, 0), 727 BM1880_PINMUX_FUNCTION(gpio4, 0), 728 BM1880_PINMUX_FUNCTION(gpio5, 0), 729 BM1880_PINMUX_FUNCTION(gpio6, 0), 730 BM1880_PINMUX_FUNCTION(gpio7, 0), 731 BM1880_PINMUX_FUNCTION(gpio8, 0), 732 BM1880_PINMUX_FUNCTION(gpio9, 0), 733 BM1880_PINMUX_FUNCTION(gpio10, 0), 734 BM1880_PINMUX_FUNCTION(gpio11, 0), 735 BM1880_PINMUX_FUNCTION(gpio12, 1), 736 BM1880_PINMUX_FUNCTION(gpio13, 1), 737 BM1880_PINMUX_FUNCTION(gpio14, 0), 738 BM1880_PINMUX_FUNCTION(gpio15, 0), 739 BM1880_PINMUX_FUNCTION(gpio16, 0), 740 BM1880_PINMUX_FUNCTION(gpio17, 0), 741 BM1880_PINMUX_FUNCTION(gpio18, 0), 742 BM1880_PINMUX_FUNCTION(gpio19, 0), 743 BM1880_PINMUX_FUNCTION(gpio20, 0), 744 BM1880_PINMUX_FUNCTION(gpio21, 0), 745 BM1880_PINMUX_FUNCTION(gpio22, 0), 746 BM1880_PINMUX_FUNCTION(gpio23, 0), 747 BM1880_PINMUX_FUNCTION(gpio24, 0), 748 BM1880_PINMUX_FUNCTION(gpio25, 0), 749 BM1880_PINMUX_FUNCTION(gpio26, 0), 750 BM1880_PINMUX_FUNCTION(gpio27, 0), 751 BM1880_PINMUX_FUNCTION(gpio28, 0), 752 BM1880_PINMUX_FUNCTION(gpio29, 0), 753 BM1880_PINMUX_FUNCTION(gpio30, 0), 754 BM1880_PINMUX_FUNCTION(gpio31, 0), 755 BM1880_PINMUX_FUNCTION(gpio32, 0), 756 BM1880_PINMUX_FUNCTION(gpio33, 0), 757 BM1880_PINMUX_FUNCTION(gpio34, 0), 758 BM1880_PINMUX_FUNCTION(gpio35, 0), 759 BM1880_PINMUX_FUNCTION(gpio36, 0), 760 BM1880_PINMUX_FUNCTION(gpio37, 0), 761 BM1880_PINMUX_FUNCTION(gpio38, 0), 762 BM1880_PINMUX_FUNCTION(gpio39, 0), 763 BM1880_PINMUX_FUNCTION(gpio40, 0), 764 BM1880_PINMUX_FUNCTION(gpio41, 0), 765 BM1880_PINMUX_FUNCTION(gpio42, 0), 766 BM1880_PINMUX_FUNCTION(gpio43, 0), 767 BM1880_PINMUX_FUNCTION(gpio44, 0), 768 BM1880_PINMUX_FUNCTION(gpio45, 0), 769 BM1880_PINMUX_FUNCTION(gpio46, 0), 770 BM1880_PINMUX_FUNCTION(gpio47, 0), 771 BM1880_PINMUX_FUNCTION(gpio48, 0), 772 BM1880_PINMUX_FUNCTION(gpio49, 0), 773 BM1880_PINMUX_FUNCTION(gpio50, 0), 774 BM1880_PINMUX_FUNCTION(gpio51, 0), 775 BM1880_PINMUX_FUNCTION(gpio52, 0), 776 BM1880_PINMUX_FUNCTION(gpio53, 0), 777 BM1880_PINMUX_FUNCTION(gpio54, 0), 778 BM1880_PINMUX_FUNCTION(gpio55, 0), 779 BM1880_PINMUX_FUNCTION(gpio56, 0), 780 BM1880_PINMUX_FUNCTION(gpio57, 0), 781 BM1880_PINMUX_FUNCTION(gpio58, 0), 782 BM1880_PINMUX_FUNCTION(gpio59, 0), 783 BM1880_PINMUX_FUNCTION(gpio60, 0), 784 BM1880_PINMUX_FUNCTION(gpio61, 0), 785 BM1880_PINMUX_FUNCTION(gpio62, 0), 786 BM1880_PINMUX_FUNCTION(gpio63, 0), 787 BM1880_PINMUX_FUNCTION(gpio64, 0), 788 BM1880_PINMUX_FUNCTION(gpio65, 0), 789 BM1880_PINMUX_FUNCTION(gpio66, 0), 790 BM1880_PINMUX_FUNCTION(gpio67, 0), 791 BM1880_PINMUX_FUNCTION(eth1, 1), 792 BM1880_PINMUX_FUNCTION(i2s0, 2), 793 BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1), 794 BM1880_PINMUX_FUNCTION(i2s1, 2), 795 BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1), 796 BM1880_PINMUX_FUNCTION(spi0, 1), 797}; 798 799#define BM1880_PINCONF_DAT(_width) \ 800 { \ 801 .drv_bits = _width, \ 802 } 803 804static const struct bm1880_pinconf_data bm1880_pinconf[] = { 805 BM1880_PINCONF_DAT(0x03), 806 BM1880_PINCONF_DAT(0x03), 807 BM1880_PINCONF_DAT(0x03), 808 BM1880_PINCONF_DAT(0x03), 809 BM1880_PINCONF_DAT(0x03), 810 BM1880_PINCONF_DAT(0x03), 811 BM1880_PINCONF_DAT(0x03), 812 BM1880_PINCONF_DAT(0x03), 813 BM1880_PINCONF_DAT(0x03), 814 BM1880_PINCONF_DAT(0x03), 815 BM1880_PINCONF_DAT(0x03), 816 BM1880_PINCONF_DAT(0x03), 817 BM1880_PINCONF_DAT(0x03), 818 BM1880_PINCONF_DAT(0x03), 819 BM1880_PINCONF_DAT(0x03), 820 BM1880_PINCONF_DAT(0x03), 821 BM1880_PINCONF_DAT(0x03), 822 BM1880_PINCONF_DAT(0x03), 823 BM1880_PINCONF_DAT(0x03), 824 BM1880_PINCONF_DAT(0x03), 825 BM1880_PINCONF_DAT(0x03), 826 BM1880_PINCONF_DAT(0x03), 827 BM1880_PINCONF_DAT(0x03), 828 BM1880_PINCONF_DAT(0x03), 829 BM1880_PINCONF_DAT(0x03), 830 BM1880_PINCONF_DAT(0x03), 831 BM1880_PINCONF_DAT(0x03), 832 BM1880_PINCONF_DAT(0x03), 833 BM1880_PINCONF_DAT(0x03), 834 BM1880_PINCONF_DAT(0x03), 835 BM1880_PINCONF_DAT(0x03), 836 BM1880_PINCONF_DAT(0x03), 837 BM1880_PINCONF_DAT(0x03), 838 BM1880_PINCONF_DAT(0x03), 839 BM1880_PINCONF_DAT(0x03), 840 BM1880_PINCONF_DAT(0x03), 841 BM1880_PINCONF_DAT(0x03), 842 BM1880_PINCONF_DAT(0x03), 843 BM1880_PINCONF_DAT(0x03), 844 BM1880_PINCONF_DAT(0x03), 845 BM1880_PINCONF_DAT(0x03), 846 BM1880_PINCONF_DAT(0x03), 847 BM1880_PINCONF_DAT(0x03), 848 BM1880_PINCONF_DAT(0x03), 849 BM1880_PINCONF_DAT(0x03), 850 BM1880_PINCONF_DAT(0x03), 851 BM1880_PINCONF_DAT(0x03), 852 BM1880_PINCONF_DAT(0x03), 853 BM1880_PINCONF_DAT(0x03), 854 BM1880_PINCONF_DAT(0x03), 855 BM1880_PINCONF_DAT(0x03), 856 BM1880_PINCONF_DAT(0x03), 857 BM1880_PINCONF_DAT(0x03), 858 BM1880_PINCONF_DAT(0x03), 859 BM1880_PINCONF_DAT(0x03), 860 BM1880_PINCONF_DAT(0x03), 861 BM1880_PINCONF_DAT(0x03), 862 BM1880_PINCONF_DAT(0x03), 863 BM1880_PINCONF_DAT(0x03), 864 BM1880_PINCONF_DAT(0x03), 865 BM1880_PINCONF_DAT(0x02), 866 BM1880_PINCONF_DAT(0x02), 867 BM1880_PINCONF_DAT(0x02), 868 BM1880_PINCONF_DAT(0x02), 869 BM1880_PINCONF_DAT(0x02), 870 BM1880_PINCONF_DAT(0x02), 871 BM1880_PINCONF_DAT(0x02), 872 BM1880_PINCONF_DAT(0x02), 873 BM1880_PINCONF_DAT(0x02), 874 BM1880_PINCONF_DAT(0x02), 875 BM1880_PINCONF_DAT(0x02), 876 BM1880_PINCONF_DAT(0x02), 877 BM1880_PINCONF_DAT(0x02), 878 BM1880_PINCONF_DAT(0x02), 879 BM1880_PINCONF_DAT(0x02), 880 BM1880_PINCONF_DAT(0x02), 881 BM1880_PINCONF_DAT(0x02), 882 BM1880_PINCONF_DAT(0x02), 883 BM1880_PINCONF_DAT(0x02), 884 BM1880_PINCONF_DAT(0x02), 885 BM1880_PINCONF_DAT(0x02), 886 BM1880_PINCONF_DAT(0x02), 887 BM1880_PINCONF_DAT(0x02), 888 BM1880_PINCONF_DAT(0x02), 889 BM1880_PINCONF_DAT(0x02), 890 BM1880_PINCONF_DAT(0x02), 891 BM1880_PINCONF_DAT(0x02), 892 BM1880_PINCONF_DAT(0x02), 893 BM1880_PINCONF_DAT(0x02), 894 BM1880_PINCONF_DAT(0x02), 895 BM1880_PINCONF_DAT(0x02), 896 BM1880_PINCONF_DAT(0x02), 897 BM1880_PINCONF_DAT(0x02), 898 BM1880_PINCONF_DAT(0x02), 899 BM1880_PINCONF_DAT(0x02), 900 BM1880_PINCONF_DAT(0x02), 901 BM1880_PINCONF_DAT(0x02), 902 BM1880_PINCONF_DAT(0x02), 903 BM1880_PINCONF_DAT(0x02), 904 BM1880_PINCONF_DAT(0x02), 905 BM1880_PINCONF_DAT(0x02), 906 BM1880_PINCONF_DAT(0x02), 907 BM1880_PINCONF_DAT(0x02), 908 BM1880_PINCONF_DAT(0x02), 909 BM1880_PINCONF_DAT(0x02), 910 BM1880_PINCONF_DAT(0x02), 911 BM1880_PINCONF_DAT(0x02), 912 BM1880_PINCONF_DAT(0x02), 913 BM1880_PINCONF_DAT(0x02), 914 BM1880_PINCONF_DAT(0x02), 915 BM1880_PINCONF_DAT(0x02), 916 BM1880_PINCONF_DAT(0x02), 917}; 918 919static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 920{ 921 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 922 923 return pctrl->ngroups; 924} 925 926static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev, 927 unsigned int selector) 928{ 929 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 930 931 return pctrl->groups[selector].name; 932} 933 934static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 935 unsigned int selector, 936 const unsigned int **pins, 937 unsigned int *num_pins) 938{ 939 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 940 941 *pins = pctrl->groups[selector].pins; 942 *num_pins = pctrl->groups[selector].npins; 943 944 return 0; 945} 946 947static const struct pinctrl_ops bm1880_pctrl_ops = { 948 .get_groups_count = bm1880_pctrl_get_groups_count, 949 .get_group_name = bm1880_pctrl_get_group_name, 950 .get_group_pins = bm1880_pctrl_get_group_pins, 951 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 952 .dt_free_map = pinctrl_utils_free_map, 953}; 954 955/* pinmux */ 956static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev) 957{ 958 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 959 960 return pctrl->nfuncs; 961} 962 963static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev, 964 unsigned int selector) 965{ 966 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 967 968 return pctrl->funcs[selector].name; 969} 970 971static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev, 972 unsigned int selector, 973 const char * const **groups, 974 unsigned * const num_groups) 975{ 976 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 977 978 *groups = pctrl->funcs[selector].groups; 979 *num_groups = pctrl->funcs[selector].ngroups; 980 return 0; 981} 982 983static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, 984 unsigned int function, 985 unsigned int group) 986{ 987 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 988 const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group]; 989 const struct bm1880_pinmux_function *func = &pctrl->funcs[function]; 990 int i; 991 992 for (i = 0; i < pgrp->npins; i++) { 993 unsigned int pin = pgrp->pins[i]; 994 u32 offset = (pin >> 1) << 2; 995 u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4); 996 u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + 997 offset); 998 999 regval &= ~(0x03 << mux_offset); 1000 regval |= func->mux_val << mux_offset; 1001 1002 writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); 1003 } 1004 1005 return 0; 1006} 1007 1008#define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx) 1009#define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0) 1010#define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1) 1011#define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2) 1012#define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6) 1013#define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9) 1014#define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10) 1015 1016static int bm1880_pinconf_drv_set(unsigned int mA, u32 width, 1017 u32 *regval, u32 bit_offset) 1018{ 1019 u32 _regval; 1020 1021 _regval = *regval; 1022 1023 /* 1024 * There are two sets of drive strength bit width exposed by the 1025 * SoC at 4mA step, hence we need to handle them separately. 1026 */ 1027 if (width == 0x03) { 1028 switch (mA) { 1029 case 4: 1030 _regval &= ~(width << bit_offset); 1031 _regval |= (0 << bit_offset); 1032 break; 1033 case 8: 1034 _regval &= ~(width << bit_offset); 1035 _regval |= (1 << bit_offset); 1036 break; 1037 case 12: 1038 _regval &= ~(width << bit_offset); 1039 _regval |= (2 << bit_offset); 1040 break; 1041 case 16: 1042 _regval &= ~(width << bit_offset); 1043 _regval |= (3 << bit_offset); 1044 break; 1045 case 20: 1046 _regval &= ~(width << bit_offset); 1047 _regval |= (4 << bit_offset); 1048 break; 1049 case 24: 1050 _regval &= ~(width << bit_offset); 1051 _regval |= (5 << bit_offset); 1052 break; 1053 case 28: 1054 _regval &= ~(width << bit_offset); 1055 _regval |= (6 << bit_offset); 1056 break; 1057 case 32: 1058 _regval &= ~(width << bit_offset); 1059 _regval |= (7 << bit_offset); 1060 break; 1061 default: 1062 return -EINVAL; 1063 } 1064 } else { 1065 switch (mA) { 1066 case 4: 1067 _regval &= ~(width << bit_offset); 1068 _regval |= (0 << bit_offset); 1069 break; 1070 case 8: 1071 _regval &= ~(width << bit_offset); 1072 _regval |= (1 << bit_offset); 1073 break; 1074 case 12: 1075 _regval &= ~(width << bit_offset); 1076 _regval |= (2 << bit_offset); 1077 break; 1078 case 16: 1079 _regval &= ~(width << bit_offset); 1080 _regval |= (3 << bit_offset); 1081 break; 1082 default: 1083 return -EINVAL; 1084 } 1085 } 1086 1087 *regval = _regval; 1088 1089 return 0; 1090} 1091 1092static int bm1880_pinconf_drv_get(u32 width, u32 drv) 1093{ 1094 int ret = -ENOTSUPP; 1095 1096 /* 1097 * There are two sets of drive strength bit width exposed by the 1098 * SoC at 4mA step, hence we need to handle them separately. 1099 */ 1100 if (width == 0x03) { 1101 switch (drv) { 1102 case 0: 1103 ret = 4; 1104 break; 1105 case 1: 1106 ret = 8; 1107 break; 1108 case 2: 1109 ret = 12; 1110 break; 1111 case 3: 1112 ret = 16; 1113 break; 1114 case 4: 1115 ret = 20; 1116 break; 1117 case 5: 1118 ret = 24; 1119 break; 1120 case 6: 1121 ret = 28; 1122 break; 1123 case 7: 1124 ret = 32; 1125 break; 1126 default: 1127 break; 1128 } 1129 } else { 1130 switch (drv) { 1131 case 0: 1132 ret = 4; 1133 break; 1134 case 1: 1135 ret = 8; 1136 break; 1137 case 2: 1138 ret = 12; 1139 break; 1140 case 3: 1141 ret = 16; 1142 break; 1143 default: 1144 break; 1145 } 1146 } 1147 1148 return ret; 1149} 1150 1151static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev, 1152 unsigned int pin, 1153 unsigned long *config) 1154{ 1155 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1156 unsigned int param = pinconf_to_config_param(*config); 1157 unsigned int arg = 0; 1158 u32 regval, offset, bit_offset; 1159 int ret; 1160 1161 offset = (pin >> 1) << 2; 1162 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); 1163 1164 switch (param) { 1165 case PIN_CONFIG_BIAS_PULL_UP: 1166 bit_offset = BM1880_PINCONF_PULLUP(pin); 1167 arg = !!(regval & BIT(bit_offset)); 1168 break; 1169 case PIN_CONFIG_BIAS_PULL_DOWN: 1170 bit_offset = BM1880_PINCONF_PULLDOWN(pin); 1171 arg = !!(regval & BIT(bit_offset)); 1172 break; 1173 case PIN_CONFIG_BIAS_DISABLE: 1174 bit_offset = BM1880_PINCONF_PULLCTRL(pin); 1175 arg = !!(regval & BIT(bit_offset)); 1176 break; 1177 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1178 bit_offset = BM1880_PINCONF_SCHMITT(pin); 1179 arg = !!(regval & BIT(bit_offset)); 1180 break; 1181 case PIN_CONFIG_SLEW_RATE: 1182 bit_offset = BM1880_PINCONF_SLEW(pin); 1183 arg = !!(regval & BIT(bit_offset)); 1184 break; 1185 case PIN_CONFIG_DRIVE_STRENGTH: 1186 bit_offset = BM1880_PINCONF_DRV(pin); 1187 ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits, 1188 !!(regval & BIT(bit_offset))); 1189 if (ret < 0) 1190 return ret; 1191 1192 arg = ret; 1193 break; 1194 default: 1195 return -ENOTSUPP; 1196 } 1197 1198 *config = pinconf_to_config_packed(param, arg); 1199 1200 return 0; 1201} 1202 1203static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev, 1204 unsigned int pin, 1205 unsigned long *configs, 1206 unsigned int num_configs) 1207{ 1208 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1209 u32 regval, offset, bit_offset; 1210 int i, ret; 1211 1212 offset = (pin >> 1) << 2; 1213 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); 1214 1215 for (i = 0; i < num_configs; i++) { 1216 unsigned int param = pinconf_to_config_param(configs[i]); 1217 unsigned int arg = pinconf_to_config_argument(configs[i]); 1218 1219 switch (param) { 1220 case PIN_CONFIG_BIAS_PULL_UP: 1221 bit_offset = BM1880_PINCONF_PULLUP(pin); 1222 regval |= BIT(bit_offset); 1223 break; 1224 case PIN_CONFIG_BIAS_PULL_DOWN: 1225 bit_offset = BM1880_PINCONF_PULLDOWN(pin); 1226 regval |= BIT(bit_offset); 1227 break; 1228 case PIN_CONFIG_BIAS_DISABLE: 1229 bit_offset = BM1880_PINCONF_PULLCTRL(pin); 1230 regval |= BIT(bit_offset); 1231 break; 1232 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1233 bit_offset = BM1880_PINCONF_SCHMITT(pin); 1234 if (arg) 1235 regval |= BIT(bit_offset); 1236 else 1237 regval &= ~BIT(bit_offset); 1238 break; 1239 case PIN_CONFIG_SLEW_RATE: 1240 bit_offset = BM1880_PINCONF_SLEW(pin); 1241 if (arg) 1242 regval |= BIT(bit_offset); 1243 else 1244 regval &= ~BIT(bit_offset); 1245 break; 1246 case PIN_CONFIG_DRIVE_STRENGTH: 1247 bit_offset = BM1880_PINCONF_DRV(pin); 1248 ret = bm1880_pinconf_drv_set(arg, 1249 pctrl->pinconf[pin].drv_bits, 1250 ®val, bit_offset); 1251 if (ret < 0) 1252 return ret; 1253 1254 break; 1255 default: 1256 dev_warn(pctldev->dev, 1257 "unsupported configuration parameter '%u'\n", 1258 param); 1259 continue; 1260 } 1261 1262 writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); 1263 } 1264 1265 return 0; 1266} 1267 1268static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev, 1269 unsigned int selector, 1270 unsigned long *configs, 1271 unsigned int num_configs) 1272{ 1273 int i, ret; 1274 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1275 const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector]; 1276 1277 for (i = 0; i < pgrp->npins; i++) { 1278 ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, 1279 num_configs); 1280 if (ret) 1281 return ret; 1282 } 1283 1284 return 0; 1285} 1286 1287static const struct pinconf_ops bm1880_pinconf_ops = { 1288 .is_generic = true, 1289 .pin_config_get = bm1880_pinconf_cfg_get, 1290 .pin_config_set = bm1880_pinconf_cfg_set, 1291 .pin_config_group_set = bm1880_pinconf_group_set, 1292}; 1293 1294static const struct pinmux_ops bm1880_pinmux_ops = { 1295 .get_functions_count = bm1880_pmux_get_functions_count, 1296 .get_function_name = bm1880_pmux_get_function_name, 1297 .get_function_groups = bm1880_pmux_get_function_groups, 1298 .set_mux = bm1880_pinmux_set_mux, 1299}; 1300 1301static struct pinctrl_desc bm1880_desc = { 1302 .name = "bm1880_pinctrl", 1303 .pins = bm1880_pins, 1304 .npins = ARRAY_SIZE(bm1880_pins), 1305 .pctlops = &bm1880_pctrl_ops, 1306 .pmxops = &bm1880_pinmux_ops, 1307 .confops = &bm1880_pinconf_ops, 1308 .owner = THIS_MODULE, 1309}; 1310 1311static int bm1880_pinctrl_probe(struct platform_device *pdev) 1312 1313{ 1314 struct bm1880_pinctrl *pctrl; 1315 1316 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1317 if (!pctrl) 1318 return -ENOMEM; 1319 1320 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1321 if (IS_ERR(pctrl->base)) 1322 return PTR_ERR(pctrl->base); 1323 1324 pctrl->groups = bm1880_pctrl_groups; 1325 pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups); 1326 pctrl->funcs = bm1880_pmux_functions; 1327 pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions); 1328 pctrl->pinconf = bm1880_pinconf; 1329 1330 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc, 1331 pctrl); 1332 if (IS_ERR(pctrl->pctrldev)) 1333 return PTR_ERR(pctrl->pctrldev); 1334 1335 platform_set_drvdata(pdev, pctrl); 1336 1337 dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n"); 1338 1339 return 0; 1340} 1341 1342static const struct of_device_id bm1880_pinctrl_of_match[] = { 1343 { .compatible = "bitmain,bm1880-pinctrl" }, 1344 { } 1345}; 1346 1347static struct platform_driver bm1880_pinctrl_driver = { 1348 .driver = { 1349 .name = "pinctrl-bm1880", 1350 .of_match_table = of_match_ptr(bm1880_pinctrl_of_match), 1351 }, 1352 .probe = bm1880_pinctrl_probe, 1353}; 1354 1355static int __init bm1880_pinctrl_init(void) 1356{ 1357 return platform_driver_register(&bm1880_pinctrl_driver); 1358} 1359arch_initcall(bm1880_pinctrl_init); 1360