1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_ 7#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_ 8 9/* Only for QMP V4 PHY - TX registers */ 10#define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11#define QSERDES_V4_TX_BIST_INVERT 0x004 12#define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 13#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14#define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 15#define QSERDES_V4_TX_TX_DRV_LVL 0x014 16#define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 17#define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 18#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 19#define QSERDES_V4_TX_TX_BAND 0x024 20#define QSERDES_V4_TX_SLEW_CNTL 0x028 21#define QSERDES_V4_TX_INTERFACE_SELECT 0x02c 22#define QSERDES_V4_TX_LPB_EN 0x030 23#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034 24#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038 25#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c 26#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040 27#define QSERDES_V4_TX_PERL_LENGTH1 0x044 28#define QSERDES_V4_TX_PERL_LENGTH2 0x048 29#define QSERDES_V4_TX_SERDES_BYP_EN_OUT 0x04c 30#define QSERDES_V4_TX_DEBUG_BUS_SEL 0x050 31#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054 32#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058 33#define QSERDES_V4_TX_TX_POL_INV 0x05c 34#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 35#define QSERDES_V4_TX_BIST_PATTERN1 0x064 36#define QSERDES_V4_TX_BIST_PATTERN2 0x068 37#define QSERDES_V4_TX_BIST_PATTERN3 0x06c 38#define QSERDES_V4_TX_BIST_PATTERN4 0x070 39#define QSERDES_V4_TX_BIST_PATTERN5 0x074 40#define QSERDES_V4_TX_BIST_PATTERN6 0x078 41#define QSERDES_V4_TX_BIST_PATTERN7 0x07c 42#define QSERDES_V4_TX_BIST_PATTERN8 0x080 43#define QSERDES_V4_TX_LANE_MODE_1 0x084 44#define QSERDES_V4_TX_LANE_MODE_2 0x088 45#define QSERDES_V4_TX_LANE_MODE_3 0x08c 46#define QSERDES_V4_TX_ATB_SEL1 0x090 47#define QSERDES_V4_TX_ATB_SEL2 0x094 48#define QSERDES_V4_TX_RCV_DETECT_LVL 0x098 49#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c 50#define QSERDES_V4_TX_PRBS_SEED1 0x0a0 51#define QSERDES_V4_TX_PRBS_SEED2 0x0a4 52#define QSERDES_V4_TX_PRBS_SEED3 0x0a8 53#define QSERDES_V4_TX_PRBS_SEED4 0x0ac 54#define QSERDES_V4_TX_RESET_GEN 0x0b0 55#define QSERDES_V4_TX_RESET_GEN_MUXES 0x0b4 56#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8 57#define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc 58#define QSERDES_V4_TX_PWM_CTRL 0x0c0 59#define QSERDES_V4_TX_PWM_ENCODED_OR_DATA 0x0c4 60#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0c8 61#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0cc 62#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0d0 63#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0d4 64#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8 65#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc 66#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0 67#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4 68#define QSERDES_V4_TX_VMODE_CTRL1 0x0e8 69#define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1 0x0ec 70#define QSERDES_V4_TX_BIST_STATUS 0x0f0 71#define QSERDES_V4_TX_BIST_ERROR_COUNT1 0x0f4 72#define QSERDES_V4_TX_BIST_ERROR_COUNT2 0x0f8 73#define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1 0x0fc 74#define QSERDES_V4_TX_LANE_DIG_CONFIG 0x100 75#define QSERDES_V4_TX_PI_QEC_CTRL 0x104 76#define QSERDES_V4_TX_PRE_EMPH 0x108 77#define QSERDES_V4_TX_SW_RESET 0x10c 78#define QSERDES_V4_TX_DCC_OFFSET 0x110 79#define QSERDES_V4_TX_DIG_BKUP_CTRL 0x114 80#define QSERDES_V4_TX_DEBUG_BUS0 0x118 81#define QSERDES_V4_TX_DEBUG_BUS1 0x11c 82#define QSERDES_V4_TX_DEBUG_BUS2 0x120 83#define QSERDES_V4_TX_DEBUG_BUS3 0x124 84#define QSERDES_V4_TX_READ_EQCODE 0x128 85#define QSERDES_V4_TX_READ_OFFSETCODE 0x12c 86#define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW 0x130 87#define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH 0x134 88#define QSERDES_V4_TX_VGA_READ_CODE 0x138 89#define QSERDES_V4_TX_VTH_READ_CODE 0x13c 90#define QSERDES_V4_TX_DFE_TAP1_READ_CODE 0x140 91#define QSERDES_V4_TX_DFE_TAP2_READ_CODE 0x144 92#define QSERDES_V4_TX_IDAC_STATUS_I 0x148 93#define QSERDES_V4_TX_IDAC_STATUS_IBAR 0x14c 94#define QSERDES_V4_TX_IDAC_STATUS_Q 0x150 95#define QSERDES_V4_TX_IDAC_STATUS_QBAR 0x154 96#define QSERDES_V4_TX_IDAC_STATUS_A 0x158 97#define QSERDES_V4_TX_IDAC_STATUS_ABAR 0x15c 98#define QSERDES_V4_TX_IDAC_STATUS_SM_ON 0x160 99#define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE 0x164 100#define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR 0x168 101#define QSERDES_V4_TX_DCC_CAL_STATUS 0x16c 102 103/* Only for QMP V4 PHY - RX registers */ 104#define QSERDES_V4_RX_UCDR_FO_GAIN_HALF 0x000 105#define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER 0x004 106#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 107#define QSERDES_V4_RX_UCDR_SO_GAIN_HALF 0x00c 108#define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER 0x010 109#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 110#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF 0x018 111#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c 112#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN 0x020 113#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF 0x024 114#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 115#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN 0x02c 116#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 117#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 118#define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY 0x038 119#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 120#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 121#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 122#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 123#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 124#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 125#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 126#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 127#define QSERDES_V4_RX_AUX_CONTROL 0x05c 128#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 129#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 130#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 131#define QSERDES_V4_RX_AC_JTAG_INITP 0x06c 132#define QSERDES_V4_RX_AC_JTAG_INITN 0x070 133#define QSERDES_V4_RX_AC_JTAG_LVL 0x074 134#define QSERDES_V4_RX_AC_JTAG_MODE 0x078 135#define QSERDES_V4_RX_AC_JTAG_RESET 0x07c 136#define QSERDES_V4_RX_RX_TERM_BW 0x080 137#define QSERDES_V4_RX_RX_RCVR_IQ_EN 0x084 138#define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS 0x088 139#define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c 140#define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS 0x090 141#define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 142#define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS 0x098 143#define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c 144#define QSERDES_V4_RX_RX_IDAC_EN 0x0a0 145#define QSERDES_V4_RX_RX_IDAC_ENABLES 0x0a4 146#define QSERDES_V4_RX_RX_IDAC_SIGN 0x0a8 147#define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE 0x0ac 148#define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 149#define QSERDES_V4_RX_DFE_1 0x0b4 150#define QSERDES_V4_RX_DFE_2 0x0b8 151#define QSERDES_V4_RX_DFE_3 0x0bc 152#define QSERDES_V4_RX_DFE_4 0x0c0 153#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1 0x0c4 154#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2 0x0c8 155#define QSERDES_V4_RX_TX_ADAPT_POST_THRESH 0x0cc 156#define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH 0x0d0 157#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 158#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 159#define QSERDES_V4_RX_GM_CAL 0x0dc 160#define QSERDES_V4_RX_RX_VGA_GAIN2_LSB 0x0e0 161#define QSERDES_V4_RX_RX_VGA_GAIN2_MSB 0x0e4 162#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 163#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 164#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 165#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 166#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 167#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 168#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 169#define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR 0x104 170#define QSERDES_V4_RX_RX_EQ_OFFSET_LSB 0x108 171#define QSERDES_V4_RX_RX_EQ_OFFSET_MSB 0x10c 172#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 173#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 174#define QSERDES_V4_RX_SIGDET_ENABLES 0x118 175#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 176#define QSERDES_V4_RX_SIGDET_LVL 0x120 177#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 178#define QSERDES_V4_RX_RX_BAND 0x128 179#define QSERDES_V4_RX_CDR_FREEZE_UP_DN 0x12c 180#define QSERDES_V4_RX_CDR_RESET_OVERRIDE 0x130 181#define QSERDES_V4_RX_RX_INTERFACE_MODE 0x134 182#define QSERDES_V4_RX_JITTER_GEN_MODE 0x138 183#define QSERDES_V4_RX_SJ_AMP1 0x13c 184#define QSERDES_V4_RX_SJ_AMP2 0x140 185#define QSERDES_V4_RX_SJ_PER1 0x144 186#define QSERDES_V4_RX_SJ_PER2 0x148 187#define QSERDES_V4_RX_PPM_OFFSET1 0x14c 188#define QSERDES_V4_RX_PPM_OFFSET2 0x150 189#define QSERDES_V4_RX_SIGN_PPM_PERIOD1 0x154 190#define QSERDES_V4_RX_SIGN_PPM_PERIOD2 0x158 191#define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA 0x15c 192#define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x160 193#define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x164 194#define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x168 195#define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x16c 196#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 197#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 198#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 199#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 200#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 201#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 202#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 203#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 204#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 205#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 206#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 207#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 208#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 209#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 210#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 211#define QSERDES_V4_RX_PHPRE_CTRL 0x1ac 212#define QSERDES_V4_RX_PHPRE_INITVAL 0x1b0 213#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 214#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 215#define QSERDES_V4_RX_DCC_CTRL1 0x1bc 216#define QSERDES_V4_RX_DCC_CTRL2 0x1c0 217#define QSERDES_V4_RX_VTH_CODE 0x1c4 218#define QSERDES_V4_RX_VTH_MIN_THRESH 0x1c8 219#define QSERDES_V4_RX_VTH_MAX_THRESH 0x1cc 220#define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1 0x1d0 221#define QSERDES_V4_RX_PI_CTRL1 0x1d4 222#define QSERDES_V4_RX_PI_CTRL2 0x1d8 223#define QSERDES_V4_RX_PI_QUAD 0x1dc 224#define QSERDES_V4_RX_IDATA1 0x1e0 225#define QSERDES_V4_RX_IDATA2 0x1e4 226#define QSERDES_V4_RX_AUX_DATA1 0x1e8 227#define QSERDES_V4_RX_AUX_DATA2 0x1ec 228#define QSERDES_V4_RX_AC_JTAG_OUTP 0x1f0 229#define QSERDES_V4_RX_AC_JTAG_OUTN 0x1f4 230#define QSERDES_V4_RX_RX_SIGDET 0x1f8 231#define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1 0x1fc 232 233#endif 234