1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_ 7#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_ 8 9/* Only for QMP V3 PHY - TX registers */ 10#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 11#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 12#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 13#define QSERDES_V3_TX_TX_DRV_LVL 0x01c 14#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 15#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 16#define QSERDES_V3_TX_TX_BAND 0x02c 17#define QSERDES_V3_TX_SLEW_CNTL 0x030 18#define QSERDES_V3_TX_INTERFACE_SELECT 0x034 19#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 20#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 21#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 22#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 23#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 24#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 25#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 26#define QSERDES_V3_TX_TX_POL_INV 0x064 27#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 28#define QSERDES_V3_TX_LANE_MODE_1 0x08c 29#define QSERDES_V3_TX_LANE_MODE_2 0x090 30#define QSERDES_V3_TX_LANE_MODE_3 0x094 31#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 32#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 33#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 34#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 35 36/* Only for QMP V3 PHY - RX registers */ 37#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 38#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 39#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 40#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 41#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 42#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 43#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 44#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 45#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 46#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 47#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 48#define QSERDES_V3_RX_RX_TERM_BW 0x07c 49#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 50#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 51#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 52#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 53#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0 54#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 55#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 56#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 57#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 58#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 59#define QSERDES_V3_RX_SIGDET_ENABLES 0x100 60#define QSERDES_V3_RX_SIGDET_CNTRL 0x104 61#define QSERDES_V3_RX_SIGDET_LVL 0x108 62#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 63#define QSERDES_V3_RX_RX_BAND 0x110 64#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 65#define QSERDES_V3_RX_RX_MODE_00 0x164 66#define QSERDES_V3_RX_RX_MODE_01 0x168 67 68#endif 69