1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MediaTek 10GE SerDes XFI T-PHY driver 4 * 5 * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org> 6 * Bc-bocun Chen <bc-bocun.chen@mediatek.com> 7 * based on mtk_usxgmii.c and mtk_sgmii.c found in MediaTek's SDK (GPL-2.0) 8 * Copyright (c) 2022 MediaTek Inc. 9 * Author: Henry Yen <henry.yen@mediatek.com> 10 */ 11 12#include <linux/module.h> 13#include <linux/device.h> 14#include <linux/platform_device.h> 15#include <linux/of.h> 16#include <linux/io.h> 17#include <linux/clk.h> 18#include <linux/reset.h> 19#include <linux/phy.h> 20#include <linux/phy/phy.h> 21 22#include "phy-mtk-io.h" 23 24#define MTK_XFI_TPHY_NUM_CLOCKS 2 25 26#define REG_DIG_GLB_70 0x0070 27#define XTP_PCS_RX_EQ_IN_PROGRESS(x) FIELD_PREP(GENMASK(25, 24), (x)) 28#define XTP_PCS_MODE_MASK GENMASK(17, 16) 29#define XTP_PCS_MODE(x) FIELD_PREP(GENMASK(17, 16), (x)) 30#define XTP_PCS_RST_B BIT(15) 31#define XTP_FRC_PCS_RST_B BIT(14) 32#define XTP_PCS_PWD_SYNC_MASK GENMASK(13, 12) 33#define XTP_PCS_PWD_SYNC(x) FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x)) 34#define XTP_PCS_PWD_ASYNC_MASK GENMASK(11, 10) 35#define XTP_PCS_PWD_ASYNC(x) FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x)) 36#define XTP_FRC_PCS_PWD_ASYNC BIT(8) 37#define XTP_PCS_UPDT BIT(4) 38#define XTP_PCS_IN_FR_RG BIT(0) 39 40#define REG_DIG_GLB_F4 0x00f4 41#define XFI_DPHY_PCS_SEL BIT(0) 42#define XFI_DPHY_PCS_SEL_SGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 1) 43#define XFI_DPHY_PCS_SEL_USXGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 0) 44#define XFI_DPHY_AD_SGDT_FRC_EN BIT(5) 45 46#define REG_DIG_LN_TRX_40 0x3040 47#define XTP_LN_FRC_TX_DATA_EN BIT(29) 48#define XTP_LN_TX_DATA_EN BIT(28) 49 50#define REG_DIG_LN_TRX_B0 0x30b0 51#define XTP_LN_FRC_TX_MACCK_EN BIT(5) 52#define XTP_LN_TX_MACCK_EN BIT(4) 53 54#define REG_ANA_GLB_D0 0x90d0 55#define XTP_GLB_USXGMII_SEL_MASK GENMASK(3, 1) 56#define XTP_GLB_USXGMII_SEL(x) FIELD_PREP(GENMASK(3, 1), (x)) 57#define XTP_GLB_USXGMII_EN BIT(0) 58 59/** 60 * struct mtk_xfi_tphy - run-time data of the XFI phy instance 61 * @base: IO memory area to access phy registers. 62 * @dev: Kernel device used to output prefixed debug info. 63 * @reset: Reset control corresponding to the phy instance. 64 * @clocks: All clocks required for the phy to operate. 65 * @da_war: Enables work-around for 10GBase-R mode. 66 */ 67struct mtk_xfi_tphy { 68 void __iomem *base; 69 struct device *dev; 70 struct reset_control *reset; 71 struct clk_bulk_data clocks[MTK_XFI_TPHY_NUM_CLOCKS]; 72 bool da_war; 73}; 74 75/** 76 * mtk_xfi_tphy_setup() - Setup phy for specified interface mode. 77 * @xfi_tphy: XFI phy instance. 78 * @interface: Ethernet interface mode 79 * 80 * The setup function is the condensed result of combining the 5 functions which 81 * setup the phy in MediaTek's GPL licensed public SDK sources. They can be found 82 * in mtk_sgmii.c[1] as well as mtk_usxgmii.c[2]. 83 * 84 * Many magic values have been replaced by register and bit definitions, however, 85 * that has not been possible in all cases. While the vendor driver uses a 86 * sequence of 32-bit writes, here we try to only modify the actually required 87 * bits. 88 * 89 * [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/b72d6cba92bf9e29fb035c03052fa1e86664a25b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c 90 * 91 * [2]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/dec96a1d9b82cdcda4a56453fd0b453d4cab4b85/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c 92 */ 93static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy, 94 phy_interface_t interface) 95{ 96 bool is_1g, is_2p5g, is_5g, is_10g, da_war, use_lynxi_pcs; 97 98 /* shorthands for specific clock speeds depending on interface mode */ 99 is_1g = interface == PHY_INTERFACE_MODE_1000BASEX || 100 interface == PHY_INTERFACE_MODE_SGMII; 101 is_2p5g = interface == PHY_INTERFACE_MODE_2500BASEX; 102 is_5g = interface == PHY_INTERFACE_MODE_5GBASER; 103 is_10g = interface == PHY_INTERFACE_MODE_10GBASER || 104 interface == PHY_INTERFACE_MODE_USXGMII; 105 106 /* Is overriding 10GBase-R tuning value required? */ 107 da_war = xfi_tphy->da_war && (interface == PHY_INTERFACE_MODE_10GBASER); 108 109 /* configure input mux to either 110 * - USXGMII PCS (64b/66b coding) for 5G/10G 111 * - LynxI PCS (8b/10b coding) for 1G/2.5G 112 */ 113 use_lynxi_pcs = is_1g || is_2p5g; 114 115 dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface)); 116 117 /* Setup PLL setting */ 118 mtk_phy_update_bits(xfi_tphy->base + 0x9024, 0x100000, is_10g ? 0x0 : 0x100000); 119 mtk_phy_update_bits(xfi_tphy->base + 0x2020, 0x202000, is_5g ? 0x202000 : 0x0); 120 mtk_phy_update_bits(xfi_tphy->base + 0x2030, 0x500, is_1g ? 0x0 : 0x500); 121 mtk_phy_update_bits(xfi_tphy->base + 0x2034, 0xa00, is_1g ? 0x0 : 0xa00); 122 mtk_phy_update_bits(xfi_tphy->base + 0x2040, 0x340000, is_1g ? 0x200000 : 0x140000); 123 124 /* Setup RXFE BW setting */ 125 mtk_phy_update_bits(xfi_tphy->base + 0x50f0, 0xc10, is_1g ? 0x410 : is_5g ? 0x800 : 0x400); 126 mtk_phy_update_bits(xfi_tphy->base + 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000); 127 128 /* Setup RX CDR setting */ 129 mtk_phy_update_bits(xfi_tphy->base + 0x506c, 0x30000, is_5g ? 0x0 : 0x30000); 130 mtk_phy_update_bits(xfi_tphy->base + 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000); 131 mtk_phy_update_bits(xfi_tphy->base + 0x5074, 0x180000, is_5g ? 0x180000 : 0x0); 132 mtk_phy_update_bits(xfi_tphy->base + 0x5078, 0xf000400, is_5g ? 0x8000000 : 133 0x7000400); 134 mtk_phy_update_bits(xfi_tphy->base + 0x507c, 0x5000500, is_5g ? 0x4000400 : 135 0x1000100); 136 mtk_phy_update_bits(xfi_tphy->base + 0x5080, 0x1410, is_1g ? 0x400 : is_5g ? 0x1010 : 0x0); 137 mtk_phy_update_bits(xfi_tphy->base + 0x5084, 0x30300, is_1g ? 0x30300 : 138 is_5g ? 0x30100 : 139 0x100); 140 mtk_phy_update_bits(xfi_tphy->base + 0x5088, 0x60200, is_1g ? 0x20200 : 141 is_5g ? 0x40000 : 142 0x20000); 143 144 /* Setting RXFE adaptation range setting */ 145 mtk_phy_update_bits(xfi_tphy->base + 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000); 146 mtk_phy_update_bits(xfi_tphy->base + 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000); 147 mtk_phy_update_bits(xfi_tphy->base + 0x50ec, 0xa00, is_1g ? 0x200 : 0x800); 148 mtk_phy_update_bits(xfi_tphy->base + 0x50a8, 0xee0000, is_5g ? 0x800000 : 149 0x6e0000); 150 mtk_phy_update_bits(xfi_tphy->base + 0x6004, 0x190000, is_5g ? 0x0 : 0x190000); 151 152 if (is_10g) 153 writel(0x01423342, xfi_tphy->base + 0x00f8); 154 else if (is_5g) 155 writel(0x00a132a1, xfi_tphy->base + 0x00f8); 156 else if (is_2p5g) 157 writel(0x009c329c, xfi_tphy->base + 0x00f8); 158 else 159 writel(0x00fa32fa, xfi_tphy->base + 0x00f8); 160 161 /* Force SGDT_OUT off and select PCS */ 162 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_F4, 163 XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL, 164 XFI_DPHY_AD_SGDT_FRC_EN | 165 (use_lynxi_pcs ? XFI_DPHY_PCS_SEL_SGMII : 166 XFI_DPHY_PCS_SEL_USXGMII)); 167 168 /* Force GLB_CKDET_OUT */ 169 mtk_phy_set_bits(xfi_tphy->base + 0x0030, 0xc00); 170 171 /* Force AEQ on */ 172 writel(XTP_PCS_RX_EQ_IN_PROGRESS(2) | XTP_PCS_PWD_SYNC(2) | XTP_PCS_PWD_ASYNC(2), 173 xfi_tphy->base + REG_DIG_GLB_70); 174 175 usleep_range(1, 5); 176 writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40); 177 178 /* Setup TX DA default value */ 179 mtk_phy_update_bits(xfi_tphy->base + 0x30b0, 0x30, 0x20); 180 writel(0x00008a01, xfi_tphy->base + 0x3028); 181 writel(0x0000a884, xfi_tphy->base + 0x302c); 182 writel(0x00083002, xfi_tphy->base + 0x3024); 183 184 /* Setup RG default value */ 185 if (use_lynxi_pcs) { 186 writel(0x00011110, xfi_tphy->base + 0x3010); 187 writel(0x40704000, xfi_tphy->base + 0x3048); 188 } else { 189 writel(0x00022220, xfi_tphy->base + 0x3010); 190 writel(0x0f020a01, xfi_tphy->base + 0x5064); 191 writel(0x06100600, xfi_tphy->base + 0x50b4); 192 if (interface == PHY_INTERFACE_MODE_USXGMII) 193 writel(0x40704000, xfi_tphy->base + 0x3048); 194 else 195 writel(0x47684100, xfi_tphy->base + 0x3048); 196 } 197 198 if (is_1g) 199 writel(0x0000c000, xfi_tphy->base + 0x3064); 200 201 /* Setup RX EQ initial value */ 202 mtk_phy_update_bits(xfi_tphy->base + 0x3050, 0xa8000000, 203 (interface != PHY_INTERFACE_MODE_10GBASER) ? 0xa8000000 : 0x0); 204 mtk_phy_update_bits(xfi_tphy->base + 0x3054, 0xaa, 205 (interface != PHY_INTERFACE_MODE_10GBASER) ? 0xaa : 0x0); 206 207 if (!use_lynxi_pcs) 208 writel(0x00000f00, xfi_tphy->base + 0x306c); 209 else if (is_2p5g) 210 writel(0x22000f00, xfi_tphy->base + 0x306c); 211 else 212 writel(0x20200f00, xfi_tphy->base + 0x306c); 213 214 mtk_phy_update_bits(xfi_tphy->base + 0xa008, 0x10000, da_war ? 0x10000 : 0x0); 215 216 mtk_phy_update_bits(xfi_tphy->base + 0xa060, 0x50000, use_lynxi_pcs ? 0x50000 : 0x40000); 217 218 /* Setup PHYA speed */ 219 mtk_phy_update_bits(xfi_tphy->base + REG_ANA_GLB_D0, 220 XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN, 221 is_10g ? XTP_GLB_USXGMII_SEL(0) : 222 is_5g ? XTP_GLB_USXGMII_SEL(1) : 223 is_2p5g ? XTP_GLB_USXGMII_SEL(2) : 224 XTP_GLB_USXGMII_SEL(3)); 225 mtk_phy_set_bits(xfi_tphy->base + REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN); 226 227 /* Release reset */ 228 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_GLB_70, 229 XTP_PCS_RST_B | XTP_FRC_PCS_RST_B); 230 usleep_range(150, 500); 231 232 /* Switch to P0 */ 233 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, 234 XTP_PCS_IN_FR_RG | 235 XTP_FRC_PCS_PWD_ASYNC | 236 XTP_PCS_PWD_ASYNC_MASK | 237 XTP_PCS_PWD_SYNC_MASK | 238 XTP_PCS_UPDT, 239 XTP_PCS_IN_FR_RG | 240 XTP_FRC_PCS_PWD_ASYNC | 241 XTP_PCS_UPDT); 242 usleep_range(1, 5); 243 244 mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT); 245 usleep_range(15, 50); 246 247 if (use_lynxi_pcs) { 248 /* Switch to Gen2 */ 249 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, 250 XTP_PCS_MODE_MASK | XTP_PCS_UPDT, 251 XTP_PCS_MODE(1) | XTP_PCS_UPDT); 252 } else { 253 /* Switch to Gen3 */ 254 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, 255 XTP_PCS_MODE_MASK | XTP_PCS_UPDT, 256 XTP_PCS_MODE(2) | XTP_PCS_UPDT); 257 } 258 usleep_range(1, 5); 259 260 mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT); 261 262 usleep_range(100, 500); 263 264 /* Enable MAC CK */ 265 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN); 266 mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN); 267 268 /* Enable TX data */ 269 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_40, 270 XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN); 271 usleep_range(400, 1000); 272} 273 274/** 275 * mtk_xfi_tphy_set_mode() - Setup phy for specified interface mode. 276 * 277 * @phy: Phy instance. 278 * @mode: Only PHY_MODE_ETHERNET is supported. 279 * @submode: An Ethernet interface mode. 280 * 281 * Validate selected mode and call function mtk_xfi_tphy_setup(). 282 * 283 * Return: 284 * * %0 - OK 285 * * %-EINVAL - invalid mode 286 */ 287static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int 288 submode) 289{ 290 struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy); 291 292 if (mode != PHY_MODE_ETHERNET) 293 return -EINVAL; 294 295 switch (submode) { 296 case PHY_INTERFACE_MODE_1000BASEX: 297 case PHY_INTERFACE_MODE_2500BASEX: 298 case PHY_INTERFACE_MODE_SGMII: 299 case PHY_INTERFACE_MODE_5GBASER: 300 case PHY_INTERFACE_MODE_10GBASER: 301 case PHY_INTERFACE_MODE_USXGMII: 302 mtk_xfi_tphy_setup(xfi_tphy, submode); 303 return 0; 304 default: 305 return -EINVAL; 306 } 307} 308 309/** 310 * mtk_xfi_tphy_reset() - Reset the phy. 311 * 312 * @phy: Phy instance. 313 * 314 * Reset the phy using the external reset controller. 315 * 316 * Return: 317 * %0 - OK 318 */ 319static int mtk_xfi_tphy_reset(struct phy *phy) 320{ 321 struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy); 322 323 reset_control_assert(xfi_tphy->reset); 324 usleep_range(100, 500); 325 reset_control_deassert(xfi_tphy->reset); 326 usleep_range(1, 10); 327 328 return 0; 329} 330 331/** 332 * mtk_xfi_tphy_power_on() - Power-on the phy. 333 * 334 * @phy: Phy instance. 335 * 336 * Prepare and enable all clocks required for the phy to operate. 337 * 338 * Return: 339 * See clk_bulk_prepare_enable(). 340 */ 341static int mtk_xfi_tphy_power_on(struct phy *phy) 342{ 343 struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy); 344 345 return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks); 346} 347 348/** 349 * mtk_xfi_tphy_power_off() - Power-off the phy. 350 * 351 * @phy: Phy instance. 352 * 353 * Disable and unprepare all clocks previously enabled. 354 * 355 * Return: 356 * See clk_bulk_prepare_disable(). 357 */ 358static int mtk_xfi_tphy_power_off(struct phy *phy) 359{ 360 struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy); 361 362 clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks); 363 364 return 0; 365} 366 367static const struct phy_ops mtk_xfi_tphy_ops = { 368 .power_on = mtk_xfi_tphy_power_on, 369 .power_off = mtk_xfi_tphy_power_off, 370 .set_mode = mtk_xfi_tphy_set_mode, 371 .reset = mtk_xfi_tphy_reset, 372 .owner = THIS_MODULE, 373}; 374 375/** 376 * mtk_xfi_tphy_probe() - Probe phy instance from Device Tree. 377 * @pdev: Matching platform device. 378 * 379 * The probe function gets IO resource, clocks, reset controller and 380 * whether the DA work-around for 10GBase-R is required from Device Tree and 381 * allocates memory for holding that information in a struct mtk_xfi_tphy. 382 * 383 * Return: 384 * * %0 - OK 385 * * %-ENODEV - Missing associated Device Tree node (should never happen). 386 * * %-ENOMEM - Out of memory. 387 * * Any error value which devm_platform_ioremap_resource(), 388 * devm_clk_bulk_get(), devm_reset_control_get_exclusive(), 389 * devm_phy_create() or devm_of_phy_provider_register() may return. 390 */ 391static int mtk_xfi_tphy_probe(struct platform_device *pdev) 392{ 393 struct device_node *np = pdev->dev.of_node; 394 struct phy_provider *phy_provider; 395 struct mtk_xfi_tphy *xfi_tphy; 396 struct phy *phy; 397 int ret; 398 399 if (!np) 400 return -ENODEV; 401 402 xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL); 403 if (!xfi_tphy) 404 return -ENOMEM; 405 406 xfi_tphy->base = devm_platform_ioremap_resource(pdev, 0); 407 if (IS_ERR(xfi_tphy->base)) 408 return PTR_ERR(xfi_tphy->base); 409 410 xfi_tphy->dev = &pdev->dev; 411 xfi_tphy->clocks[0].id = "topxtal"; 412 xfi_tphy->clocks[1].id = "xfipll"; 413 ret = devm_clk_bulk_get(&pdev->dev, MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks); 414 if (ret) 415 return ret; 416 417 xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 418 if (IS_ERR(xfi_tphy->reset)) 419 return PTR_ERR(xfi_tphy->reset); 420 421 xfi_tphy->da_war = of_property_read_bool(np, "mediatek,usxgmii-performance-errata"); 422 423 phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops); 424 if (IS_ERR(phy)) 425 return PTR_ERR(phy); 426 427 phy_set_drvdata(phy, xfi_tphy); 428 phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); 429 430 return PTR_ERR_OR_ZERO(phy_provider); 431} 432 433static const struct of_device_id mtk_xfi_tphy_match[] = { 434 { .compatible = "mediatek,mt7988-xfi-tphy", }, 435 { /* sentinel */ } 436}; 437MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match); 438 439static struct platform_driver mtk_xfi_tphy_driver = { 440 .probe = mtk_xfi_tphy_probe, 441 .driver = { 442 .name = "mtk-xfi-tphy", 443 .of_match_table = mtk_xfi_tphy_match, 444 }, 445}; 446module_platform_driver(mtk_xfi_tphy_driver); 447 448MODULE_DESCRIPTION("MediaTek 10GE SerDes XFI T-PHY driver"); 449MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 450MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>"); 451MODULE_LICENSE("GPL"); 452