1// SPDX-License-Identifier: GPL-2.0-only 2/* Low-level parallel-port routines for 8255-based PC-style hardware. 3 * 4 * Authors: Phil Blundell <philb@gnu.org> 5 * Tim Waugh <tim@cyberelk.demon.co.uk> 6 * Jose Renau <renau@acm.org> 7 * David Campbell 8 * Andrea Arcangeli 9 * 10 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. 11 * 12 * Cleaned up include files - Russell King <linux@arm.uk.linux.org> 13 * DMA support - Bert De Jonghe <bert@sophis.be> 14 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 15 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. 16 * Various hacks, Fred Barnes, 04/2001 17 * Updated probing logic - Adam Belay <ambx1@neo.rr.com> 18 */ 19 20/* This driver should work with any hardware that is broadly compatible 21 * with that in the IBM PC. This applies to the majority of integrated 22 * I/O chipsets that are commonly available. The expected register 23 * layout is: 24 * 25 * base+0 data 26 * base+1 status 27 * base+2 control 28 * 29 * In addition, there are some optional registers: 30 * 31 * base+3 EPP address 32 * base+4 EPP data 33 * base+0x400 ECP config A 34 * base+0x401 ECP config B 35 * base+0x402 ECP control 36 * 37 * All registers are 8 bits wide and read/write. If your hardware differs 38 * only in register addresses (eg because your registers are on 32-bit 39 * word boundaries) then you can alter the constants in parport_pc.h to 40 * accommodate this. 41 * 42 * Note that the ECP registers may not start at offset 0x400 for PCI cards, 43 * but rather will start at port->base_hi. 44 */ 45 46#include <linux/module.h> 47#include <linux/init.h> 48#include <linux/sched/signal.h> 49#include <linux/delay.h> 50#include <linux/errno.h> 51#include <linux/interrupt.h> 52#include <linux/ioport.h> 53#include <linux/kernel.h> 54#include <linux/slab.h> 55#include <linux/dma-mapping.h> 56#include <linux/pci.h> 57#include <linux/pnp.h> 58#include <linux/platform_device.h> 59#include <linux/sysctl.h> 60#include <linux/io.h> 61#include <linux/uaccess.h> 62 63#include <asm/dma.h> 64 65#include <linux/parport.h> 66#include <linux/parport_pc.h> 67#include <linux/via.h> 68#include <asm/parport.h> 69 70#define PARPORT_PC_MAX_PORTS PARPORT_MAX 71 72#ifdef CONFIG_ISA_DMA_API 73#define HAS_DMA 74#endif 75 76/* ECR modes */ 77#define ECR_SPP 00 78#define ECR_PS2 01 79#define ECR_PPF 02 80#define ECR_ECP 03 81#define ECR_EPP 04 82#define ECR_VND 05 83#define ECR_TST 06 84#define ECR_CNF 07 85#define ECR_MODE_MASK 0xe0 86#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v)) 87 88#undef DEBUG 89 90#define NR_SUPERIOS 3 91static struct superio_struct { /* For Super-IO chips autodetection */ 92 int io; 93 int irq; 94 int dma; 95} superios[NR_SUPERIOS] = { {0,},}; 96 97static int user_specified; 98#if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 99 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 100static int verbose_probing; 101#endif 102static int pci_registered_parport; 103static int pnp_registered_parport; 104 105/* frob_control, but for ECR */ 106static void frob_econtrol(struct parport *pb, unsigned char m, 107 unsigned char v) 108{ 109 const struct parport_pc_private *priv = pb->physport->private_data; 110 unsigned char ecr_writable = priv->ecr_writable; 111 unsigned char ectr = 0; 112 unsigned char new; 113 114 if (m != 0xff) 115 ectr = inb(ECONTROL(pb)); 116 117 new = (ectr & ~m) ^ v; 118 if (ecr_writable) 119 /* All known users of the ECR mask require bit 0 to be set. */ 120 new = (new & ecr_writable) | 1; 121 122 pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", m, v, ectr, new); 123 124 outb(new, ECONTROL(pb)); 125} 126 127static inline void frob_set_mode(struct parport *p, int mode) 128{ 129 frob_econtrol(p, ECR_MODE_MASK, mode << 5); 130} 131 132#ifdef CONFIG_PARPORT_PC_FIFO 133/* Safely change the mode bits in the ECR 134 Returns: 135 0 : Success 136 -EBUSY: Could not drain FIFO in some finite amount of time, 137 mode not changed! 138 */ 139static int change_mode(struct parport *p, int m) 140{ 141 const struct parport_pc_private *priv = p->physport->private_data; 142 unsigned char oecr; 143 int mode; 144 145 pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m); 146 147 if (!priv->ecr) { 148 printk(KERN_DEBUG "change_mode: but there's no ECR!\n"); 149 return 0; 150 } 151 152 /* Bits <7:5> contain the mode. */ 153 oecr = inb(ECONTROL(p)); 154 mode = (oecr >> 5) & 0x7; 155 if (mode == m) 156 return 0; 157 158 if (mode >= 2 && !(priv->ctr & 0x20)) { 159 /* This mode resets the FIFO, so we may 160 * have to wait for it to drain first. */ 161 unsigned long expire = jiffies + p->physport->cad->timeout; 162 int counter; 163 switch (mode) { 164 case ECR_PPF: /* Parallel Port FIFO mode */ 165 case ECR_ECP: /* ECP Parallel Port mode */ 166 /* Busy wait for 200us */ 167 for (counter = 0; counter < 40; counter++) { 168 if (inb(ECONTROL(p)) & 0x01) 169 break; 170 if (signal_pending(current)) 171 break; 172 udelay(5); 173 } 174 175 /* Poll slowly. */ 176 while (!(inb(ECONTROL(p)) & 0x01)) { 177 if (time_after_eq(jiffies, expire)) 178 /* The FIFO is stuck. */ 179 return -EBUSY; 180 schedule_timeout_interruptible( 181 msecs_to_jiffies(10)); 182 if (signal_pending(current)) 183 break; 184 } 185 } 186 } 187 188 if (mode >= 2 && m >= 2) { 189 /* We have to go through mode 001 */ 190 oecr &= ~(7 << 5); 191 oecr |= ECR_PS2 << 5; 192 ECR_WRITE(p, oecr); 193 } 194 195 /* Set the mode. */ 196 oecr &= ~(7 << 5); 197 oecr |= m << 5; 198 ECR_WRITE(p, oecr); 199 return 0; 200} 201#endif /* FIFO support */ 202 203/* 204 * Clear TIMEOUT BIT in EPP MODE 205 * 206 * This is also used in SPP detection. 207 */ 208static int clear_epp_timeout(struct parport *pb) 209{ 210 unsigned char r; 211 212 if (!(parport_pc_read_status(pb) & 0x01)) 213 return 1; 214 215 /* To clear timeout some chips require double read */ 216 parport_pc_read_status(pb); 217 r = parport_pc_read_status(pb); 218 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */ 219 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */ 220 r = parport_pc_read_status(pb); 221 222 return !(r & 0x01); 223} 224 225/* 226 * Access functions. 227 * 228 * Most of these aren't static because they may be used by the 229 * parport_xxx_yyy macros. extern __inline__ versions of several 230 * of these are in parport_pc.h. 231 */ 232 233static void parport_pc_init_state(struct pardevice *dev, 234 struct parport_state *s) 235{ 236 s->u.pc.ctr = 0xc; 237 if (dev->irq_func && 238 dev->port->irq != PARPORT_IRQ_NONE) 239 /* Set ackIntEn */ 240 s->u.pc.ctr |= 0x10; 241 242 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; 243 * D.Gruszka VScom */ 244} 245 246static void parport_pc_save_state(struct parport *p, struct parport_state *s) 247{ 248 const struct parport_pc_private *priv = p->physport->private_data; 249 s->u.pc.ctr = priv->ctr; 250 if (priv->ecr) 251 s->u.pc.ecr = inb(ECONTROL(p)); 252} 253 254static void parport_pc_restore_state(struct parport *p, 255 struct parport_state *s) 256{ 257 struct parport_pc_private *priv = p->physport->private_data; 258 register unsigned char c = s->u.pc.ctr & priv->ctr_writable; 259 outb(c, CONTROL(p)); 260 priv->ctr = c; 261 if (priv->ecr) 262 ECR_WRITE(p, s->u.pc.ecr); 263} 264 265#ifdef CONFIG_PARPORT_1284 266static size_t parport_pc_epp_read_data(struct parport *port, void *buf, 267 size_t length, int flags) 268{ 269 size_t got = 0; 270 271 if (flags & PARPORT_W91284PIC) { 272 unsigned char status; 273 size_t left = length; 274 275 /* use knowledge about data lines..: 276 * nFault is 0 if there is at least 1 byte in the Warp's FIFO 277 * pError is 1 if there are 16 bytes in the Warp's FIFO 278 */ 279 status = inb(STATUS(port)); 280 281 while (!(status & 0x08) && got < length) { 282 if (left >= 16 && (status & 0x20) && !(status & 0x08)) { 283 /* can grab 16 bytes from warp fifo */ 284 if (!((long)buf & 0x03)) 285 insl(EPPDATA(port), buf, 4); 286 else 287 insb(EPPDATA(port), buf, 16); 288 buf += 16; 289 got += 16; 290 left -= 16; 291 } else { 292 /* grab single byte from the warp fifo */ 293 *((char *)buf) = inb(EPPDATA(port)); 294 buf++; 295 got++; 296 left--; 297 } 298 status = inb(STATUS(port)); 299 if (status & 0x01) { 300 /* EPP timeout should never occur... */ 301 printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", 302 port->name); 303 clear_epp_timeout(port); 304 } 305 } 306 return got; 307 } 308 if ((length > 1) && ((flags & PARPORT_EPP_FAST_32) 309 || flags & PARPORT_EPP_FAST_16 310 || flags & PARPORT_EPP_FAST_8)) { 311 if ((flags & PARPORT_EPP_FAST_32) 312 && !(((long)buf | length) & 0x03)) 313 insl(EPPDATA(port), buf, (length >> 2)); 314 else if ((flags & PARPORT_EPP_FAST_16) 315 && !(((long)buf | length) & 0x01)) 316 insw(EPPDATA(port), buf, length >> 1); 317 else 318 insb(EPPDATA(port), buf, length); 319 if (inb(STATUS(port)) & 0x01) { 320 clear_epp_timeout(port); 321 return -EIO; 322 } 323 return length; 324 } 325 for (; got < length; got++) { 326 *((char *)buf) = inb(EPPDATA(port)); 327 buf++; 328 if (inb(STATUS(port)) & 0x01) { 329 /* EPP timeout */ 330 clear_epp_timeout(port); 331 break; 332 } 333 } 334 335 return got; 336} 337 338static size_t parport_pc_epp_write_data(struct parport *port, const void *buf, 339 size_t length, int flags) 340{ 341 size_t written = 0; 342 343 if ((length > 1) && ((flags & PARPORT_EPP_FAST_32) 344 || flags & PARPORT_EPP_FAST_16 345 || flags & PARPORT_EPP_FAST_8)) { 346 if ((flags & PARPORT_EPP_FAST_32) 347 && !(((long)buf | length) & 0x03)) 348 outsl(EPPDATA(port), buf, (length >> 2)); 349 else if ((flags & PARPORT_EPP_FAST_16) 350 && !(((long)buf | length) & 0x01)) 351 outsw(EPPDATA(port), buf, length >> 1); 352 else 353 outsb(EPPDATA(port), buf, length); 354 if (inb(STATUS(port)) & 0x01) { 355 clear_epp_timeout(port); 356 return -EIO; 357 } 358 return length; 359 } 360 for (; written < length; written++) { 361 outb(*((char *)buf), EPPDATA(port)); 362 buf++; 363 if (inb(STATUS(port)) & 0x01) { 364 clear_epp_timeout(port); 365 break; 366 } 367 } 368 369 return written; 370} 371 372static size_t parport_pc_epp_read_addr(struct parport *port, void *buf, 373 size_t length, int flags) 374{ 375 size_t got = 0; 376 377 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 378 insb(EPPADDR(port), buf, length); 379 if (inb(STATUS(port)) & 0x01) { 380 clear_epp_timeout(port); 381 return -EIO; 382 } 383 return length; 384 } 385 for (; got < length; got++) { 386 *((char *)buf) = inb(EPPADDR(port)); 387 buf++; 388 if (inb(STATUS(port)) & 0x01) { 389 clear_epp_timeout(port); 390 break; 391 } 392 } 393 394 return got; 395} 396 397static size_t parport_pc_epp_write_addr(struct parport *port, 398 const void *buf, size_t length, 399 int flags) 400{ 401 size_t written = 0; 402 403 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 404 outsb(EPPADDR(port), buf, length); 405 if (inb(STATUS(port)) & 0x01) { 406 clear_epp_timeout(port); 407 return -EIO; 408 } 409 return length; 410 } 411 for (; written < length; written++) { 412 outb(*((char *)buf), EPPADDR(port)); 413 buf++; 414 if (inb(STATUS(port)) & 0x01) { 415 clear_epp_timeout(port); 416 break; 417 } 418 } 419 420 return written; 421} 422 423static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf, 424 size_t length, int flags) 425{ 426 size_t got; 427 428 frob_set_mode(port, ECR_EPP); 429 parport_pc_data_reverse(port); 430 parport_pc_write_control(port, 0x4); 431 got = parport_pc_epp_read_data(port, buf, length, flags); 432 frob_set_mode(port, ECR_PS2); 433 434 return got; 435} 436 437static size_t parport_pc_ecpepp_write_data(struct parport *port, 438 const void *buf, size_t length, 439 int flags) 440{ 441 size_t written; 442 443 frob_set_mode(port, ECR_EPP); 444 parport_pc_write_control(port, 0x4); 445 parport_pc_data_forward(port); 446 written = parport_pc_epp_write_data(port, buf, length, flags); 447 frob_set_mode(port, ECR_PS2); 448 449 return written; 450} 451 452static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf, 453 size_t length, int flags) 454{ 455 size_t got; 456 457 frob_set_mode(port, ECR_EPP); 458 parport_pc_data_reverse(port); 459 parport_pc_write_control(port, 0x4); 460 got = parport_pc_epp_read_addr(port, buf, length, flags); 461 frob_set_mode(port, ECR_PS2); 462 463 return got; 464} 465 466static size_t parport_pc_ecpepp_write_addr(struct parport *port, 467 const void *buf, size_t length, 468 int flags) 469{ 470 size_t written; 471 472 frob_set_mode(port, ECR_EPP); 473 parport_pc_write_control(port, 0x4); 474 parport_pc_data_forward(port); 475 written = parport_pc_epp_write_addr(port, buf, length, flags); 476 frob_set_mode(port, ECR_PS2); 477 478 return written; 479} 480#endif /* IEEE 1284 support */ 481 482#ifdef CONFIG_PARPORT_PC_FIFO 483static size_t parport_pc_fifo_write_block_pio(struct parport *port, 484 const void *buf, size_t length) 485{ 486 int ret = 0; 487 const unsigned char *bufp = buf; 488 size_t left = length; 489 unsigned long expire = jiffies + port->physport->cad->timeout; 490 const unsigned long fifo = FIFO(port); 491 int poll_for = 8; /* 80 usecs */ 492 const struct parport_pc_private *priv = port->physport->private_data; 493 const int fifo_depth = priv->fifo_depth; 494 495 port = port->physport; 496 497 /* We don't want to be interrupted every character. */ 498 parport_pc_disable_irq(port); 499 /* set nErrIntrEn and serviceIntr */ 500 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 501 502 /* Forward mode. */ 503 parport_pc_data_forward(port); /* Must be in PS2 mode */ 504 505 while (left) { 506 unsigned char byte; 507 unsigned char ecrval = inb(ECONTROL(port)); 508 int i = 0; 509 510 if (need_resched() && time_before(jiffies, expire)) 511 /* Can't yield the port. */ 512 schedule(); 513 514 /* Anyone else waiting for the port? */ 515 if (port->waithead) { 516 printk(KERN_DEBUG "Somebody wants the port\n"); 517 break; 518 } 519 520 if (ecrval & 0x02) { 521 /* FIFO is full. Wait for interrupt. */ 522 523 /* Clear serviceIntr */ 524 ECR_WRITE(port, ecrval & ~(1<<2)); 525false_alarm: 526 ret = parport_wait_event(port, HZ); 527 if (ret < 0) 528 break; 529 ret = 0; 530 if (!time_before(jiffies, expire)) { 531 /* Timed out. */ 532 printk(KERN_DEBUG "FIFO write timed out\n"); 533 break; 534 } 535 ecrval = inb(ECONTROL(port)); 536 if (!(ecrval & (1<<2))) { 537 if (need_resched() && 538 time_before(jiffies, expire)) 539 schedule(); 540 541 goto false_alarm; 542 } 543 544 continue; 545 } 546 547 /* Can't fail now. */ 548 expire = jiffies + port->cad->timeout; 549 550poll: 551 if (signal_pending(current)) 552 break; 553 554 if (ecrval & 0x01) { 555 /* FIFO is empty. Blast it full. */ 556 const int n = left < fifo_depth ? left : fifo_depth; 557 outsb(fifo, bufp, n); 558 bufp += n; 559 left -= n; 560 561 /* Adjust the poll time. */ 562 if (i < (poll_for - 2)) 563 poll_for--; 564 continue; 565 } else if (i++ < poll_for) { 566 udelay(10); 567 ecrval = inb(ECONTROL(port)); 568 goto poll; 569 } 570 571 /* Half-full(call me an optimist) */ 572 byte = *bufp++; 573 outb(byte, fifo); 574 left--; 575 } 576 dump_parport_state("leave fifo_write_block_pio", port); 577 return length - left; 578} 579 580#ifdef HAS_DMA 581static size_t parport_pc_fifo_write_block_dma(struct parport *port, 582 const void *buf, size_t length) 583{ 584 int ret = 0; 585 unsigned long dmaflag; 586 size_t left = length; 587 const struct parport_pc_private *priv = port->physport->private_data; 588 struct device *dev = port->physport->dev; 589 dma_addr_t dma_addr, dma_handle; 590 size_t maxlen = 0x10000; /* max 64k per DMA transfer */ 591 unsigned long start = (unsigned long) buf; 592 unsigned long end = (unsigned long) buf + length - 1; 593 594 dump_parport_state("enter fifo_write_block_dma", port); 595 if (end < MAX_DMA_ADDRESS) { 596 /* If it would cross a 64k boundary, cap it at the end. */ 597 if ((start ^ end) & ~0xffffUL) 598 maxlen = 0x10000 - (start & 0xffff); 599 600 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length, 601 DMA_TO_DEVICE); 602 } else { 603 /* above 16 MB we use a bounce buffer as ISA-DMA 604 is not possible */ 605 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ 606 dma_addr = priv->dma_handle; 607 dma_handle = 0; 608 } 609 610 port = port->physport; 611 612 /* We don't want to be interrupted every character. */ 613 parport_pc_disable_irq(port); 614 /* set nErrIntrEn and serviceIntr */ 615 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 616 617 /* Forward mode. */ 618 parport_pc_data_forward(port); /* Must be in PS2 mode */ 619 620 while (left) { 621 unsigned long expire = jiffies + port->physport->cad->timeout; 622 623 size_t count = left; 624 625 if (count > maxlen) 626 count = maxlen; 627 628 if (!dma_handle) /* bounce buffer ! */ 629 memcpy(priv->dma_buf, buf, count); 630 631 dmaflag = claim_dma_lock(); 632 disable_dma(port->dma); 633 clear_dma_ff(port->dma); 634 set_dma_mode(port->dma, DMA_MODE_WRITE); 635 set_dma_addr(port->dma, dma_addr); 636 set_dma_count(port->dma, count); 637 638 /* Set DMA mode */ 639 frob_econtrol(port, 1<<3, 1<<3); 640 641 /* Clear serviceIntr */ 642 frob_econtrol(port, 1<<2, 0); 643 644 enable_dma(port->dma); 645 release_dma_lock(dmaflag); 646 647 /* assume DMA will be successful */ 648 left -= count; 649 buf += count; 650 if (dma_handle) 651 dma_addr += count; 652 653 /* Wait for interrupt. */ 654false_alarm: 655 ret = parport_wait_event(port, HZ); 656 if (ret < 0) 657 break; 658 ret = 0; 659 if (!time_before(jiffies, expire)) { 660 /* Timed out. */ 661 printk(KERN_DEBUG "DMA write timed out\n"); 662 break; 663 } 664 /* Is serviceIntr set? */ 665 if (!(inb(ECONTROL(port)) & (1<<2))) { 666 cond_resched(); 667 668 goto false_alarm; 669 } 670 671 dmaflag = claim_dma_lock(); 672 disable_dma(port->dma); 673 clear_dma_ff(port->dma); 674 count = get_dma_residue(port->dma); 675 release_dma_lock(dmaflag); 676 677 cond_resched(); /* Can't yield the port. */ 678 679 /* Anyone else waiting for the port? */ 680 if (port->waithead) { 681 printk(KERN_DEBUG "Somebody wants the port\n"); 682 break; 683 } 684 685 /* update for possible DMA residue ! */ 686 buf -= count; 687 left += count; 688 if (dma_handle) 689 dma_addr -= count; 690 } 691 692 /* Maybe got here through break, so adjust for DMA residue! */ 693 dmaflag = claim_dma_lock(); 694 disable_dma(port->dma); 695 clear_dma_ff(port->dma); 696 left += get_dma_residue(port->dma); 697 release_dma_lock(dmaflag); 698 699 /* Turn off DMA mode */ 700 frob_econtrol(port, 1<<3, 0); 701 702 if (dma_handle) 703 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE); 704 705 dump_parport_state("leave fifo_write_block_dma", port); 706 return length - left; 707} 708#endif 709 710static inline size_t parport_pc_fifo_write_block(struct parport *port, 711 const void *buf, size_t length) 712{ 713#ifdef HAS_DMA 714 if (port->dma != PARPORT_DMA_NONE) 715 return parport_pc_fifo_write_block_dma(port, buf, length); 716#endif 717 return parport_pc_fifo_write_block_pio(port, buf, length); 718} 719 720/* Parallel Port FIFO mode (ECP chipsets) */ 721static size_t parport_pc_compat_write_block_pio(struct parport *port, 722 const void *buf, size_t length, 723 int flags) 724{ 725 size_t written; 726 int r; 727 unsigned long expire; 728 const struct parport_pc_private *priv = port->physport->private_data; 729 730 /* Special case: a timeout of zero means we cannot call schedule(). 731 * Also if O_NONBLOCK is set then use the default implementation. */ 732 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 733 return parport_ieee1284_write_compat(port, buf, 734 length, flags); 735 736 /* Set up parallel port FIFO mode.*/ 737 parport_pc_data_forward(port); /* Must be in PS2 mode */ 738 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0); 739 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */ 740 if (r) 741 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", 742 port->name); 743 744 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 745 746 /* Write the data to the FIFO. */ 747 written = parport_pc_fifo_write_block(port, buf, length); 748 749 /* Finish up. */ 750 /* For some hardware we don't want to touch the mode until 751 * the FIFO is empty, so allow 4 seconds for each position 752 * in the fifo. 753 */ 754 expire = jiffies + (priv->fifo_depth * HZ * 4); 755 do { 756 /* Wait for the FIFO to empty */ 757 r = change_mode(port, ECR_PS2); 758 if (r != -EBUSY) 759 break; 760 } while (time_before(jiffies, expire)); 761 if (r == -EBUSY) { 762 763 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); 764 765 /* Prevent further data transfer. */ 766 frob_set_mode(port, ECR_TST); 767 768 /* Adjust for the contents of the FIFO. */ 769 for (written -= priv->fifo_depth; ; written++) { 770 if (inb(ECONTROL(port)) & 0x2) { 771 /* Full up. */ 772 break; 773 } 774 outb(0, FIFO(port)); 775 } 776 777 /* Reset the FIFO and return to PS2 mode. */ 778 frob_set_mode(port, ECR_PS2); 779 } 780 781 r = parport_wait_peripheral(port, 782 PARPORT_STATUS_BUSY, 783 PARPORT_STATUS_BUSY); 784 if (r) 785 printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n", 786 port->name, r); 787 788 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 789 790 return written; 791} 792 793/* ECP */ 794#ifdef CONFIG_PARPORT_1284 795static size_t parport_pc_ecp_write_block_pio(struct parport *port, 796 const void *buf, size_t length, 797 int flags) 798{ 799 size_t written; 800 int r; 801 unsigned long expire; 802 const struct parport_pc_private *priv = port->physport->private_data; 803 804 /* Special case: a timeout of zero means we cannot call schedule(). 805 * Also if O_NONBLOCK is set then use the default implementation. */ 806 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 807 return parport_ieee1284_ecp_write_data(port, buf, 808 length, flags); 809 810 /* Switch to forward mode if necessary. */ 811 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 812 /* Event 47: Set nInit high. */ 813 parport_frob_control(port, 814 PARPORT_CONTROL_INIT 815 | PARPORT_CONTROL_AUTOFD, 816 PARPORT_CONTROL_INIT 817 | PARPORT_CONTROL_AUTOFD); 818 819 /* Event 49: PError goes high. */ 820 r = parport_wait_peripheral(port, 821 PARPORT_STATUS_PAPEROUT, 822 PARPORT_STATUS_PAPEROUT); 823 if (r) { 824 printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n", 825 port->name, r); 826 } 827 } 828 829 /* Set up ECP parallel port mode.*/ 830 parport_pc_data_forward(port); /* Must be in PS2 mode */ 831 parport_pc_frob_control(port, 832 PARPORT_CONTROL_STROBE | 833 PARPORT_CONTROL_AUTOFD, 834 0); 835 r = change_mode(port, ECR_ECP); /* ECP FIFO */ 836 if (r) 837 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", 838 port->name); 839 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 840 841 /* Write the data to the FIFO. */ 842 written = parport_pc_fifo_write_block(port, buf, length); 843 844 /* Finish up. */ 845 /* For some hardware we don't want to touch the mode until 846 * the FIFO is empty, so allow 4 seconds for each position 847 * in the fifo. 848 */ 849 expire = jiffies + (priv->fifo_depth * (HZ * 4)); 850 do { 851 /* Wait for the FIFO to empty */ 852 r = change_mode(port, ECR_PS2); 853 if (r != -EBUSY) 854 break; 855 } while (time_before(jiffies, expire)); 856 if (r == -EBUSY) { 857 858 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); 859 860 /* Prevent further data transfer. */ 861 frob_set_mode(port, ECR_TST); 862 863 /* Adjust for the contents of the FIFO. */ 864 for (written -= priv->fifo_depth; ; written++) { 865 if (inb(ECONTROL(port)) & 0x2) { 866 /* Full up. */ 867 break; 868 } 869 outb(0, FIFO(port)); 870 } 871 872 /* Reset the FIFO and return to PS2 mode. */ 873 frob_set_mode(port, ECR_PS2); 874 875 /* Host transfer recovery. */ 876 parport_pc_data_reverse(port); /* Must be in PS2 mode */ 877 udelay(5); 878 parport_frob_control(port, PARPORT_CONTROL_INIT, 0); 879 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); 880 if (r) 881 printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n", 882 port->name, r); 883 884 parport_frob_control(port, 885 PARPORT_CONTROL_INIT, 886 PARPORT_CONTROL_INIT); 887 r = parport_wait_peripheral(port, 888 PARPORT_STATUS_PAPEROUT, 889 PARPORT_STATUS_PAPEROUT); 890 if (r) 891 printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n", 892 port->name, r); 893 } 894 895 r = parport_wait_peripheral(port, 896 PARPORT_STATUS_BUSY, 897 PARPORT_STATUS_BUSY); 898 if (r) 899 printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n", 900 port->name, r); 901 902 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 903 904 return written; 905} 906#endif /* IEEE 1284 support */ 907#endif /* Allowed to use FIFO/DMA */ 908 909 910/* 911 * ****************************************** 912 * INITIALISATION AND MODULE STUFF BELOW HERE 913 * ****************************************** 914 */ 915 916/* GCC is not inlining extern inline function later overwritten to non-inline, 917 so we use outlined_ variants here. */ 918static const struct parport_operations parport_pc_ops = { 919 .write_data = parport_pc_write_data, 920 .read_data = parport_pc_read_data, 921 922 .write_control = parport_pc_write_control, 923 .read_control = parport_pc_read_control, 924 .frob_control = parport_pc_frob_control, 925 926 .read_status = parport_pc_read_status, 927 928 .enable_irq = parport_pc_enable_irq, 929 .disable_irq = parport_pc_disable_irq, 930 931 .data_forward = parport_pc_data_forward, 932 .data_reverse = parport_pc_data_reverse, 933 934 .init_state = parport_pc_init_state, 935 .save_state = parport_pc_save_state, 936 .restore_state = parport_pc_restore_state, 937 938 .epp_write_data = parport_ieee1284_epp_write_data, 939 .epp_read_data = parport_ieee1284_epp_read_data, 940 .epp_write_addr = parport_ieee1284_epp_write_addr, 941 .epp_read_addr = parport_ieee1284_epp_read_addr, 942 943 .ecp_write_data = parport_ieee1284_ecp_write_data, 944 .ecp_read_data = parport_ieee1284_ecp_read_data, 945 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 946 947 .compat_write_data = parport_ieee1284_write_compat, 948 .nibble_read_data = parport_ieee1284_read_nibble, 949 .byte_read_data = parport_ieee1284_read_byte, 950 951 .owner = THIS_MODULE, 952}; 953 954#ifdef CONFIG_PARPORT_PC_SUPERIO 955 956static struct superio_struct *find_free_superio(void) 957{ 958 int i; 959 for (i = 0; i < NR_SUPERIOS; i++) 960 if (superios[i].io == 0) 961 return &superios[i]; 962 return NULL; 963} 964 965 966/* Super-IO chipset detection, Winbond, SMSC */ 967static void show_parconfig_smsc37c669(int io, int key) 968{ 969 int cr1, cr4, cra, cr23, cr26, cr27; 970 struct superio_struct *s; 971 972 static const char *const modes[] = { 973 "SPP and Bidirectional (PS/2)", 974 "EPP and SPP", 975 "ECP", 976 "ECP and EPP" }; 977 978 outb(key, io); 979 outb(key, io); 980 outb(1, io); 981 cr1 = inb(io + 1); 982 outb(4, io); 983 cr4 = inb(io + 1); 984 outb(0x0a, io); 985 cra = inb(io + 1); 986 outb(0x23, io); 987 cr23 = inb(io + 1); 988 outb(0x26, io); 989 cr26 = inb(io + 1); 990 outb(0x27, io); 991 cr27 = inb(io + 1); 992 outb(0xaa, io); 993 994 if (verbose_probing) { 995 pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", 996 cr1, cr4, cra, cr23, cr26, cr27); 997 998 /* The documentation calls DMA and IRQ-Lines by letters, so 999 the board maker can/will wire them 1000 appropriately/randomly... G=reserved H=IDE-irq, */ 1001 pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", 1002 cr23 * 4, 1003 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', 1004 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', 1005 cra & 0x0f); 1006 pr_info("SMSC LPT Config: enabled=%s power=%s\n", 1007 (cr23 * 4 >= 0x100) ? "yes" : "no", 1008 (cr1 & 4) ? "yes" : "no"); 1009 pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n", 1010 (cr1 & 0x08) ? "Standard mode only (SPP)" 1011 : modes[cr4 & 0x03], 1012 (cr4 & 0x40) ? "1.7" : "1.9"); 1013 } 1014 1015 /* Heuristics ! BIOS setup for this mainboard device limits 1016 the choices to standard settings, i.e. io-address and IRQ 1017 are related, however DMA can be 1 or 3, assume DMA_A=DMA1, 1018 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ 1019 if (cr23 * 4 >= 0x100) { /* if active */ 1020 s = find_free_superio(); 1021 if (s == NULL) 1022 pr_info("Super-IO: too many chips!\n"); 1023 else { 1024 int d; 1025 switch (cr23 * 4) { 1026 case 0x3bc: 1027 s->io = 0x3bc; 1028 s->irq = 7; 1029 break; 1030 case 0x378: 1031 s->io = 0x378; 1032 s->irq = 7; 1033 break; 1034 case 0x278: 1035 s->io = 0x278; 1036 s->irq = 5; 1037 } 1038 d = (cr26 & 0x0f); 1039 if (d == 1 || d == 3) 1040 s->dma = d; 1041 else 1042 s->dma = PARPORT_DMA_NONE; 1043 } 1044 } 1045} 1046 1047 1048static void show_parconfig_winbond(int io, int key) 1049{ 1050 int cr30, cr60, cr61, cr70, cr74, crf0; 1051 struct superio_struct *s; 1052 static const char *const modes[] = { 1053 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ 1054 "EPP-1.9 and SPP", 1055 "ECP", 1056 "ECP and EPP-1.9", 1057 "Standard (SPP)", 1058 "EPP-1.7 and SPP", /* 5 */ 1059 "undefined!", 1060 "ECP and EPP-1.7" }; 1061 static char *const irqtypes[] = { 1062 "pulsed low, high-Z", 1063 "follows nACK" }; 1064 1065 /* The registers are called compatible-PnP because the 1066 register layout is modelled after ISA-PnP, the access 1067 method is just another ... */ 1068 outb(key, io); 1069 outb(key, io); 1070 outb(0x07, io); /* Register 7: Select Logical Device */ 1071 outb(0x01, io + 1); /* LD1 is Parallel Port */ 1072 outb(0x30, io); 1073 cr30 = inb(io + 1); 1074 outb(0x60, io); 1075 cr60 = inb(io + 1); 1076 outb(0x61, io); 1077 cr61 = inb(io + 1); 1078 outb(0x70, io); 1079 cr70 = inb(io + 1); 1080 outb(0x74, io); 1081 cr74 = inb(io + 1); 1082 outb(0xf0, io); 1083 crf0 = inb(io + 1); 1084 outb(0xaa, io); 1085 1086 if (verbose_probing) { 1087 pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", 1088 cr30, cr60, cr61, cr70, cr74, crf0); 1089 pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", 1090 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); 1091 if ((cr74 & 0x07) > 3) 1092 pr_cont("dma=none\n"); 1093 else 1094 pr_cont("dma=%d\n", cr74 & 0x07); 1095 pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", 1096 irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f); 1097 pr_info("Winbond LPT Config: Port mode=%s\n", 1098 modes[crf0 & 0x07]); 1099 } 1100 1101 if (cr30 & 0x01) { /* the settings can be interrogated later ... */ 1102 s = find_free_superio(); 1103 if (s == NULL) 1104 pr_info("Super-IO: too many chips!\n"); 1105 else { 1106 s->io = (cr60 << 8) | cr61; 1107 s->irq = cr70 & 0x0f; 1108 s->dma = (((cr74 & 0x07) > 3) ? 1109 PARPORT_DMA_NONE : (cr74 & 0x07)); 1110 } 1111 } 1112} 1113 1114static void decode_winbond(int efer, int key, int devid, int devrev, int oldid) 1115{ 1116 const char *type = "unknown"; 1117 int id, progif = 2; 1118 1119 if (devid == devrev) 1120 /* simple heuristics, we happened to read some 1121 non-winbond register */ 1122 return; 1123 1124 id = (devid << 8) | devrev; 1125 1126 /* Values are from public data sheets pdf files, I can just 1127 confirm 83977TF is correct :-) */ 1128 if (id == 0x9771) 1129 type = "83977F/AF"; 1130 else if (id == 0x9773) 1131 type = "83977TF / SMSC 97w33x/97w34x"; 1132 else if (id == 0x9774) 1133 type = "83977ATF"; 1134 else if ((id & ~0x0f) == 0x5270) 1135 type = "83977CTF / SMSC 97w36x"; 1136 else if ((id & ~0x0f) == 0x52f0) 1137 type = "83977EF / SMSC 97w35x"; 1138 else if ((id & ~0x0f) == 0x5210) 1139 type = "83627"; 1140 else if ((id & ~0x0f) == 0x6010) 1141 type = "83697HF"; 1142 else if ((oldid & 0x0f) == 0x0a) { 1143 type = "83877F"; 1144 progif = 1; 1145 } else if ((oldid & 0x0f) == 0x0b) { 1146 type = "83877AF"; 1147 progif = 1; 1148 } else if ((oldid & 0x0f) == 0x0c) { 1149 type = "83877TF"; 1150 progif = 1; 1151 } else if ((oldid & 0x0f) == 0x0d) { 1152 type = "83877ATF"; 1153 progif = 1; 1154 } else 1155 progif = 0; 1156 1157 if (verbose_probing) 1158 pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n", 1159 efer, key, devid, devrev, oldid, type); 1160 1161 if (progif == 2) 1162 show_parconfig_winbond(efer, key); 1163} 1164 1165static void decode_smsc(int efer, int key, int devid, int devrev) 1166{ 1167 const char *type = "unknown"; 1168 void (*func)(int io, int key); 1169 int id; 1170 1171 if (devid == devrev) 1172 /* simple heuristics, we happened to read some 1173 non-smsc register */ 1174 return; 1175 1176 func = NULL; 1177 id = (devid << 8) | devrev; 1178 1179 if (id == 0x0302) { 1180 type = "37c669"; 1181 func = show_parconfig_smsc37c669; 1182 } else if (id == 0x6582) 1183 type = "37c665IR"; 1184 else if (devid == 0x65) 1185 type = "37c665GT"; 1186 else if (devid == 0x66) 1187 type = "37c666GT"; 1188 1189 if (verbose_probing) 1190 pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n", 1191 efer, key, devid, devrev, type); 1192 1193 if (func) 1194 func(efer, key); 1195} 1196 1197 1198static void winbond_check(int io, int key) 1199{ 1200 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid; 1201 1202 if (!request_region(io, 3, __func__)) 1203 return; 1204 1205 origval = inb(io); /* Save original value */ 1206 1207 /* First probe without key */ 1208 outb(0x20, io); 1209 x_devid = inb(io + 1); 1210 outb(0x21, io); 1211 x_devrev = inb(io + 1); 1212 outb(0x09, io); 1213 x_oldid = inb(io + 1); 1214 1215 outb(key, io); 1216 outb(key, io); /* Write Magic Sequence to EFER, extended 1217 function enable register */ 1218 outb(0x20, io); /* Write EFIR, extended function index register */ 1219 devid = inb(io + 1); /* Read EFDR, extended function data register */ 1220 outb(0x21, io); 1221 devrev = inb(io + 1); 1222 outb(0x09, io); 1223 oldid = inb(io + 1); 1224 outb(0xaa, io); /* Magic Seal */ 1225 1226 outb(origval, io); /* in case we poked some entirely different hardware */ 1227 1228 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1229 goto out; /* protection against false positives */ 1230 1231 decode_winbond(io, key, devid, devrev, oldid); 1232out: 1233 release_region(io, 3); 1234} 1235 1236static void winbond_check2(int io, int key) 1237{ 1238 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid; 1239 1240 if (!request_region(io, 3, __func__)) 1241 return; 1242 1243 origval[0] = inb(io); /* Save original values */ 1244 origval[1] = inb(io + 1); 1245 origval[2] = inb(io + 2); 1246 1247 /* First probe without the key */ 1248 outb(0x20, io + 2); 1249 x_devid = inb(io + 2); 1250 outb(0x21, io + 1); 1251 x_devrev = inb(io + 2); 1252 outb(0x09, io + 1); 1253 x_oldid = inb(io + 2); 1254 1255 outb(key, io); /* Write Magic Byte to EFER, extended 1256 function enable register */ 1257 outb(0x20, io + 2); /* Write EFIR, extended function index register */ 1258 devid = inb(io + 2); /* Read EFDR, extended function data register */ 1259 outb(0x21, io + 1); 1260 devrev = inb(io + 2); 1261 outb(0x09, io + 1); 1262 oldid = inb(io + 2); 1263 outb(0xaa, io); /* Magic Seal */ 1264 1265 outb(origval[0], io); /* in case we poked some entirely different hardware */ 1266 outb(origval[1], io + 1); 1267 outb(origval[2], io + 2); 1268 1269 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid) 1270 goto out; /* protection against false positives */ 1271 1272 decode_winbond(io, key, devid, devrev, oldid); 1273out: 1274 release_region(io, 3); 1275} 1276 1277static void smsc_check(int io, int key) 1278{ 1279 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev; 1280 1281 if (!request_region(io, 3, __func__)) 1282 return; 1283 1284 origval = inb(io); /* Save original value */ 1285 1286 /* First probe without the key */ 1287 outb(0x0d, io); 1288 x_oldid = inb(io + 1); 1289 outb(0x0e, io); 1290 x_oldrev = inb(io + 1); 1291 outb(0x20, io); 1292 x_id = inb(io + 1); 1293 outb(0x21, io); 1294 x_rev = inb(io + 1); 1295 1296 outb(key, io); 1297 outb(key, io); /* Write Magic Sequence to EFER, extended 1298 function enable register */ 1299 outb(0x0d, io); /* Write EFIR, extended function index register */ 1300 oldid = inb(io + 1); /* Read EFDR, extended function data register */ 1301 outb(0x0e, io); 1302 oldrev = inb(io + 1); 1303 outb(0x20, io); 1304 id = inb(io + 1); 1305 outb(0x21, io); 1306 rev = inb(io + 1); 1307 outb(0xaa, io); /* Magic Seal */ 1308 1309 outb(origval, io); /* in case we poked some entirely different hardware */ 1310 1311 if (x_id == id && x_oldrev == oldrev && 1312 x_oldid == oldid && x_rev == rev) 1313 goto out; /* protection against false positives */ 1314 1315 decode_smsc(io, key, oldid, oldrev); 1316out: 1317 release_region(io, 3); 1318} 1319 1320 1321static void detect_and_report_winbond(void) 1322{ 1323 if (verbose_probing) 1324 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); 1325 winbond_check(0x3f0, 0x87); 1326 winbond_check(0x370, 0x87); 1327 winbond_check(0x2e , 0x87); 1328 winbond_check(0x4e , 0x87); 1329 winbond_check(0x3f0, 0x86); 1330 winbond_check2(0x250, 0x88); 1331 winbond_check2(0x250, 0x89); 1332} 1333 1334static void detect_and_report_smsc(void) 1335{ 1336 if (verbose_probing) 1337 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); 1338 smsc_check(0x3f0, 0x55); 1339 smsc_check(0x370, 0x55); 1340 smsc_check(0x3f0, 0x44); 1341 smsc_check(0x370, 0x44); 1342} 1343 1344static void detect_and_report_it87(void) 1345{ 1346 u16 dev; 1347 u8 origval, r; 1348 if (verbose_probing) 1349 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n"); 1350 if (!request_muxed_region(0x2e, 2, __func__)) 1351 return; 1352 origval = inb(0x2e); /* Save original value */ 1353 outb(0x87, 0x2e); 1354 outb(0x01, 0x2e); 1355 outb(0x55, 0x2e); 1356 outb(0x55, 0x2e); 1357 outb(0x20, 0x2e); 1358 dev = inb(0x2f) << 8; 1359 outb(0x21, 0x2e); 1360 dev |= inb(0x2f); 1361 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || 1362 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { 1363 pr_info("IT%04X SuperIO detected\n", dev); 1364 outb(0x07, 0x2E); /* Parallel Port */ 1365 outb(0x03, 0x2F); 1366 outb(0xF0, 0x2E); /* BOOT 0x80 off */ 1367 r = inb(0x2f); 1368 outb(0xF0, 0x2E); 1369 outb(r | 8, 0x2F); 1370 outb(0x02, 0x2E); /* Lock */ 1371 outb(0x02, 0x2F); 1372 } else { 1373 outb(origval, 0x2e); /* Oops, sorry to disturb */ 1374 } 1375 release_region(0x2e, 2); 1376} 1377#endif /* CONFIG_PARPORT_PC_SUPERIO */ 1378 1379static struct superio_struct *find_superio(struct parport *p) 1380{ 1381 int i; 1382 for (i = 0; i < NR_SUPERIOS; i++) 1383 if (superios[i].io == p->base) 1384 return &superios[i]; 1385 return NULL; 1386} 1387 1388static int get_superio_dma(struct parport *p) 1389{ 1390 struct superio_struct *s = find_superio(p); 1391 if (s) 1392 return s->dma; 1393 return PARPORT_DMA_NONE; 1394} 1395 1396static int get_superio_irq(struct parport *p) 1397{ 1398 struct superio_struct *s = find_superio(p); 1399 if (s) 1400 return s->irq; 1401 return PARPORT_IRQ_NONE; 1402} 1403 1404 1405/* --- Mode detection ------------------------------------- */ 1406 1407/* 1408 * Checks for port existence, all ports support SPP MODE 1409 * Returns: 1410 * 0 : No parallel port at this address 1411 * PARPORT_MODE_PCSPP : SPP port detected 1412 * (if the user specified an ioport himself, 1413 * this shall always be the case!) 1414 * 1415 */ 1416static int parport_SPP_supported(struct parport *pb) 1417{ 1418 unsigned char r, w; 1419 1420 /* 1421 * first clear an eventually pending EPP timeout 1422 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset 1423 * that does not even respond to SPP cycles if an EPP 1424 * timeout is pending 1425 */ 1426 clear_epp_timeout(pb); 1427 1428 /* Do a simple read-write test to make sure the port exists. */ 1429 w = 0xc; 1430 outb(w, CONTROL(pb)); 1431 1432 /* Is there a control register that we can read from? Some 1433 * ports don't allow reads, so read_control just returns a 1434 * software copy. Some ports _do_ allow reads, so bypass the 1435 * software copy here. In addition, some bits aren't 1436 * writable. */ 1437 r = inb(CONTROL(pb)); 1438 if ((r & 0xf) == w) { 1439 w = 0xe; 1440 outb(w, CONTROL(pb)); 1441 r = inb(CONTROL(pb)); 1442 outb(0xc, CONTROL(pb)); 1443 if ((r & 0xf) == w) 1444 return PARPORT_MODE_PCSPP; 1445 } 1446 1447 if (user_specified) 1448 /* That didn't work, but the user thinks there's a 1449 * port here. */ 1450 pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n", 1451 pb->base, w, r); 1452 1453 /* Try the data register. The data lines aren't tri-stated at 1454 * this stage, so we expect back what we wrote. */ 1455 w = 0xaa; 1456 parport_pc_write_data(pb, w); 1457 r = parport_pc_read_data(pb); 1458 if (r == w) { 1459 w = 0x55; 1460 parport_pc_write_data(pb, w); 1461 r = parport_pc_read_data(pb); 1462 if (r == w) 1463 return PARPORT_MODE_PCSPP; 1464 } 1465 1466 if (user_specified) { 1467 /* Didn't work, but the user is convinced this is the 1468 * place. */ 1469 pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n", 1470 pb->base, w, r); 1471 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n", 1472 pb->base); 1473 } 1474 1475 /* It's possible that we can't read the control register or 1476 * the data register. In that case just believe the user. */ 1477 if (user_specified) 1478 return PARPORT_MODE_PCSPP; 1479 1480 return 0; 1481} 1482 1483/* Check for ECR 1484 * 1485 * Old style XT ports alias io ports every 0x400, hence accessing ECR 1486 * on these cards actually accesses the CTR. 1487 * 1488 * Modern cards don't do this but reading from ECR will return 0xff 1489 * regardless of what is written here if the card does NOT support 1490 * ECP. 1491 * 1492 * We first check to see if ECR is the same as CTR. If not, the low 1493 * two bits of ECR aren't writable, so we check by writing ECR and 1494 * reading it back to see if it's what we expect. 1495 */ 1496static int parport_ECR_present(struct parport *pb) 1497{ 1498 struct parport_pc_private *priv = pb->private_data; 1499 unsigned char r = 0xc; 1500 1501 if (!priv->ecr_writable) { 1502 outb(r, CONTROL(pb)); 1503 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { 1504 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ 1505 1506 r = inb(CONTROL(pb)); 1507 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) 1508 /* Sure that no ECR register exists */ 1509 goto no_reg; 1510 } 1511 1512 if ((inb(ECONTROL(pb)) & 0x3) != 0x1) 1513 goto no_reg; 1514 1515 ECR_WRITE(pb, 0x34); 1516 if (inb(ECONTROL(pb)) != 0x35) 1517 goto no_reg; 1518 } 1519 1520 priv->ecr = 1; 1521 outb(0xc, CONTROL(pb)); 1522 1523 /* Go to mode 000 */ 1524 frob_set_mode(pb, ECR_SPP); 1525 1526 return 1; 1527 1528 no_reg: 1529 outb(0xc, CONTROL(pb)); 1530 return 0; 1531} 1532 1533#ifdef CONFIG_PARPORT_1284 1534/* Detect PS/2 support. 1535 * 1536 * Bit 5 (0x20) sets the PS/2 data direction; setting this high 1537 * allows us to read data from the data lines. In theory we would get back 1538 * 0xff but any peripheral attached to the port may drag some or all of the 1539 * lines down to zero. So if we get back anything that isn't the contents 1540 * of the data register we deem PS/2 support to be present. 1541 * 1542 * Some SPP ports have "half PS/2" ability - you can't turn off the line 1543 * drivers, but an external peripheral with sufficiently beefy drivers of 1544 * its own can overpower them and assert its own levels onto the bus, from 1545 * where they can then be read back as normal. Ports with this property 1546 * and the right type of device attached are likely to fail the SPP test, 1547 * (as they will appear to have stuck bits) and so the fact that they might 1548 * be misdetected here is rather academic. 1549 */ 1550 1551static int parport_PS2_supported(struct parport *pb) 1552{ 1553 int ok = 0; 1554 1555 clear_epp_timeout(pb); 1556 1557 /* try to tri-state the buffer */ 1558 parport_pc_data_reverse(pb); 1559 1560 parport_pc_write_data(pb, 0x55); 1561 if (parport_pc_read_data(pb) != 0x55) 1562 ok++; 1563 1564 parport_pc_write_data(pb, 0xaa); 1565 if (parport_pc_read_data(pb) != 0xaa) 1566 ok++; 1567 1568 /* cancel input mode */ 1569 parport_pc_data_forward(pb); 1570 1571 if (ok) { 1572 pb->modes |= PARPORT_MODE_TRISTATE; 1573 } else { 1574 struct parport_pc_private *priv = pb->private_data; 1575 priv->ctr_writable &= ~0x20; 1576 } 1577 1578 return ok; 1579} 1580 1581#ifdef CONFIG_PARPORT_PC_FIFO 1582static int parport_ECP_supported(struct parport *pb) 1583{ 1584 int i; 1585 int config, configb; 1586 int pword; 1587 struct parport_pc_private *priv = pb->private_data; 1588 /* Translate ECP intrLine to ISA irq value */ 1589 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 }; 1590 1591 /* If there is no ECR, we have no hope of supporting ECP. */ 1592 if (!priv->ecr) 1593 return 0; 1594 1595 /* Find out FIFO depth */ 1596 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ 1597 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */ 1598 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++) 1599 outb(0xaa, FIFO(pb)); 1600 1601 /* 1602 * Using LGS chipset it uses ECR register, but 1603 * it doesn't support ECP or FIFO MODE 1604 */ 1605 if (i == 1024) { 1606 ECR_WRITE(pb, ECR_SPP << 5); 1607 return 0; 1608 } 1609 1610 priv->fifo_depth = i; 1611 if (verbose_probing) 1612 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); 1613 1614 /* Find out writeIntrThreshold */ 1615 frob_econtrol(pb, 1<<2, 1<<2); 1616 frob_econtrol(pb, 1<<2, 0); 1617 for (i = 1; i <= priv->fifo_depth; i++) { 1618 inb(FIFO(pb)); 1619 udelay(50); 1620 if (inb(ECONTROL(pb)) & (1<<2)) 1621 break; 1622 } 1623 1624 if (i <= priv->fifo_depth) { 1625 if (verbose_probing) 1626 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", 1627 pb->base, i); 1628 } else 1629 /* Number of bytes we know we can write if we get an 1630 interrupt. */ 1631 i = 0; 1632 1633 priv->writeIntrThreshold = i; 1634 1635 /* Find out readIntrThreshold */ 1636 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */ 1637 parport_pc_data_reverse(pb); /* Must be in PS2 mode */ 1638 frob_set_mode(pb, ECR_TST); /* Test FIFO */ 1639 frob_econtrol(pb, 1<<2, 1<<2); 1640 frob_econtrol(pb, 1<<2, 0); 1641 for (i = 1; i <= priv->fifo_depth; i++) { 1642 outb(0xaa, FIFO(pb)); 1643 if (inb(ECONTROL(pb)) & (1<<2)) 1644 break; 1645 } 1646 1647 if (i <= priv->fifo_depth) { 1648 if (verbose_probing) 1649 pr_info("0x%lx: readIntrThreshold is %d\n", 1650 pb->base, i); 1651 } else 1652 /* Number of bytes we can read if we get an interrupt. */ 1653 i = 0; 1654 1655 priv->readIntrThreshold = i; 1656 1657 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ 1658 ECR_WRITE(pb, 0xf4); /* Configuration mode */ 1659 config = inb(CONFIGA(pb)); 1660 pword = (config >> 4) & 0x7; 1661 switch (pword) { 1662 case 0: 1663 pword = 2; 1664 pr_warn("0x%lx: Unsupported pword size!\n", pb->base); 1665 break; 1666 case 2: 1667 pword = 4; 1668 pr_warn("0x%lx: Unsupported pword size!\n", pb->base); 1669 break; 1670 default: 1671 pr_warn("0x%lx: Unknown implementation ID\n", pb->base); 1672 fallthrough; /* Assume 1 */ 1673 case 1: 1674 pword = 1; 1675 } 1676 priv->pword = pword; 1677 1678 if (verbose_probing) { 1679 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", 1680 pb->base, 8 * pword); 1681 1682 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", 1683 pb->base, config & 0x80 ? "Level" : "Pulses"); 1684 1685 configb = inb(CONFIGB(pb)); 1686 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", 1687 pb->base, config, configb); 1688 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); 1689 if ((configb >> 3) & 0x07) 1690 pr_cont("%d", intrline[(configb >> 3) & 0x07]); 1691 else 1692 pr_cont("<none or set by other means>"); 1693 pr_cont(" dma="); 1694 if ((configb & 0x03) == 0x00) 1695 pr_cont("<none or set by other means>\n"); 1696 else 1697 pr_cont("%d\n", configb & 0x07); 1698 } 1699 1700 /* Go back to mode 000 */ 1701 frob_set_mode(pb, ECR_SPP); 1702 1703 return 1; 1704} 1705#endif 1706 1707#ifdef CONFIG_X86_32 1708static int intel_bug_present_check_epp(struct parport *pb) 1709{ 1710 const struct parport_pc_private *priv = pb->private_data; 1711 int bug_present = 0; 1712 1713 if (priv->ecr) { 1714 /* store value of ECR */ 1715 unsigned char ecr = inb(ECONTROL(pb)); 1716 unsigned char i; 1717 for (i = 0x00; i < 0x80; i += 0x20) { 1718 ECR_WRITE(pb, i); 1719 if (clear_epp_timeout(pb)) { 1720 /* Phony EPP in ECP. */ 1721 bug_present = 1; 1722 break; 1723 } 1724 } 1725 /* return ECR into the inital state */ 1726 ECR_WRITE(pb, ecr); 1727 } 1728 1729 return bug_present; 1730} 1731static int intel_bug_present(struct parport *pb) 1732{ 1733/* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */ 1734 if (pb->dev != NULL) { 1735 return 0; 1736 } 1737 1738 return intel_bug_present_check_epp(pb); 1739} 1740#else 1741static int intel_bug_present(struct parport *pb) 1742{ 1743 return 0; 1744} 1745#endif /* CONFIG_X86_32 */ 1746 1747static int parport_ECPPS2_supported(struct parport *pb) 1748{ 1749 const struct parport_pc_private *priv = pb->private_data; 1750 int result; 1751 unsigned char oecr; 1752 1753 if (!priv->ecr) 1754 return 0; 1755 1756 oecr = inb(ECONTROL(pb)); 1757 ECR_WRITE(pb, ECR_PS2 << 5); 1758 result = parport_PS2_supported(pb); 1759 ECR_WRITE(pb, oecr); 1760 return result; 1761} 1762 1763/* EPP mode detection */ 1764 1765static int parport_EPP_supported(struct parport *pb) 1766{ 1767 /* 1768 * Theory: 1769 * Bit 0 of STR is the EPP timeout bit, this bit is 0 1770 * when EPP is possible and is set high when an EPP timeout 1771 * occurs (EPP uses the HALT line to stop the CPU while it does 1772 * the byte transfer, an EPP timeout occurs if the attached 1773 * device fails to respond after 10 micro seconds). 1774 * 1775 * This bit is cleared by either reading it (National Semi) 1776 * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? 1777 * This bit is always high in non EPP modes. 1778 */ 1779 1780 /* If EPP timeout bit clear then EPP available */ 1781 if (!clear_epp_timeout(pb)) 1782 return 0; /* No way to clear timeout */ 1783 1784 /* Check for Intel bug. */ 1785 if (intel_bug_present(pb)) 1786 return 0; 1787 1788 pb->modes |= PARPORT_MODE_EPP; 1789 1790 /* Set up access functions to use EPP hardware. */ 1791 pb->ops->epp_read_data = parport_pc_epp_read_data; 1792 pb->ops->epp_write_data = parport_pc_epp_write_data; 1793 pb->ops->epp_read_addr = parport_pc_epp_read_addr; 1794 pb->ops->epp_write_addr = parport_pc_epp_write_addr; 1795 1796 return 1; 1797} 1798 1799static int parport_ECPEPP_supported(struct parport *pb) 1800{ 1801 struct parport_pc_private *priv = pb->private_data; 1802 int result; 1803 unsigned char oecr; 1804 1805 if (!priv->ecr) 1806 return 0; 1807 1808 oecr = inb(ECONTROL(pb)); 1809 /* Search for SMC style EPP+ECP mode */ 1810 ECR_WRITE(pb, 0x80); 1811 outb(0x04, CONTROL(pb)); 1812 result = parport_EPP_supported(pb); 1813 1814 ECR_WRITE(pb, oecr); 1815 1816 if (result) { 1817 /* Set up access functions to use ECP+EPP hardware. */ 1818 pb->ops->epp_read_data = parport_pc_ecpepp_read_data; 1819 pb->ops->epp_write_data = parport_pc_ecpepp_write_data; 1820 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; 1821 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; 1822 } 1823 1824 return result; 1825} 1826 1827#else /* No IEEE 1284 support */ 1828 1829/* Don't bother probing for modes we know we won't use. */ 1830static int parport_PS2_supported(struct parport *pb) { return 0; } 1831#ifdef CONFIG_PARPORT_PC_FIFO 1832static int parport_ECP_supported(struct parport *pb) 1833{ 1834 return 0; 1835} 1836#endif 1837static int parport_EPP_supported(struct parport *pb) 1838{ 1839 return 0; 1840} 1841 1842static int parport_ECPEPP_supported(struct parport *pb) 1843{ 1844 return 0; 1845} 1846 1847static int parport_ECPPS2_supported(struct parport *pb) 1848{ 1849 return 0; 1850} 1851 1852#endif /* No IEEE 1284 support */ 1853 1854/* --- IRQ detection -------------------------------------- */ 1855 1856/* Only if supports ECP mode */ 1857static int programmable_irq_support(struct parport *pb) 1858{ 1859 int irq, intrLine; 1860 unsigned char oecr = inb(ECONTROL(pb)); 1861 static const int lookup[8] = { 1862 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 1863 }; 1864 1865 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */ 1866 1867 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07; 1868 irq = lookup[intrLine]; 1869 1870 ECR_WRITE(pb, oecr); 1871 return irq; 1872} 1873 1874static int irq_probe_ECP(struct parport *pb) 1875{ 1876 int i; 1877 unsigned long irqs; 1878 1879 irqs = probe_irq_on(); 1880 1881 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ 1882 ECR_WRITE(pb, (ECR_TST << 5) | 0x04); 1883 ECR_WRITE(pb, ECR_TST << 5); 1884 1885 /* If Full FIFO sure that writeIntrThreshold is generated */ 1886 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++) 1887 outb(0xaa, FIFO(pb)); 1888 1889 pb->irq = probe_irq_off(irqs); 1890 ECR_WRITE(pb, ECR_SPP << 5); 1891 1892 if (pb->irq <= 0) 1893 pb->irq = PARPORT_IRQ_NONE; 1894 1895 return pb->irq; 1896} 1897 1898/* 1899 * This detection seems that only works in National Semiconductors 1900 * This doesn't work in SMC, LGS, and Winbond 1901 */ 1902static int irq_probe_EPP(struct parport *pb) 1903{ 1904#ifndef ADVANCED_DETECT 1905 return PARPORT_IRQ_NONE; 1906#else 1907 int irqs; 1908 unsigned char oecr; 1909 1910 if (pb->modes & PARPORT_MODE_PCECR) 1911 oecr = inb(ECONTROL(pb)); 1912 1913 irqs = probe_irq_on(); 1914 1915 if (pb->modes & PARPORT_MODE_PCECR) 1916 frob_econtrol(pb, 0x10, 0x10); 1917 1918 clear_epp_timeout(pb); 1919 parport_pc_frob_control(pb, 0x20, 0x20); 1920 parport_pc_frob_control(pb, 0x10, 0x10); 1921 clear_epp_timeout(pb); 1922 1923 /* Device isn't expecting an EPP read 1924 * and generates an IRQ. 1925 */ 1926 parport_pc_read_epp(pb); 1927 udelay(20); 1928 1929 pb->irq = probe_irq_off(irqs); 1930 if (pb->modes & PARPORT_MODE_PCECR) 1931 ECR_WRITE(pb, oecr); 1932 parport_pc_write_control(pb, 0xc); 1933 1934 if (pb->irq <= 0) 1935 pb->irq = PARPORT_IRQ_NONE; 1936 1937 return pb->irq; 1938#endif /* Advanced detection */ 1939} 1940 1941static int irq_probe_SPP(struct parport *pb) 1942{ 1943 /* Don't even try to do this. */ 1944 return PARPORT_IRQ_NONE; 1945} 1946 1947/* We will attempt to share interrupt requests since other devices 1948 * such as sound cards and network cards seem to like using the 1949 * printer IRQs. 1950 * 1951 * When ECP is available we can autoprobe for IRQs. 1952 * NOTE: If we can autoprobe it, we can register the IRQ. 1953 */ 1954static int parport_irq_probe(struct parport *pb) 1955{ 1956 struct parport_pc_private *priv = pb->private_data; 1957 1958 if (priv->ecr) { 1959 pb->irq = programmable_irq_support(pb); 1960 1961 if (pb->irq == PARPORT_IRQ_NONE) 1962 pb->irq = irq_probe_ECP(pb); 1963 } 1964 1965 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && 1966 (pb->modes & PARPORT_MODE_EPP)) 1967 pb->irq = irq_probe_EPP(pb); 1968 1969 clear_epp_timeout(pb); 1970 1971 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) 1972 pb->irq = irq_probe_EPP(pb); 1973 1974 clear_epp_timeout(pb); 1975 1976 if (pb->irq == PARPORT_IRQ_NONE) 1977 pb->irq = irq_probe_SPP(pb); 1978 1979 if (pb->irq == PARPORT_IRQ_NONE) 1980 pb->irq = get_superio_irq(pb); 1981 1982 return pb->irq; 1983} 1984 1985/* --- DMA detection -------------------------------------- */ 1986 1987/* Only if chipset conforms to ECP ISA Interface Standard */ 1988static int programmable_dma_support(struct parport *p) 1989{ 1990 unsigned char oecr = inb(ECONTROL(p)); 1991 int dma; 1992 1993 frob_set_mode(p, ECR_CNF); 1994 1995 dma = inb(CONFIGB(p)) & 0x07; 1996 /* 000: Indicates jumpered 8-bit DMA if read-only. 1997 100: Indicates jumpered 16-bit DMA if read-only. */ 1998 if ((dma & 0x03) == 0) 1999 dma = PARPORT_DMA_NONE; 2000 2001 ECR_WRITE(p, oecr); 2002 return dma; 2003} 2004 2005static int parport_dma_probe(struct parport *p) 2006{ 2007 const struct parport_pc_private *priv = p->private_data; 2008 if (priv->ecr) /* ask ECP chipset first */ 2009 p->dma = programmable_dma_support(p); 2010 if (p->dma == PARPORT_DMA_NONE) { 2011 /* ask known Super-IO chips proper, although these 2012 claim ECP compatible, some don't report their DMA 2013 conforming to ECP standards */ 2014 p->dma = get_superio_dma(p); 2015 } 2016 2017 return p->dma; 2018} 2019 2020/* --- Initialisation code -------------------------------- */ 2021 2022static LIST_HEAD(ports_list); 2023static DEFINE_SPINLOCK(ports_lock); 2024 2025static struct parport *__parport_pc_probe_port(unsigned long int base, 2026 unsigned long int base_hi, 2027 int irq, int dma, 2028 struct device *dev, 2029 int irqflags, 2030 unsigned int mode_mask, 2031 unsigned char ecr_writable) 2032{ 2033 struct parport_pc_private *priv; 2034 struct parport_operations *ops; 2035 struct parport *p; 2036 int probedirq = PARPORT_IRQ_NONE; 2037 struct resource *base_res; 2038 struct resource *ECR_res = NULL; 2039 struct resource *EPP_res = NULL; 2040 struct platform_device *pdev = NULL; 2041 int ret; 2042 2043 if (!dev) { 2044 /* We need a physical device to attach to, but none was 2045 * provided. Create our own. */ 2046 pdev = platform_device_register_simple("parport_pc", 2047 base, NULL, 0); 2048 if (IS_ERR(pdev)) 2049 return NULL; 2050 dev = &pdev->dev; 2051 2052 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24)); 2053 if (ret) { 2054 dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n"); 2055 dma = PARPORT_DMA_NONE; 2056 } 2057 } 2058 2059 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); 2060 if (!ops) 2061 goto out1; 2062 2063 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL); 2064 if (!priv) 2065 goto out2; 2066 2067 /* a misnomer, actually - it's allocate and reserve parport number */ 2068 p = parport_register_port(base, irq, dma, ops); 2069 if (!p) 2070 goto out3; 2071 2072 base_res = request_region(base, 3, p->name); 2073 if (!base_res) 2074 goto out4; 2075 2076 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations)); 2077 priv->ctr = 0xc; 2078 priv->ctr_writable = ~0x10; 2079 priv->ecr = 0; 2080 priv->ecr_writable = ecr_writable; 2081 priv->fifo_depth = 0; 2082 priv->dma_buf = NULL; 2083 priv->dma_handle = 0; 2084 INIT_LIST_HEAD(&priv->list); 2085 priv->port = p; 2086 2087 p->dev = dev; 2088 p->base_hi = base_hi; 2089 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2090 p->private_data = priv; 2091 2092 if (base_hi) { 2093 ECR_res = request_region(base_hi, 3, p->name); 2094 if (ECR_res) 2095 parport_ECR_present(p); 2096 } 2097 2098 if (base != 0x3bc) { 2099 EPP_res = request_region(base+0x3, 5, p->name); 2100 if (EPP_res) 2101 if (!parport_EPP_supported(p)) 2102 parport_ECPEPP_supported(p); 2103 } 2104 if (!parport_SPP_supported(p)) 2105 /* No port. */ 2106 goto out5; 2107 if (priv->ecr) 2108 parport_ECPPS2_supported(p); 2109 else 2110 parport_PS2_supported(p); 2111 2112 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3; 2113 2114 pr_info("%s: PC-style at 0x%lx", p->name, p->base); 2115 if (p->base_hi && priv->ecr) 2116 pr_cont(" (0x%lx)", p->base_hi); 2117 if (p->irq == PARPORT_IRQ_AUTO) { 2118 p->irq = PARPORT_IRQ_NONE; 2119 parport_irq_probe(p); 2120 } else if (p->irq == PARPORT_IRQ_PROBEONLY) { 2121 p->irq = PARPORT_IRQ_NONE; 2122 parport_irq_probe(p); 2123 probedirq = p->irq; 2124 p->irq = PARPORT_IRQ_NONE; 2125 } 2126 if (p->irq != PARPORT_IRQ_NONE) { 2127 pr_cont(", irq %d", p->irq); 2128 priv->ctr_writable |= 0x10; 2129 2130 if (p->dma == PARPORT_DMA_AUTO) { 2131 p->dma = PARPORT_DMA_NONE; 2132 parport_dma_probe(p); 2133 } 2134 } 2135 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq 2136 is mandatory (see above) */ 2137 p->dma = PARPORT_DMA_NONE; 2138 2139#ifdef CONFIG_PARPORT_PC_FIFO 2140 if (parport_ECP_supported(p) && 2141 p->dma != PARPORT_DMA_NOFIFO && 2142 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { 2143 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; 2144 if (p->dma != PARPORT_DMA_NONE) 2145 p->modes |= PARPORT_MODE_DMA; 2146 } else 2147 /* We can't use the DMA channel after all. */ 2148 p->dma = PARPORT_DMA_NONE; 2149#endif /* Allowed to use FIFO/DMA */ 2150 2151 p->modes &= ~mode_mask; 2152 2153#ifdef CONFIG_PARPORT_PC_FIFO 2154 if ((p->modes & PARPORT_MODE_COMPAT) != 0) 2155 p->ops->compat_write_data = parport_pc_compat_write_block_pio; 2156#ifdef CONFIG_PARPORT_1284 2157 if ((p->modes & PARPORT_MODE_ECP) != 0) 2158 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; 2159#endif 2160 if ((p->modes & (PARPORT_MODE_ECP | PARPORT_MODE_COMPAT)) != 0) { 2161 if ((p->modes & PARPORT_MODE_DMA) != 0) 2162 pr_cont(", dma %d", p->dma); 2163 else 2164 pr_cont(", using FIFO"); 2165 } 2166#endif /* Allowed to use FIFO/DMA */ 2167 2168 pr_cont(" ["); 2169 2170#define printmode(x) \ 2171do { \ 2172 if (p->modes & PARPORT_MODE_##x) \ 2173 pr_cont("%s%s", f++ ? "," : "", #x); \ 2174} while (0) 2175 2176 { 2177 int f = 0; 2178 printmode(PCSPP); 2179 printmode(TRISTATE); 2180 printmode(COMPAT); 2181 printmode(EPP); 2182 printmode(ECP); 2183 printmode(DMA); 2184 } 2185#undef printmode 2186#ifndef CONFIG_PARPORT_1284 2187 pr_cont("(,...)"); 2188#endif /* CONFIG_PARPORT_1284 */ 2189 pr_cont("]\n"); 2190 if (probedirq != PARPORT_IRQ_NONE) 2191 pr_info("%s: irq %d detected\n", p->name, probedirq); 2192 2193 /* If No ECP release the ports grabbed above. */ 2194 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { 2195 release_region(base_hi, 3); 2196 ECR_res = NULL; 2197 } 2198 /* Likewise for EEP ports */ 2199 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { 2200 release_region(base+3, 5); 2201 EPP_res = NULL; 2202 } 2203 if (p->irq != PARPORT_IRQ_NONE) { 2204 if (request_irq(p->irq, parport_irq_handler, 2205 irqflags, p->name, p)) { 2206 pr_warn("%s: irq %d in use, resorting to polled operation\n", 2207 p->name, p->irq); 2208 p->irq = PARPORT_IRQ_NONE; 2209 p->dma = PARPORT_DMA_NONE; 2210 } 2211 2212#ifdef CONFIG_PARPORT_PC_FIFO 2213#ifdef HAS_DMA 2214 if (p->dma != PARPORT_DMA_NONE) { 2215 if (request_dma(p->dma, p->name)) { 2216 pr_warn("%s: dma %d in use, resorting to PIO operation\n", 2217 p->name, p->dma); 2218 p->dma = PARPORT_DMA_NONE; 2219 } else { 2220 priv->dma_buf = 2221 dma_alloc_coherent(dev, 2222 PAGE_SIZE, 2223 &priv->dma_handle, 2224 GFP_KERNEL); 2225 if (!priv->dma_buf) { 2226 pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n", 2227 p->name); 2228 free_dma(p->dma); 2229 p->dma = PARPORT_DMA_NONE; 2230 } 2231 } 2232 } 2233#endif 2234#endif 2235 } 2236 2237 /* Done probing. Now put the port into a sensible start-up state. */ 2238 if (priv->ecr) 2239 /* 2240 * Put the ECP detected port in PS2 mode. 2241 * Do this also for ports that have ECR but don't do ECP. 2242 */ 2243 ECR_WRITE(p, 0x34); 2244 2245 parport_pc_write_data(p, 0); 2246 parport_pc_data_forward(p); 2247 2248 /* Now that we've told the sharing engine about the port, and 2249 found out its characteristics, let the high-level drivers 2250 know about it. */ 2251 spin_lock(&ports_lock); 2252 list_add(&priv->list, &ports_list); 2253 spin_unlock(&ports_lock); 2254 parport_announce_port(p); 2255 2256 return p; 2257 2258out5: 2259 if (ECR_res) 2260 release_region(base_hi, 3); 2261 if (EPP_res) 2262 release_region(base+0x3, 5); 2263 release_region(base, 3); 2264out4: 2265 parport_del_port(p); 2266out3: 2267 kfree(priv); 2268out2: 2269 kfree(ops); 2270out1: 2271 if (pdev) 2272 platform_device_unregister(pdev); 2273 return NULL; 2274} 2275 2276struct parport *parport_pc_probe_port(unsigned long int base, 2277 unsigned long int base_hi, 2278 int irq, int dma, 2279 struct device *dev, 2280 int irqflags) 2281{ 2282 return __parport_pc_probe_port(base, base_hi, irq, dma, 2283 dev, irqflags, 0, 0); 2284} 2285EXPORT_SYMBOL(parport_pc_probe_port); 2286 2287void parport_pc_unregister_port(struct parport *p) 2288{ 2289 struct parport_pc_private *priv = p->private_data; 2290 struct parport_operations *ops = p->ops; 2291 2292 parport_remove_port(p); 2293 spin_lock(&ports_lock); 2294 list_del_init(&priv->list); 2295 spin_unlock(&ports_lock); 2296#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2297 if (p->dma != PARPORT_DMA_NONE) 2298 free_dma(p->dma); 2299#endif 2300 if (p->irq != PARPORT_IRQ_NONE) 2301 free_irq(p->irq, p); 2302 release_region(p->base, 3); 2303 if (p->size > 3) 2304 release_region(p->base + 3, p->size - 3); 2305 if (p->modes & PARPORT_MODE_ECP) 2306 release_region(p->base_hi, 3); 2307#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2308 if (priv->dma_buf) 2309 dma_free_coherent(p->physport->dev, PAGE_SIZE, 2310 priv->dma_buf, 2311 priv->dma_handle); 2312#endif 2313 kfree(p->private_data); 2314 parport_del_port(p); 2315 kfree(ops); /* hope no-one cached it */ 2316} 2317EXPORT_SYMBOL(parport_pc_unregister_port); 2318 2319#ifdef CONFIG_PCI 2320 2321/* ITE support maintained by Rich Liu <richliu@poorman.org> */ 2322static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, 2323 const struct parport_pc_via_data *via) 2324{ 2325 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; 2326 u32 ite8872set; 2327 u32 ite8872_lpt, ite8872_lpthi; 2328 u8 ite8872_irq, type; 2329 int irq; 2330 int i; 2331 2332 pr_debug("sio_ite_8872_probe()\n"); 2333 2334 /* make sure which one chip */ 2335 for (i = 0; i < 5; i++) { 2336 if (request_region(inta_addr[i], 32, "it887x")) { 2337 int test; 2338 pci_write_config_dword(pdev, 0x60, 2339 0xe5000000 | inta_addr[i]); 2340 pci_write_config_dword(pdev, 0x78, 2341 0x00000000 | inta_addr[i]); 2342 test = inb(inta_addr[i]); 2343 if (test != 0xff) 2344 break; 2345 release_region(inta_addr[i], 32); 2346 } 2347 } 2348 if (i >= 5) { 2349 pr_info("parport_pc: cannot find ITE8872 INTA\n"); 2350 return 0; 2351 } 2352 2353 type = inb(inta_addr[i] + 0x18); 2354 type &= 0x0f; 2355 2356 switch (type) { 2357 case 0x2: 2358 pr_info("parport_pc: ITE8871 found (1P)\n"); 2359 ite8872set = 0x64200000; 2360 break; 2361 case 0xa: 2362 pr_info("parport_pc: ITE8875 found (1P)\n"); 2363 ite8872set = 0x64200000; 2364 break; 2365 case 0xe: 2366 pr_info("parport_pc: ITE8872 found (2S1P)\n"); 2367 ite8872set = 0x64e00000; 2368 break; 2369 case 0x6: 2370 pr_info("parport_pc: ITE8873 found (1S)\n"); 2371 release_region(inta_addr[i], 32); 2372 return 0; 2373 case 0x8: 2374 pr_info("parport_pc: ITE8874 found (2S)\n"); 2375 release_region(inta_addr[i], 32); 2376 return 0; 2377 default: 2378 pr_info("parport_pc: unknown ITE887x\n"); 2379 pr_info("parport_pc: please mail 'lspci -nvv' output to Rich.Liu@ite.com.tw\n"); 2380 release_region(inta_addr[i], 32); 2381 return 0; 2382 } 2383 2384 pci_read_config_byte(pdev, 0x3c, &ite8872_irq); 2385 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt); 2386 ite8872_lpt &= 0x0000ff00; 2387 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi); 2388 ite8872_lpthi &= 0x0000ff00; 2389 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt); 2390 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi); 2391 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); 2392 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */ 2393 /* SET Parallel IRQ */ 2394 pci_write_config_dword(pdev, 0x9c, 2395 ite8872set | (ite8872_irq * 0x11111)); 2396 2397 pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq); 2398 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt); 2399 pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi); 2400 2401 /* Let the user (or defaults) steer us away from interrupts */ 2402 irq = ite8872_irq; 2403 if (autoirq != PARPORT_IRQ_AUTO) 2404 irq = PARPORT_IRQ_NONE; 2405 2406 /* 2407 * Release the resource so that parport_pc_probe_port can get it. 2408 */ 2409 release_region(inta_addr[i], 32); 2410 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi, 2411 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { 2412 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X", 2413 ite8872_lpt); 2414 if (irq != PARPORT_IRQ_NONE) 2415 pr_cont(", irq=%d", irq); 2416 pr_cont("\n"); 2417 return 1; 2418 } 2419 2420 return 0; 2421} 2422 2423/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> 2424 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ 2425static int parport_init_mode; 2426 2427/* Data for two known VIA chips */ 2428static struct parport_pc_via_data via_686a_data = { 2429 0x51, 2430 0x50, 2431 0x85, 2432 0x02, 2433 0xE2, 2434 0xF0, 2435 0xE6 2436}; 2437static struct parport_pc_via_data via_8231_data = { 2438 0x45, 2439 0x44, 2440 0x50, 2441 0x04, 2442 0xF2, 2443 0xFA, 2444 0xF6 2445}; 2446 2447static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, 2448 const struct parport_pc_via_data *via) 2449{ 2450 u8 tmp, tmp2, siofunc; 2451 u8 ppcontrol = 0; 2452 int dma, irq; 2453 unsigned port1, port2; 2454 unsigned have_epp = 0; 2455 2456 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); 2457 2458 switch (parport_init_mode) { 2459 case 1: 2460 printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); 2461 siofunc = VIA_FUNCTION_PARPORT_SPP; 2462 break; 2463 case 2: 2464 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); 2465 siofunc = VIA_FUNCTION_PARPORT_SPP; 2466 ppcontrol = VIA_PARPORT_BIDIR; 2467 break; 2468 case 3: 2469 printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); 2470 siofunc = VIA_FUNCTION_PARPORT_EPP; 2471 ppcontrol = VIA_PARPORT_BIDIR; 2472 have_epp = 1; 2473 break; 2474 case 4: 2475 printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); 2476 siofunc = VIA_FUNCTION_PARPORT_ECP; 2477 ppcontrol = VIA_PARPORT_BIDIR; 2478 break; 2479 case 5: 2480 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); 2481 siofunc = VIA_FUNCTION_PARPORT_ECP; 2482 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; 2483 have_epp = 1; 2484 break; 2485 default: 2486 printk(KERN_DEBUG "parport_pc: probing current configuration\n"); 2487 siofunc = VIA_FUNCTION_PROBE; 2488 break; 2489 } 2490 /* 2491 * unlock super i/o configuration 2492 */ 2493 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2494 tmp |= via->via_pci_superio_config_data; 2495 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2496 2497 /* Bits 1-0: Parallel Port Mode / Enable */ 2498 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2499 tmp = inb(VIA_CONFIG_DATA); 2500 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ 2501 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2502 tmp2 = inb(VIA_CONFIG_DATA); 2503 if (siofunc == VIA_FUNCTION_PROBE) { 2504 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; 2505 ppcontrol = tmp2; 2506 } else { 2507 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; 2508 tmp |= siofunc; 2509 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2510 outb(tmp, VIA_CONFIG_DATA); 2511 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); 2512 tmp2 |= ppcontrol; 2513 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2514 outb(tmp2, VIA_CONFIG_DATA); 2515 } 2516 2517 /* Parallel Port I/O Base Address, bits 9-2 */ 2518 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2519 port1 = inb(VIA_CONFIG_DATA) << 2; 2520 2521 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", 2522 port1); 2523 if (port1 == 0x3BC && have_epp) { 2524 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2525 outb((0x378 >> 2), VIA_CONFIG_DATA); 2526 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); 2527 port1 = 0x378; 2528 } 2529 2530 /* 2531 * lock super i/o configuration 2532 */ 2533 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2534 tmp &= ~via->via_pci_superio_config_data; 2535 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2536 2537 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { 2538 pr_info("parport_pc: VIA parallel port disabled in BIOS\n"); 2539 return 0; 2540 } 2541 2542 /* Bits 7-4: PnP Routing for Parallel Port IRQ */ 2543 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); 2544 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); 2545 2546 if (siofunc == VIA_FUNCTION_PARPORT_ECP) { 2547 /* Bits 3-2: PnP Routing for Parallel Port DMA */ 2548 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); 2549 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); 2550 } else 2551 /* if ECP not enabled, DMA is not enabled, assumed 2552 bogus 'dma' value */ 2553 dma = PARPORT_DMA_NONE; 2554 2555 /* Let the user (or defaults) steer us away from interrupts and DMA */ 2556 if (autoirq == PARPORT_IRQ_NONE) { 2557 irq = PARPORT_IRQ_NONE; 2558 dma = PARPORT_DMA_NONE; 2559 } 2560 if (autodma == PARPORT_DMA_NONE) 2561 dma = PARPORT_DMA_NONE; 2562 2563 switch (port1) { 2564 case 0x3bc: 2565 port2 = 0x7bc; break; 2566 case 0x378: 2567 port2 = 0x778; break; 2568 case 0x278: 2569 port2 = 0x678; break; 2570 default: 2571 pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n", 2572 port1); 2573 return 0; 2574 } 2575 2576 /* filter bogus IRQs */ 2577 switch (irq) { 2578 case 0: 2579 case 2: 2580 case 8: 2581 case 13: 2582 irq = PARPORT_IRQ_NONE; 2583 break; 2584 2585 default: /* do nothing */ 2586 break; 2587 } 2588 2589 /* finally, do the probe with values obtained */ 2590 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { 2591 pr_info("parport_pc: VIA parallel port: io=0x%X", port1); 2592 if (irq != PARPORT_IRQ_NONE) 2593 pr_cont(", irq=%d", irq); 2594 if (dma != PARPORT_DMA_NONE) 2595 pr_cont(", dma=%d", dma); 2596 pr_cont("\n"); 2597 return 1; 2598 } 2599 2600 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", 2601 port1, irq, dma); 2602 return 0; 2603} 2604 2605 2606enum parport_pc_sio_types { 2607 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ 2608 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ 2609 sio_ite_8872, 2610 last_sio 2611}; 2612 2613/* each element directly indexed from enum list, above */ 2614static struct parport_pc_superio { 2615 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, 2616 const struct parport_pc_via_data *via); 2617 const struct parport_pc_via_data *via; 2618} parport_pc_superio_info[] = { 2619 { sio_via_probe, &via_686a_data, }, 2620 { sio_via_probe, &via_8231_data, }, 2621 { sio_ite_8872_probe, NULL, }, 2622}; 2623 2624enum parport_pc_pci_cards { 2625 siig_1p_10x = last_sio, 2626 siig_2p_10x, 2627 siig_1p_20x, 2628 siig_2p_20x, 2629 lava_parallel, 2630 lava_parallel_dual_a, 2631 lava_parallel_dual_b, 2632 boca_ioppar, 2633 plx_9050, 2634 timedia_4006a, 2635 timedia_4014, 2636 timedia_4008a, 2637 timedia_4018, 2638 timedia_9018a, 2639 syba_2p_epp, 2640 syba_1p_ecp, 2641 titan_010l, 2642 avlab_1p, 2643 avlab_2p, 2644 oxsemi_952, 2645 oxsemi_954, 2646 oxsemi_840, 2647 oxsemi_pcie_pport, 2648 aks_0100, 2649 mobility_pp, 2650 netmos_9900, 2651 netmos_9705, 2652 netmos_9715, 2653 netmos_9755, 2654 netmos_9805, 2655 netmos_9815, 2656 netmos_9901, 2657 netmos_9865, 2658 asix_ax99100, 2659 quatech_sppxp100, 2660 wch_ch382l, 2661 brainboxes_uc146, 2662 brainboxes_px203, 2663}; 2664 2665 2666/* each element directly indexed from enum list, above 2667 * (but offset by last_sio) */ 2668static struct parport_pc_pci { 2669 int numports; 2670 struct { /* BAR (base address registers) numbers in the config 2671 space header */ 2672 int lo; 2673 int hi; 2674 /* -1 if not there, >6 for offset-method (max BAR is 6) */ 2675 } addr[2]; 2676 2677 /* Bit field of parport modes to exclude. */ 2678 unsigned int mode_mask; 2679 2680 /* If non-zero, sets the bitmask of writable ECR bits. In that 2681 * case additionally bit 0 will be forcibly set on writes. */ 2682 unsigned char ecr_writable; 2683 2684 /* If set, this is called immediately after pci_enable_device. 2685 * If it returns non-zero, no probing will take place and the 2686 * ports will not be used. */ 2687 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); 2688 2689 /* If set, this is called after probing for ports. If 'failed' 2690 * is non-zero we couldn't use any of the ports. */ 2691 void (*postinit_hook) (struct pci_dev *pdev, int failed); 2692} cards[] = { 2693 /* siig_1p_10x */ { 1, { { 2, 3 }, } }, 2694 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2695 /* siig_1p_20x */ { 1, { { 0, 1 }, } }, 2696 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2697 /* lava_parallel */ { 1, { { 0, -1 }, } }, 2698 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, 2699 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, 2700 /* boca_ioppar */ { 1, { { 0, -1 }, } }, 2701 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, 2702 /* timedia_4006a */ { 1, { { 0, -1 }, } }, 2703 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, 2704 /* timedia_4008a */ { 1, { { 0, 1 }, } }, 2705 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2706 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2707 /* SYBA uses fixed offsets in 2708 a 1K io window */ 2709 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, 2710 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, 2711 /* titan_010l */ { 1, { { 3, -1 }, } }, 2712 /* avlab_1p */ { 1, { { 0, 1}, } }, 2713 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, 2714 /* The Oxford Semi cards are unusual: older variants of 954 don't 2715 * support ECP, and 840 locks up if you write 1 to bit 2! None 2716 * implement nFault or service interrupts and all require 00001 2717 * bit pattern to be used for bits 4:0 with ECR writes. */ 2718 /* oxsemi_952 */ { 1, { { 0, 1 }, }, 2719 PARPORT_MODE_COMPAT, ECR_MODE_MASK }, 2720 /* oxsemi_954 */ { 1, { { 0, 1 }, }, 2721 PARPORT_MODE_ECP | 2722 PARPORT_MODE_COMPAT, ECR_MODE_MASK }, 2723 /* oxsemi_840 */ { 1, { { 0, 1 }, }, 2724 PARPORT_MODE_COMPAT, ECR_MODE_MASK }, 2725 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, }, 2726 PARPORT_MODE_COMPAT, ECR_MODE_MASK }, 2727 /* aks_0100 */ { 1, { { 0, -1 }, } }, 2728 /* mobility_pp */ { 1, { { 0, 1 }, } }, 2729 /* netmos_9900 */ { 1, { { 0, -1 }, } }, 2730 2731 /* The netmos entries below are untested */ 2732 /* netmos_9705 */ { 1, { { 0, -1 }, } }, 2733 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, 2734 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, 2735 /* netmos_9805 */ { 1, { { 0, 1 }, } }, 2736 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2737 /* netmos_9901 */ { 1, { { 0, -1 }, } }, 2738 /* netmos_9865 */ { 1, { { 0, -1 }, } }, 2739 /* asix_ax99100 */ { 1, { { 0, 1 }, } }, 2740 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } }, 2741 /* wch_ch382l */ { 1, { { 2, -1 }, } }, 2742 /* brainboxes_uc146 */ { 1, { { 3, -1 }, } }, 2743 /* brainboxes_px203 */ { 1, { { 0, -1 }, } }, 2744}; 2745 2746static const struct pci_device_id parport_pc_pci_tbl[] = { 2747 /* Super-IO onboard chips */ 2748 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, 2749 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, 2750 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 2751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, 2752 2753 /* PCI cards */ 2754 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, 2755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, 2756 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, 2757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, 2758 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, 2759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, 2760 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, 2761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, 2762 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, 2763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, 2764 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, 2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, 2766 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, 2767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, 2768 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, 2769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, 2770 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2771 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 }, 2772 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ 2773 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, 2774 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, 2775 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, 2776 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, 2777 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, 2778 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, 2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, 2780 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, 2781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, 2782 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, 2783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, 2784 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ 2785 /* AFAVLAB_TK9902 */ 2786 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, 2787 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, 2788 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP, 2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 }, 2790 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, 2791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, 2792 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, 2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, 2794 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840, 2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2796 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G, 2797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2798 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0, 2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2800 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G, 2801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2802 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1, 2803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2804 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G, 2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2806 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U, 2807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2808 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU, 2809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2810 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, 2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, 2812 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, 2813 /* NetMos communication controllers */ 2814 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 2815 0xA000, 0x2000, 0, 0, netmos_9900 }, 2816 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, 2817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, 2818 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, 2819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, 2820 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, 2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, 2822 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, 2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, 2824 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, 2825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, 2826 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 2827 0xA000, 0x2000, 0, 0, netmos_9901 }, 2828 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 2829 0xA000, 0x1000, 0, 0, netmos_9865 }, 2830 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 2831 0xA000, 0x2000, 0, 0, netmos_9865 }, 2832 /* ASIX AX99100 PCIe to Multi I/O Controller */ 2833 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 2834 0xA000, 0x2000, 0, 0, asix_ax99100 }, 2835 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */ 2836 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100, 2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 }, 2838 /* WCH CH382L PCI-E single parallel port card */ 2839 { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l }, 2840 /* Brainboxes IX-500/550 */ 2841 { PCI_VENDOR_ID_INTASHIELD, 0x402a, 2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2843 /* Brainboxes UC-146/UC-157 */ 2844 { PCI_VENDOR_ID_INTASHIELD, 0x0be1, 2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 }, 2846 { PCI_VENDOR_ID_INTASHIELD, 0x0be2, 2847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 }, 2848 /* Brainboxes PX-146/PX-257 */ 2849 { PCI_VENDOR_ID_INTASHIELD, 0x401c, 2850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2851 /* Brainboxes PX-203 */ 2852 { PCI_VENDOR_ID_INTASHIELD, 0x4007, 2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_px203 }, 2854 /* Brainboxes PX-475 */ 2855 { PCI_VENDOR_ID_INTASHIELD, 0x401f, 2856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2857 { 0, } /* terminate list */ 2858}; 2859MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl); 2860 2861struct pci_parport_data { 2862 int num; 2863 struct parport *ports[2]; 2864}; 2865 2866static int parport_pc_pci_probe(struct pci_dev *dev, 2867 const struct pci_device_id *id) 2868{ 2869 int err, count, n, i = id->driver_data; 2870 struct pci_parport_data *data; 2871 2872 if (i < last_sio) 2873 /* This is an onboard Super-IO and has already been probed */ 2874 return 0; 2875 2876 /* This is a PCI card */ 2877 i -= last_sio; 2878 count = 0; 2879 err = pci_enable_device(dev); 2880 if (err) 2881 return err; 2882 2883 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); 2884 if (!data) 2885 return -ENOMEM; 2886 2887 if (cards[i].preinit_hook && 2888 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { 2889 kfree(data); 2890 return -ENODEV; 2891 } 2892 2893 for (n = 0; n < cards[i].numports; n++) { 2894 int lo = cards[i].addr[n].lo; 2895 int hi = cards[i].addr[n].hi; 2896 int irq; 2897 unsigned long io_lo, io_hi; 2898 io_lo = pci_resource_start(dev, lo); 2899 io_hi = 0; 2900 if ((hi >= 0) && (hi <= 6)) 2901 io_hi = pci_resource_start(dev, hi); 2902 else if (hi > 6) 2903 io_lo += hi; /* Reinterpret the meaning of 2904 "hi" as an offset (see SYBA 2905 def.) */ 2906 /* TODO: test if sharing interrupts works */ 2907 irq = dev->irq; 2908 if (irq == IRQ_NONE) { 2909 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", 2910 id->vendor, id->device, io_lo, io_hi); 2911 irq = PARPORT_IRQ_NONE; 2912 } else { 2913 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", 2914 id->vendor, id->device, io_lo, io_hi, irq); 2915 } 2916 data->ports[count] = 2917 __parport_pc_probe_port(io_lo, io_hi, irq, 2918 PARPORT_DMA_NONE, &dev->dev, 2919 IRQF_SHARED, 2920 cards[i].mode_mask, 2921 cards[i].ecr_writable); 2922 if (data->ports[count]) 2923 count++; 2924 } 2925 2926 data->num = count; 2927 2928 if (cards[i].postinit_hook) 2929 cards[i].postinit_hook(dev, count == 0); 2930 2931 if (count) { 2932 pci_set_drvdata(dev, data); 2933 return 0; 2934 } 2935 2936 kfree(data); 2937 2938 return -ENODEV; 2939} 2940 2941static void parport_pc_pci_remove(struct pci_dev *dev) 2942{ 2943 struct pci_parport_data *data = pci_get_drvdata(dev); 2944 int i; 2945 2946 if (data) { 2947 for (i = data->num - 1; i >= 0; i--) 2948 parport_pc_unregister_port(data->ports[i]); 2949 2950 kfree(data); 2951 } 2952} 2953 2954static struct pci_driver parport_pc_pci_driver = { 2955 .name = "parport_pc", 2956 .id_table = parport_pc_pci_tbl, 2957 .probe = parport_pc_pci_probe, 2958 .remove = parport_pc_pci_remove, 2959}; 2960 2961static int __init parport_pc_init_superio(int autoirq, int autodma) 2962{ 2963 const struct pci_device_id *id; 2964 struct pci_dev *pdev = NULL; 2965 int ret = 0; 2966 2967 for_each_pci_dev(pdev) { 2968 id = pci_match_id(parport_pc_pci_tbl, pdev); 2969 if (id == NULL || id->driver_data >= last_sio) 2970 continue; 2971 2972 if (parport_pc_superio_info[id->driver_data].probe( 2973 pdev, autoirq, autodma, 2974 parport_pc_superio_info[id->driver_data].via)) { 2975 ret++; 2976 } 2977 } 2978 2979 return ret; /* number of devices found */ 2980} 2981#else 2982static struct pci_driver parport_pc_pci_driver; 2983static int __init parport_pc_init_superio(int autoirq, int autodma) 2984{ 2985 return 0; 2986} 2987#endif /* CONFIG_PCI */ 2988 2989#ifdef CONFIG_PNP 2990 2991static const struct pnp_device_id parport_pc_pnp_tbl[] = { 2992 /* Standard LPT Printer Port */ 2993 {.id = "PNP0400", .driver_data = 0}, 2994 /* ECP Printer Port */ 2995 {.id = "PNP0401", .driver_data = 0}, 2996 { } 2997}; 2998 2999MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl); 3000 3001static int parport_pc_pnp_probe(struct pnp_dev *dev, 3002 const struct pnp_device_id *id) 3003{ 3004 struct parport *pdata; 3005 unsigned long io_lo, io_hi; 3006 int dma, irq; 3007 3008 if (pnp_port_valid(dev, 0) && 3009 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) { 3010 io_lo = pnp_port_start(dev, 0); 3011 } else 3012 return -EINVAL; 3013 3014 if (pnp_port_valid(dev, 1) && 3015 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) { 3016 io_hi = pnp_port_start(dev, 1); 3017 } else 3018 io_hi = 0; 3019 3020 if (pnp_irq_valid(dev, 0) && 3021 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) { 3022 irq = pnp_irq(dev, 0); 3023 } else 3024 irq = PARPORT_IRQ_NONE; 3025 3026 if (pnp_dma_valid(dev, 0) && 3027 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) { 3028 dma = pnp_dma(dev, 0); 3029 } else 3030 dma = PARPORT_DMA_NONE; 3031 3032 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name); 3033 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0); 3034 if (pdata == NULL) 3035 return -ENODEV; 3036 3037 pnp_set_drvdata(dev, pdata); 3038 return 0; 3039} 3040 3041static void parport_pc_pnp_remove(struct pnp_dev *dev) 3042{ 3043 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); 3044 if (!pdata) 3045 return; 3046 3047 parport_pc_unregister_port(pdata); 3048} 3049 3050/* we only need the pnp layer to activate the device, at least for now */ 3051static struct pnp_driver parport_pc_pnp_driver = { 3052 .name = "parport_pc", 3053 .id_table = parport_pc_pnp_tbl, 3054 .probe = parport_pc_pnp_probe, 3055 .remove = parport_pc_pnp_remove, 3056}; 3057 3058#else 3059static struct pnp_driver parport_pc_pnp_driver; 3060#endif /* CONFIG_PNP */ 3061 3062static int parport_pc_platform_probe(struct platform_device *pdev) 3063{ 3064 /* Always succeed, the actual probing is done in 3065 * parport_pc_probe_port(). */ 3066 return 0; 3067} 3068 3069static struct platform_driver parport_pc_platform_driver = { 3070 .driver = { 3071 .name = "parport_pc", 3072 }, 3073 .probe = parport_pc_platform_probe, 3074}; 3075 3076/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ 3077static int __attribute__((unused)) 3078parport_pc_find_isa_ports(int autoirq, int autodma) 3079{ 3080 int count = 0; 3081 3082 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0)) 3083 count++; 3084 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0)) 3085 count++; 3086 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0)) 3087 count++; 3088 3089 return count; 3090} 3091 3092/* This function is called by parport_pc_init if the user didn't 3093 * specify any ports to probe. Its job is to find some ports. Order 3094 * is important here -- we want ISA ports to be registered first, 3095 * followed by PCI cards (for least surprise), but before that we want 3096 * to do chipset-specific tests for some onboard ports that we know 3097 * about. 3098 * 3099 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY 3100 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO 3101 */ 3102static void __init parport_pc_find_ports(int autoirq, int autodma) 3103{ 3104 int count = 0, err; 3105 3106#ifdef CONFIG_PARPORT_PC_SUPERIO 3107 detect_and_report_it87(); 3108 detect_and_report_winbond(); 3109 detect_and_report_smsc(); 3110#endif 3111 3112 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ 3113 count += parport_pc_init_superio(autoirq, autodma); 3114 3115 /* PnP ports, skip detection if SuperIO already found them */ 3116 if (!count) { 3117 err = pnp_register_driver(&parport_pc_pnp_driver); 3118 if (!err) 3119 pnp_registered_parport = 1; 3120 } 3121 3122 /* ISA ports and whatever (see asm/parport.h). */ 3123 parport_pc_find_nonpci_ports(autoirq, autodma); 3124 3125 err = pci_register_driver(&parport_pc_pci_driver); 3126 if (!err) 3127 pci_registered_parport = 1; 3128} 3129 3130/* 3131 * Piles of crap below pretend to be a parser for module and kernel 3132 * parameters. Say "thank you" to whoever had come up with that 3133 * syntax and keep in mind that code below is a cleaned up version. 3134 */ 3135 3136static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { 3137 [0 ... PARPORT_PC_MAX_PORTS] = 0 3138}; 3139static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = { 3140 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO 3141}; 3142static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { 3143 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE 3144}; 3145static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { 3146 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY 3147}; 3148 3149static int __init parport_parse_param(const char *s, int *val, 3150 int automatic, int none, int nofifo) 3151{ 3152 if (!s) 3153 return 0; 3154 if (!strncmp(s, "auto", 4)) 3155 *val = automatic; 3156 else if (!strncmp(s, "none", 4)) 3157 *val = none; 3158 else if (nofifo && !strncmp(s, "nofifo", 6)) 3159 *val = nofifo; 3160 else { 3161 char *ep; 3162 unsigned long r = simple_strtoul(s, &ep, 0); 3163 if (ep != s) 3164 *val = r; 3165 else { 3166 pr_err("parport: bad specifier `%s'\n", s); 3167 return -1; 3168 } 3169 } 3170 return 0; 3171} 3172 3173static int __init parport_parse_irq(const char *irqstr, int *val) 3174{ 3175 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, 3176 PARPORT_IRQ_NONE, 0); 3177} 3178 3179static int __init parport_parse_dma(const char *dmastr, int *val) 3180{ 3181 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, 3182 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); 3183} 3184 3185#ifdef CONFIG_PCI 3186static int __init parport_init_mode_setup(char *str) 3187{ 3188 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", 3189 str); 3190 3191 if (!strcmp(str, "spp")) 3192 parport_init_mode = 1; 3193 if (!strcmp(str, "ps2")) 3194 parport_init_mode = 2; 3195 if (!strcmp(str, "epp")) 3196 parport_init_mode = 3; 3197 if (!strcmp(str, "ecp")) 3198 parport_init_mode = 4; 3199 if (!strcmp(str, "ecpepp")) 3200 parport_init_mode = 5; 3201 return 1; 3202} 3203#endif 3204 3205#ifdef MODULE 3206static char *irq[PARPORT_PC_MAX_PORTS]; 3207static char *dma[PARPORT_PC_MAX_PORTS]; 3208 3209MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); 3210module_param_hw_array(io, int, ioport, NULL, 0); 3211MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); 3212module_param_hw_array(io_hi, int, ioport, NULL, 0); 3213MODULE_PARM_DESC(irq, "IRQ line"); 3214module_param_hw_array(irq, charp, irq, NULL, 0); 3215MODULE_PARM_DESC(dma, "DMA channel"); 3216module_param_hw_array(dma, charp, dma, NULL, 0); 3217#if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 3218 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 3219MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); 3220module_param(verbose_probing, int, 0644); 3221#endif 3222#ifdef CONFIG_PCI 3223static char *init_mode; 3224MODULE_PARM_DESC(init_mode, 3225 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); 3226module_param(init_mode, charp, 0); 3227#endif 3228 3229static int __init parse_parport_params(void) 3230{ 3231 unsigned int i; 3232 int val; 3233 3234#ifdef CONFIG_PCI 3235 if (init_mode) 3236 parport_init_mode_setup(init_mode); 3237#endif 3238 3239 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { 3240 if (parport_parse_irq(irq[i], &val)) 3241 return 1; 3242 irqval[i] = val; 3243 if (parport_parse_dma(dma[i], &val)) 3244 return 1; 3245 dmaval[i] = val; 3246 } 3247 if (!io[0]) { 3248 /* The user can make us use any IRQs or DMAs we find. */ 3249 if (irq[0] && !parport_parse_irq(irq[0], &val)) 3250 switch (val) { 3251 case PARPORT_IRQ_NONE: 3252 case PARPORT_IRQ_AUTO: 3253 irqval[0] = val; 3254 break; 3255 default: 3256 pr_warn("parport_pc: irq specified without base address. Use 'io=' to specify one\n"); 3257 } 3258 3259 if (dma[0] && !parport_parse_dma(dma[0], &val)) 3260 switch (val) { 3261 case PARPORT_DMA_NONE: 3262 case PARPORT_DMA_AUTO: 3263 dmaval[0] = val; 3264 break; 3265 default: 3266 pr_warn("parport_pc: dma specified without base address. Use 'io=' to specify one\n"); 3267 } 3268 } 3269 return 0; 3270} 3271 3272#else 3273 3274static int parport_setup_ptr __initdata; 3275 3276/* 3277 * Acceptable parameters: 3278 * 3279 * parport=0 3280 * parport=auto 3281 * parport=0xBASE[,IRQ[,DMA]] 3282 * 3283 * IRQ/DMA may be numeric or 'auto' or 'none' 3284 */ 3285static int __init parport_setup(char *str) 3286{ 3287 char *endptr; 3288 char *sep; 3289 int val; 3290 3291 if (!str || !*str || (*str == '0' && !*(str+1))) { 3292 /* Disable parport if "parport=0" in cmdline */ 3293 io[0] = PARPORT_DISABLE; 3294 return 1; 3295 } 3296 3297 if (!strncmp(str, "auto", 4)) { 3298 irqval[0] = PARPORT_IRQ_AUTO; 3299 dmaval[0] = PARPORT_DMA_AUTO; 3300 return 1; 3301 } 3302 3303 val = simple_strtoul(str, &endptr, 0); 3304 if (endptr == str) { 3305 pr_warn("parport=%s not understood\n", str); 3306 return 1; 3307 } 3308 3309 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { 3310 pr_err("parport=%s ignored, too many ports\n", str); 3311 return 1; 3312 } 3313 3314 io[parport_setup_ptr] = val; 3315 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; 3316 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; 3317 3318 sep = strchr(str, ','); 3319 if (sep++) { 3320 if (parport_parse_irq(sep, &val)) 3321 return 1; 3322 irqval[parport_setup_ptr] = val; 3323 sep = strchr(sep, ','); 3324 if (sep++) { 3325 if (parport_parse_dma(sep, &val)) 3326 return 1; 3327 dmaval[parport_setup_ptr] = val; 3328 } 3329 } 3330 parport_setup_ptr++; 3331 return 1; 3332} 3333 3334static int __init parse_parport_params(void) 3335{ 3336 return io[0] == PARPORT_DISABLE; 3337} 3338 3339__setup("parport=", parport_setup); 3340 3341/* 3342 * Acceptable parameters: 3343 * 3344 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] 3345 */ 3346#ifdef CONFIG_PCI 3347__setup("parport_init_mode=", parport_init_mode_setup); 3348#endif 3349#endif 3350 3351/* "Parser" ends here */ 3352 3353static int __init parport_pc_init(void) 3354{ 3355 int err; 3356 3357 if (parse_parport_params()) 3358 return -EINVAL; 3359 3360 err = platform_driver_register(&parport_pc_platform_driver); 3361 if (err) 3362 return err; 3363 3364 if (io[0]) { 3365 int i; 3366 /* Only probe the ports we were given. */ 3367 user_specified = 1; 3368 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { 3369 if (!io[i]) 3370 break; 3371 if (io_hi[i] == PARPORT_IOHI_AUTO) 3372 io_hi[i] = 0x400 + io[i]; 3373 parport_pc_probe_port(io[i], io_hi[i], 3374 irqval[i], dmaval[i], NULL, 0); 3375 } 3376 } else 3377 parport_pc_find_ports(irqval[0], dmaval[0]); 3378 3379 return 0; 3380} 3381 3382static void __exit parport_pc_exit(void) 3383{ 3384 if (pci_registered_parport) 3385 pci_unregister_driver(&parport_pc_pci_driver); 3386 if (pnp_registered_parport) 3387 pnp_unregister_driver(&parport_pc_pnp_driver); 3388 platform_driver_unregister(&parport_pc_platform_driver); 3389 3390 while (!list_empty(&ports_list)) { 3391 struct parport_pc_private *priv; 3392 struct parport *port; 3393 struct device *dev; 3394 priv = list_entry(ports_list.next, 3395 struct parport_pc_private, list); 3396 port = priv->port; 3397 dev = port->dev; 3398 parport_pc_unregister_port(port); 3399 if (dev && dev->bus == &platform_bus_type) 3400 platform_device_unregister(to_platform_device(dev)); 3401 } 3402} 3403 3404MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); 3405MODULE_DESCRIPTION("PC-style parallel port driver"); 3406MODULE_LICENSE("GPL"); 3407module_init(parport_pc_init) 3408module_exit(parport_pc_exit) 3409