1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * This file is part of wlcore 4 * 5 * Copyright (C) 2011 Texas Instruments Inc. 6 */ 7 8#ifndef __WLCORE_H__ 9#define __WLCORE_H__ 10 11#include <linux/platform_device.h> 12 13#include "wlcore_i.h" 14#include "event.h" 15#include "boot.h" 16 17/* The maximum number of Tx descriptors in all chip families */ 18#define WLCORE_MAX_TX_DESCRIPTORS 32 19 20/* 21 * We always allocate this number of mac addresses. If we don't 22 * have enough allocated addresses, the LAA bit is used 23 */ 24#define WLCORE_NUM_MAC_ADDRESSES 3 25 26/* wl12xx/wl18xx maximum transmission power (in dBm) */ 27#define WLCORE_MAX_TXPWR 25 28 29/* Texas Instruments pre assigned OUI */ 30#define WLCORE_TI_OUI_ADDRESS 0x080028 31 32/* forward declaration */ 33struct wl1271_tx_hw_descr; 34enum wl_rx_buf_align; 35struct wl1271_rx_descriptor; 36 37struct wlcore_ops { 38 int (*setup)(struct wl1271 *wl); 39 int (*identify_chip)(struct wl1271 *wl); 40 int (*identify_fw)(struct wl1271 *wl); 41 int (*boot)(struct wl1271 *wl); 42 int (*plt_init)(struct wl1271 *wl); 43 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr, 44 void *buf, size_t len); 45 int (*ack_event)(struct wl1271 *wl); 46 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event, 47 bool *timeout); 48 int (*process_mailbox_events)(struct wl1271 *wl); 49 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks); 50 void (*set_tx_desc_blocks)(struct wl1271 *wl, 51 struct wl1271_tx_hw_descr *desc, 52 u32 blks, u32 spare_blks); 53 void (*set_tx_desc_data_len)(struct wl1271 *wl, 54 struct wl1271_tx_hw_descr *desc, 55 struct sk_buff *skb); 56 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl, 57 u32 rx_desc); 58 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len); 59 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data, 60 u32 data_len); 61 int (*tx_delayed_compl)(struct wl1271 *wl); 62 void (*tx_immediate_compl)(struct wl1271 *wl); 63 int (*hw_init)(struct wl1271 *wl); 64 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 65 void (*convert_fw_status)(struct wl1271 *wl, void *raw_fw_status, 66 struct wl_fw_status *fw_status); 67 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl, 68 struct wl12xx_vif *wlvif); 69 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver); 70 int (*get_mac)(struct wl1271 *wl); 71 void (*set_tx_desc_csum)(struct wl1271 *wl, 72 struct wl1271_tx_hw_descr *desc, 73 struct sk_buff *skb); 74 void (*set_rx_csum)(struct wl1271 *wl, 75 struct wl1271_rx_descriptor *desc, 76 struct sk_buff *skb); 77 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl, 78 struct wl12xx_vif *wlvif); 79 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir); 80 int (*handle_static_data)(struct wl1271 *wl, 81 struct wl1271_static_data *static_data); 82 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, 83 struct cfg80211_scan_request *req); 84 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 85 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, 86 struct cfg80211_sched_scan_request *req, 87 struct ieee80211_scan_ies *ies); 88 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 89 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem); 90 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd, 91 struct ieee80211_vif *vif, 92 struct ieee80211_sta *sta, 93 struct ieee80211_key_conf *key_conf); 94 int (*channel_switch)(struct wl1271 *wl, 95 struct wl12xx_vif *wlvif, 96 struct ieee80211_channel_switch *ch_switch); 97 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len); 98 void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 99 int (*set_peer_cap)(struct wl1271 *wl, 100 struct ieee80211_sta_ht_cap *ht_cap, 101 bool allow_ht_operation, 102 u32 rate_set, u8 hlid); 103 u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr); 104 bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid, 105 struct wl1271_link *lnk); 106 bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid, 107 struct wl1271_link *lnk); 108 int (*interrupt_notify)(struct wl1271 *wl, bool action); 109 int (*rx_ba_filter)(struct wl1271 *wl, bool action); 110 int (*ap_sleep)(struct wl1271 *wl); 111 int (*smart_config_start)(struct wl1271 *wl, u32 group_bitmap); 112 int (*smart_config_stop)(struct wl1271 *wl); 113 int (*smart_config_set_group_key)(struct wl1271 *wl, u16 group_id, 114 u8 key_len, u8 *key); 115 int (*set_cac)(struct wl1271 *wl, struct wl12xx_vif *wlvif, 116 bool start); 117 int (*dfs_master_restart)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 118}; 119 120enum wlcore_partitions { 121 PART_DOWN, 122 PART_WORK, 123 PART_BOOT, 124 PART_DRPW, 125 PART_TOP_PRCM_ELP_SOC, 126 PART_PHY_INIT, 127 128 PART_TABLE_LEN, 129}; 130 131struct wlcore_partition { 132 u32 size; 133 u32 start; 134}; 135 136struct wlcore_partition_set { 137 struct wlcore_partition mem; 138 struct wlcore_partition reg; 139 struct wlcore_partition mem2; 140 struct wlcore_partition mem3; 141}; 142 143enum wlcore_registers { 144 /* register addresses, used with partition translation */ 145 REG_ECPU_CONTROL, 146 REG_INTERRUPT_NO_CLEAR, 147 REG_INTERRUPT_ACK, 148 REG_COMMAND_MAILBOX_PTR, 149 REG_EVENT_MAILBOX_PTR, 150 REG_INTERRUPT_TRIG, 151 REG_INTERRUPT_MASK, 152 REG_PC_ON_RECOVERY, 153 REG_CHIP_ID_B, 154 REG_CMD_MBOX_ADDRESS, 155 156 /* data access memory addresses, used with partition translation */ 157 REG_SLV_MEM_DATA, 158 REG_SLV_REG_DATA, 159 160 /* raw data access memory addresses */ 161 REG_RAW_FW_STATUS_ADDR, 162 163 REG_TABLE_LEN, 164}; 165 166struct wl1271_stats { 167 void *fw_stats; 168 unsigned long fw_stats_update; 169 size_t fw_stats_len; 170 171 unsigned int retry_count; 172 unsigned int excessive_retries; 173}; 174 175struct wl1271 { 176 bool initialized; 177 struct ieee80211_hw *hw; 178 bool mac80211_registered; 179 180 struct device *dev; 181 struct platform_device *pdev; 182 183 void *if_priv; 184 185 struct wl1271_if_operations *if_ops; 186 187 int irq; 188 int wakeirq; 189 190 int irq_flags; 191 int wakeirq_flags; 192 193 spinlock_t wl_lock; 194 195 enum wlcore_state state; 196 enum wl12xx_fw_type fw_type; 197 bool plt; 198 enum plt_mode plt_mode; 199 u8 fem_manuf; 200 u8 last_vif_count; 201 struct mutex mutex; 202 203 unsigned long flags; 204 205 struct wlcore_partition_set curr_part; 206 207 struct wl1271_chip chip; 208 209 int cmd_box_addr; 210 211 u8 *fw; 212 size_t fw_len; 213 void *nvs; 214 size_t nvs_len; 215 216 s8 hw_pg_ver; 217 218 /* address read from the fuse ROM */ 219 u32 fuse_oui_addr; 220 u32 fuse_nic_addr; 221 222 /* we have up to 2 MAC addresses */ 223 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES]; 224 int channel; 225 u8 system_hlid; 226 227 unsigned long links_map[BITS_TO_LONGS(WLCORE_MAX_LINKS)]; 228 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; 229 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; 230 unsigned long rate_policies_map[ 231 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)]; 232 unsigned long klv_templates_map[ 233 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)]; 234 235 u8 session_ids[WLCORE_MAX_LINKS]; 236 237 struct list_head wlvif_list; 238 239 u8 sta_count; 240 u8 ap_count; 241 242 struct wl1271_acx_mem_map *target_mem_map; 243 244 /* Accounting for allocated / available TX blocks on HW */ 245 u32 tx_blocks_freed; 246 u32 tx_blocks_available; 247 u32 tx_allocated_blocks; 248 u32 tx_results_count; 249 250 /* Accounting for allocated / available Tx packets in HW */ 251 u32 tx_pkts_freed[NUM_TX_QUEUES]; 252 u32 tx_allocated_pkts[NUM_TX_QUEUES]; 253 254 /* Transmitted TX packets counter for chipset interface */ 255 u32 tx_packets_count; 256 257 /* Time-offset between host and chipset clocks */ 258 s64 time_offset; 259 260 /* Frames scheduled for transmission, not handled yet */ 261 int tx_queue_count[NUM_TX_QUEUES]; 262 unsigned long queue_stop_reasons[ 263 NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES]; 264 265 /* Frames received, not handled yet by mac80211 */ 266 struct sk_buff_head deferred_rx_queue; 267 268 /* Frames sent, not returned yet to mac80211 */ 269 struct sk_buff_head deferred_tx_queue; 270 271 struct work_struct tx_work; 272 struct workqueue_struct *freezable_wq; 273 274 /* Pending TX frames */ 275 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)]; 276 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS]; 277 int tx_frames_cnt; 278 279 /* FW Rx counter */ 280 u32 rx_counter; 281 282 /* Intermediate buffer, used for packet aggregation */ 283 u8 *aggr_buf; 284 u32 aggr_buf_size; 285 286 /* Reusable dummy packet template */ 287 struct sk_buff *dummy_packet; 288 289 /* Network stack work */ 290 struct work_struct netstack_work; 291 292 /* FW log buffer */ 293 u8 *fwlog; 294 295 /* Number of valid bytes in the FW log buffer */ 296 ssize_t fwlog_size; 297 298 /* FW log end marker */ 299 u32 fwlog_end; 300 301 /* FW memory block size */ 302 u32 fw_mem_block_size; 303 304 /* Hardware recovery work */ 305 struct work_struct recovery_work; 306 bool watchdog_recovery; 307 308 /* Reg domain last configuration */ 309 DECLARE_BITMAP(reg_ch_conf_last, 64); 310 /* Reg domain pending configuration */ 311 DECLARE_BITMAP(reg_ch_conf_pending, 64); 312 313 /* Pointer that holds DMA-friendly block for the mailbox */ 314 void *mbox; 315 316 /* The mbox event mask */ 317 u32 event_mask; 318 /* events to unmask only when ap interface is up */ 319 u32 ap_event_mask; 320 321 /* Mailbox pointers */ 322 u32 mbox_size; 323 u32 mbox_ptr[2]; 324 325 /* Are we currently scanning */ 326 struct wl12xx_vif *scan_wlvif; 327 struct wl1271_scan scan; 328 struct delayed_work scan_complete_work; 329 330 struct ieee80211_vif *roc_vif; 331 struct delayed_work roc_complete_work; 332 333 struct wl12xx_vif *sched_vif; 334 335 /* The current band */ 336 enum nl80211_band band; 337 338 struct completion *elp_compl; 339 340 /* in dBm */ 341 int power_level; 342 343 struct wl1271_stats stats; 344 345 __le32 *buffer_32; 346 u32 buffer_cmd; 347 u32 buffer_busyword[WL1271_BUSY_WORD_CNT]; 348 349 void *raw_fw_status; 350 struct wl_fw_status *fw_status; 351 struct wl1271_tx_hw_res_if *tx_res_if; 352 353 /* Current chipset configuration */ 354 struct wlcore_conf conf; 355 356 bool sg_enabled; 357 358 bool enable_11a; 359 360 int recovery_count; 361 362 /* Most recently reported noise in dBm */ 363 s8 noise; 364 365 /* bands supported by this instance of wl12xx */ 366 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS]; 367 368 /* 369 * wowlan trigger was configured during suspend. 370 * (currently, only "ANY" trigger is supported) 371 */ 372 bool wow_enabled; 373 bool irq_wake_enabled; 374 375 /* 376 * AP-mode - links indexed by HLID. The global and broadcast links 377 * are always active. 378 */ 379 struct wl1271_link links[WLCORE_MAX_LINKS]; 380 381 /* number of currently active links */ 382 int active_link_count; 383 384 /* Fast/slow links bitmap according to FW */ 385 unsigned long fw_fast_lnk_map; 386 387 /* AP-mode - a bitmap of links currently in PS mode according to FW */ 388 unsigned long ap_fw_ps_map; 389 390 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */ 391 unsigned long ap_ps_map; 392 393 /* Quirks of specific hardware revisions */ 394 unsigned int quirks; 395 396 /* number of currently active RX BA sessions */ 397 int ba_rx_session_count; 398 399 /* Maximum number of supported RX BA sessions */ 400 int ba_rx_session_count_max; 401 402 /* AP-mode - number of currently connected stations */ 403 int active_sta_count; 404 405 /* Flag determining whether AP should broadcast OFDM-only rates */ 406 bool ofdm_only_ap; 407 408 /* last wlvif we transmitted from */ 409 struct wl12xx_vif *last_wlvif; 410 411 /* work to fire when Tx is stuck */ 412 struct delayed_work tx_watchdog_work; 413 414 struct wlcore_ops *ops; 415 /* pointer to the lower driver partition table */ 416 const struct wlcore_partition_set *ptable; 417 /* pointer to the lower driver register table */ 418 const int *rtable; 419 /* name of the firmwares to load - for PLT, single role, multi-role */ 420 const char *plt_fw_name; 421 const char *sr_fw_name; 422 const char *mr_fw_name; 423 424 u8 scan_templ_id_2_4; 425 u8 scan_templ_id_5; 426 u8 sched_scan_templ_id_2_4; 427 u8 sched_scan_templ_id_5; 428 u8 max_channels_5; 429 430 /* per-chip-family private structure */ 431 void *priv; 432 433 /* number of TX descriptors the HW supports. */ 434 u32 num_tx_desc; 435 /* number of RX descriptors the HW supports. */ 436 u32 num_rx_desc; 437 /* number of links the HW supports */ 438 u8 num_links; 439 /* max stations a single AP can support */ 440 u8 max_ap_stations; 441 442 /* translate HW Tx rates to standard rate-indices */ 443 const u8 **band_rate_to_idx; 444 445 /* size of table for HW rates that can be received from chip */ 446 u8 hw_tx_rate_tbl_size; 447 448 /* this HW rate and below are considered HT rates for this chip */ 449 u8 hw_min_ht_rate; 450 451 /* HW HT (11n) capabilities */ 452 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS]; 453 454 /* the current dfs region */ 455 enum nl80211_dfs_regions dfs_region; 456 bool radar_debug_mode; 457 458 /* size of the private FW status data */ 459 size_t fw_status_len; 460 size_t fw_status_priv_len; 461 462 /* RX Data filter rule state - enabled/disabled */ 463 unsigned long rx_filter_enabled[BITS_TO_LONGS(WL1271_MAX_RX_FILTERS)]; 464 465 /* size of the private static data */ 466 size_t static_data_priv_len; 467 468 /* the current channel type */ 469 enum nl80211_channel_type channel_type; 470 471 /* mutex for protecting the tx_flush function */ 472 struct mutex flush_mutex; 473 474 /* sleep auth value currently configured to FW */ 475 int sleep_auth; 476 477 /* the number of allocated MAC addresses in this chip */ 478 int num_mac_addr; 479 480 /* minimum FW version required for the driver to work in single-role */ 481 unsigned int min_sr_fw_ver[NUM_FW_VER]; 482 483 /* minimum FW version required for the driver to work in multi-role */ 484 unsigned int min_mr_fw_ver[NUM_FW_VER]; 485 486 struct completion nvs_loading_complete; 487 488 /* interface combinations supported by the hw */ 489 const struct ieee80211_iface_combination *iface_combinations; 490 u8 n_iface_combinations; 491 492 /* dynamic fw traces */ 493 u32 dynamic_fw_traces; 494 495 /* time sync zone master */ 496 u8 zone_master_mac_addr[ETH_ALEN]; 497}; 498 499int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev); 500void wlcore_remove(struct platform_device *pdev); 501struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size, 502 u32 mbox_size); 503int wlcore_free_hw(struct wl1271 *wl); 504int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd, 505 struct ieee80211_vif *vif, 506 struct ieee80211_sta *sta, 507 struct ieee80211_key_conf *key_conf); 508void wlcore_regdomain_config(struct wl1271 *wl); 509void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif, 510 struct wl1271_station *wl_sta, bool in_conn); 511 512static inline void 513wlcore_set_ht_cap(struct wl1271 *wl, enum nl80211_band band, 514 struct ieee80211_sta_ht_cap *ht_cap) 515{ 516 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap)); 517} 518 519/* Tell wlcore not to care about this element when checking the version */ 520#define WLCORE_FW_VER_IGNORE -1 521 522static inline void 523wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip, 524 unsigned int iftype_sr, unsigned int major_sr, 525 unsigned int subtype_sr, unsigned int minor_sr, 526 unsigned int iftype_mr, unsigned int major_mr, 527 unsigned int subtype_mr, unsigned int minor_mr) 528{ 529 wl->min_sr_fw_ver[FW_VER_CHIP] = chip; 530 wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr; 531 wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr; 532 wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr; 533 wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr; 534 535 wl->min_mr_fw_ver[FW_VER_CHIP] = chip; 536 wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr; 537 wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr; 538 wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr; 539 wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr; 540} 541 542/* Firmware image load chunk size */ 543#define CHUNK_SIZE 16384 544 545/* Quirks */ 546 547/* Each RX/TX transaction requires an end-of-transaction transfer */ 548#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0) 549 550/* wl127x and SPI don't support SDIO block size alignment */ 551#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2) 552 553/* means aggregated Rx packets are aligned to a SDIO block */ 554#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3) 555 556/* Older firmwares did not implement the FW logger over bus feature */ 557#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4) 558 559/* Older firmwares use an old NVS format */ 560#define WLCORE_QUIRK_LEGACY_NVS BIT(5) 561 562/* pad only the last frame in the aggregate buffer */ 563#define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7) 564 565/* extra header space is required for TKIP */ 566#define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8) 567 568/* Some firmwares not support sched scans while connected */ 569#define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9) 570 571/* separate probe response templates for one-shot and sched scans */ 572#define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10) 573 574/* Firmware requires reg domain configuration for active calibration */ 575#define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11) 576 577/* The FW only support a zero session id for AP */ 578#define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12) 579 580/* TODO: move all these common registers and values elsewhere */ 581#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC 582 583/* ELP register commands */ 584#define ELPCTRL_WAKE_UP 0x1 585#define ELPCTRL_WAKE_UP_WLAN_READY 0x5 586#define ELPCTRL_SLEEP 0x0 587/* ELP WLAN_READY bit */ 588#define ELPCTRL_WLAN_READY 0x2 589 590/************************************************************************* 591 592 Interrupt Trigger Register (Host -> WiLink) 593 594**************************************************************************/ 595 596/* Hardware to Embedded CPU Interrupts - first 32-bit register set */ 597 598/* 599 * The host sets this bit to inform the Wlan 600 * FW that a TX packet is in the XFER 601 * Buffer #0. 602 */ 603#define INTR_TRIG_TX_PROC0 BIT(2) 604 605/* 606 * The host sets this bit to inform the FW 607 * that it read a packet from RX XFER 608 * Buffer #0. 609 */ 610#define INTR_TRIG_RX_PROC0 BIT(3) 611 612#define INTR_TRIG_DEBUG_ACK BIT(4) 613 614#define INTR_TRIG_STATE_CHANGED BIT(5) 615 616/* Hardware to Embedded CPU Interrupts - second 32-bit register set */ 617 618/* 619 * The host sets this bit to inform the FW 620 * that it read a packet from RX XFER 621 * Buffer #1. 622 */ 623#define INTR_TRIG_RX_PROC1 BIT(17) 624 625/* 626 * The host sets this bit to inform the Wlan 627 * hardware that a TX packet is in the XFER 628 * Buffer #1. 629 */ 630#define INTR_TRIG_TX_PROC1 BIT(18) 631 632#define ACX_SLV_SOFT_RESET_BIT BIT(1) 633#define SOFT_RESET_MAX_TIME 1000000 634#define SOFT_RESET_STALL_TIME 1000 635 636#define ECPU_CONTROL_HALT 0x00000101 637 638#define WELP_ARM_COMMAND_VAL 0x4 639 640#endif /* __WLCORE_H__ */ 641