1/* SPDX-License-Identifier: GPL-2.0-only or Apache-2.0 */ 2/* 3 * WF200 hardware interface definitions 4 * 5 * Copyright (c) 2018-2020, Silicon Laboratories Inc. 6 */ 7 8#ifndef WFX_HIF_API_GENERAL_H 9#define WFX_HIF_API_GENERAL_H 10 11#include <linux/types.h> 12#include <linux/if_ether.h> 13 14#define HIF_ID_IS_INDICATION 0x80 15#define HIF_COUNTER_MAX 7 16 17struct wfx_hif_msg { 18 __le16 len; 19 u8 id; 20 u8 reserved:1; 21 u8 interface:2; 22 u8 seqnum:3; 23 u8 encrypted:2; 24 u8 body[]; 25} __packed; 26 27enum wfx_hif_general_requests_ids { 28 HIF_REQ_ID_CONFIGURATION = 0x09, 29 HIF_REQ_ID_CONTROL_GPIO = 0x26, 30 HIF_REQ_ID_SET_SL_MAC_KEY = 0x27, 31 HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28, 32 HIF_REQ_ID_SL_CONFIGURE = 0x29, 33 HIF_REQ_ID_PREVENT_ROLLBACK = 0x2a, 34 HIF_REQ_ID_PTA_SETTINGS = 0x2b, 35 HIF_REQ_ID_PTA_PRIORITY = 0x2c, 36 HIF_REQ_ID_PTA_STATE = 0x2d, 37 HIF_REQ_ID_SHUT_DOWN = 0x32, 38}; 39 40enum wfx_hif_general_confirmations_ids { 41 HIF_CNF_ID_CONFIGURATION = 0x09, 42 HIF_CNF_ID_CONTROL_GPIO = 0x26, 43 HIF_CNF_ID_SET_SL_MAC_KEY = 0x27, 44 HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28, 45 HIF_CNF_ID_SL_CONFIGURE = 0x29, 46 HIF_CNF_ID_PREVENT_ROLLBACK = 0x2a, 47 HIF_CNF_ID_PTA_SETTINGS = 0x2b, 48 HIF_CNF_ID_PTA_PRIORITY = 0x2c, 49 HIF_CNF_ID_PTA_STATE = 0x2d, 50 HIF_CNF_ID_SHUT_DOWN = 0x32, 51}; 52 53enum wfx_hif_general_indications_ids { 54 HIF_IND_ID_EXCEPTION = 0xe0, 55 HIF_IND_ID_STARTUP = 0xe1, 56 HIF_IND_ID_WAKEUP = 0xe2, 57 HIF_IND_ID_GENERIC = 0xe3, 58 HIF_IND_ID_ERROR = 0xe4, 59 HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5 60}; 61 62#define HIF_STATUS_SUCCESS (cpu_to_le32(0x0000)) 63#define HIF_STATUS_FAIL (cpu_to_le32(0x0001)) 64#define HIF_STATUS_INVALID_PARAMETER (cpu_to_le32(0x0002)) 65#define HIF_STATUS_WARNING (cpu_to_le32(0x0003)) 66#define HIF_STATUS_UNKNOWN_REQUEST (cpu_to_le32(0x0004)) 67#define HIF_STATUS_RX_FAIL_DECRYPT (cpu_to_le32(0x0010)) 68#define HIF_STATUS_RX_FAIL_MIC (cpu_to_le32(0x0011)) 69#define HIF_STATUS_RX_FAIL_NO_KEY (cpu_to_le32(0x0012)) 70#define HIF_STATUS_TX_FAIL_RETRIES (cpu_to_le32(0x0013)) 71#define HIF_STATUS_TX_FAIL_TIMEOUT (cpu_to_le32(0x0014)) 72#define HIF_STATUS_TX_FAIL_REQUEUE (cpu_to_le32(0x0015)) 73#define HIF_STATUS_REFUSED (cpu_to_le32(0x0016)) 74#define HIF_STATUS_BUSY (cpu_to_le32(0x0017)) 75#define HIF_STATUS_SLK_SET_KEY_SUCCESS (cpu_to_le32(0x005A)) 76#define HIF_STATUS_SLK_SET_KEY_ALREADY_BURNED (cpu_to_le32(0x006B)) 77#define HIF_STATUS_SLK_SET_KEY_DISALLOWED_MODE (cpu_to_le32(0x007C)) 78#define HIF_STATUS_SLK_SET_KEY_UNKNOWN_MODE (cpu_to_le32(0x008D)) 79#define HIF_STATUS_SLK_NEGO_SUCCESS (cpu_to_le32(0x009E)) 80#define HIF_STATUS_SLK_NEGO_FAILED (cpu_to_le32(0x00AF)) 81#define HIF_STATUS_ROLLBACK_SUCCESS (cpu_to_le32(0x1234)) 82#define HIF_STATUS_ROLLBACK_FAIL (cpu_to_le32(0x1256)) 83 84enum wfx_hif_api_rate_index { 85 API_RATE_INDEX_B_1MBPS = 0, 86 API_RATE_INDEX_B_2MBPS = 1, 87 API_RATE_INDEX_B_5P5MBPS = 2, 88 API_RATE_INDEX_B_11MBPS = 3, 89 API_RATE_INDEX_PBCC_22MBPS = 4, 90 API_RATE_INDEX_PBCC_33MBPS = 5, 91 API_RATE_INDEX_G_6MBPS = 6, 92 API_RATE_INDEX_G_9MBPS = 7, 93 API_RATE_INDEX_G_12MBPS = 8, 94 API_RATE_INDEX_G_18MBPS = 9, 95 API_RATE_INDEX_G_24MBPS = 10, 96 API_RATE_INDEX_G_36MBPS = 11, 97 API_RATE_INDEX_G_48MBPS = 12, 98 API_RATE_INDEX_G_54MBPS = 13, 99 API_RATE_INDEX_N_6P5MBPS = 14, 100 API_RATE_INDEX_N_13MBPS = 15, 101 API_RATE_INDEX_N_19P5MBPS = 16, 102 API_RATE_INDEX_N_26MBPS = 17, 103 API_RATE_INDEX_N_39MBPS = 18, 104 API_RATE_INDEX_N_52MBPS = 19, 105 API_RATE_INDEX_N_58P5MBPS = 20, 106 API_RATE_INDEX_N_65MBPS = 21, 107 API_RATE_NUM_ENTRIES = 22 108}; 109 110struct wfx_hif_ind_startup { 111 __le32 status; 112 __le16 hardware_id; 113 u8 opn[14]; 114 u8 uid[8]; 115 __le16 num_inp_ch_bufs; 116 __le16 size_inp_ch_buf; 117 u8 num_links_ap; 118 u8 num_interfaces; 119 u8 mac_addr[2][ETH_ALEN]; 120 u8 api_version_minor; 121 u8 api_version_major; 122 u8 link_mode:2; 123 u8 reserved1:6; 124 u8 reserved2; 125 u8 reserved3; 126 u8 reserved4; 127 u8 firmware_build; 128 u8 firmware_minor; 129 u8 firmware_major; 130 u8 firmware_type; 131 u8 disabled_channel_list[2]; 132 u8 region_sel_mode:4; 133 u8 reserved5:4; 134 u8 phy1_region:3; 135 u8 phy0_region:3; 136 u8 otp_phy_ver:2; 137 __le32 supported_rate_mask; 138 u8 firmware_label[128]; 139} __packed; 140 141struct wfx_hif_ind_wakeup { 142} __packed; 143 144struct wfx_hif_req_configuration { 145 __le16 length; 146 u8 pds_data[]; 147} __packed; 148 149struct wfx_hif_cnf_configuration { 150 __le32 status; 151} __packed; 152 153enum wfx_hif_gpio_mode { 154 HIF_GPIO_MODE_D0 = 0x0, 155 HIF_GPIO_MODE_D1 = 0x1, 156 HIF_GPIO_MODE_OD0 = 0x2, 157 HIF_GPIO_MODE_OD1 = 0x3, 158 HIF_GPIO_MODE_TRISTATE = 0x4, 159 HIF_GPIO_MODE_TOGGLE = 0x5, 160 HIF_GPIO_MODE_READ = 0x6 161}; 162 163struct wfx_hif_req_control_gpio { 164 u8 gpio_label; 165 u8 gpio_mode; 166} __packed; 167 168struct wfx_hif_cnf_control_gpio { 169 __le32 status; 170 __le32 value; 171} __packed; 172 173enum wfx_hif_generic_indication_type { 174 HIF_GENERIC_INDICATION_TYPE_RAW = 0x0, 175 HIF_GENERIC_INDICATION_TYPE_STRING = 0x1, 176 HIF_GENERIC_INDICATION_TYPE_RX_STATS = 0x2, 177 HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO = 0x3, 178}; 179 180struct wfx_hif_rx_stats { 181 __le32 nb_rx_frame; 182 __le32 nb_crc_frame; 183 __le32 per_total; 184 __le32 throughput; 185 __le32 nb_rx_by_rate[API_RATE_NUM_ENTRIES]; 186 __le16 per[API_RATE_NUM_ENTRIES]; 187 __le16 snr[API_RATE_NUM_ENTRIES]; /* signed value */ 188 __le16 rssi[API_RATE_NUM_ENTRIES]; /* signed value */ 189 __le16 cfo[API_RATE_NUM_ENTRIES]; /* signed value */ 190 __le32 date; 191 __le32 pwr_clk_freq; 192 u8 is_ext_pwr_clk; 193 s8 current_temp; 194} __packed; 195 196struct wfx_hif_tx_power_loop_info { 197 __le16 tx_gain_dig; 198 __le16 tx_gain_pa; 199 __le16 target_pout; /* signed value */ 200 __le16 p_estimation; /* signed value */ 201 __le16 vpdet; 202 u8 measurement_index; 203 u8 reserved; 204} __packed; 205 206struct wfx_hif_ind_generic { 207 __le32 type; 208 union { 209 struct wfx_hif_rx_stats rx_stats; 210 struct wfx_hif_tx_power_loop_info tx_power_loop_info; 211 } data; 212} __packed; 213 214enum wfx_hif_error { 215 HIF_ERROR_FIRMWARE_ROLLBACK = 0x00, 216 HIF_ERROR_FIRMWARE_DEBUG_ENABLED = 0x01, 217 HIF_ERROR_SLK_OUTDATED_SESSION_KEY = 0x02, 218 HIF_ERROR_SLK_SESSION_KEY = 0x03, 219 HIF_ERROR_OOR_VOLTAGE = 0x04, 220 HIF_ERROR_PDS_PAYLOAD = 0x05, 221 HIF_ERROR_OOR_TEMPERATURE = 0x06, 222 HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE = 0x07, 223 HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED = 0x08, 224 HIF_ERROR_SLK_OVERFLOW = 0x09, 225 HIF_ERROR_SLK_DECRYPTION = 0x0a, 226 HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE = 0x0b, 227 HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW = 0x0c, 228 HIF_ERROR_HIF_RX_DATA_TOO_LARGE = 0x0e, 229 HIF_ERROR_HIF_TX_QUEUE_FULL = 0x0d, 230 HIF_ERROR_HIF_BUS = 0x0f, 231 HIF_ERROR_PDS_TESTFEATURE = 0x10, 232 HIF_ERROR_SLK_UNCONFIGURED = 0x11, 233}; 234 235struct wfx_hif_ind_error { 236 __le32 type; 237 u8 data[]; 238} __packed; 239 240struct wfx_hif_ind_exception { 241 __le32 type; 242 u8 data[]; 243} __packed; 244 245enum wfx_hif_secure_link_state { 246 SEC_LINK_UNAVAILABLE = 0x0, 247 SEC_LINK_RESERVED = 0x1, 248 SEC_LINK_EVAL = 0x2, 249 SEC_LINK_ENFORCED = 0x3 250}; 251 252#endif 253