1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2020 Realtek Corporation 3 */ 4 5#ifndef __RTW89_TXRX_H__ 6#define __RTW89_TXRX_H__ 7 8#include "debug.h" 9 10#define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) 11#define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8) 12#define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) 13#define DATA_RATE_MODE_NON_HT 0x0 14#define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) 15#define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0) 16#define DATA_RATE_MODE_HT 0x1 17#define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) 18#define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) 19#define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5) 20#define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0) 21#define DATA_RATE_MODE_VHT 0x2 22#define DATA_RATE_MODE_HE 0x3 23#define DATA_RATE_MODE_EHT 0x4 24 25static inline u8 rtw89_get_data_rate_mode(struct rtw89_dev *rtwdev, u16 hw_rate) 26{ 27 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 28 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK_V1); 29 30 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK); 31} 32 33static inline u8 rtw89_get_data_not_ht_idx(struct rtw89_dev *rtwdev, u16 hw_rate) 34{ 35 return u16_get_bits(hw_rate, DATA_RATE_NOT_HT_IDX_MASK); 36} 37 38static inline u8 rtw89_get_data_ht_mcs(struct rtw89_dev *rtwdev, u16 hw_rate) 39{ 40 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 41 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK_V1); 42 43 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK); 44} 45 46static inline u8 rtw89_get_data_mcs(struct rtw89_dev *rtwdev, u16 hw_rate) 47{ 48 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 49 return u16_get_bits(hw_rate, DATA_RATE_MCS_MASK_V1); 50 51 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_IDX_MASK); 52} 53 54static inline u8 rtw89_get_data_nss(struct rtw89_dev *rtwdev, u16 hw_rate) 55{ 56 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 57 return u16_get_bits(hw_rate, DATA_RATE_NSS_MASK_V1); 58 59 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_NSS_MASK); 60} 61 62/* TX WD BODY DWORD 0 */ 63#define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) 64#define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24) 65#define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 66#define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 67#define RTW89_TXWD_BODY0_FW_DL BIT(20) 68#define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) 69#define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 70#define RTW89_TXWD_BODY0_WD_PAGE BIT(7) 71#define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) 72#define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2) 73#define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0) 74 75/* TX WD BODY DWORD 1 */ 76#define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26) 77#define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) 78#define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4) 79#define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0) 80 81/* TX WD BODY DWORD 2 */ 82#define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) 83#define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) 84#define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) 85#define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) 86 87/* TX WD BODY DWORD 3 */ 88#define RTW89_TXWD_BODY3_BK BIT(13) 89#define RTW89_TXWD_BODY3_AGG_EN BIT(12) 90#define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) 91 92/* TX WD BODY DWORD 4 */ 93#define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24) 94#define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16) 95 96/* TX WD BODY DWORD 5 */ 97#define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24) 98#define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16) 99#define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8) 100#define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0) 101 102/* TX WD BODY DWORD 6 (V1) */ 103 104/* TX WD BODY DWORD 7 (V1) */ 105#define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31) 106#define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28) 107#define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25) 108#define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16) 109 110/* TX WD INFO DWORD 0 */ 111#define RTW89_TXWD_INFO0_USE_RATE BIT(30) 112#define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) 113#define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) 114#define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) 115#define RTW89_TXWD_INFO0_DATA_ER BIT(15) 116#define RTW89_TXWD_INFO0_DISDATAFB BIT(10) 117#define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8) 118#define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4) 119 120/* TX WD INFO DWORD 1 */ 121#define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) 122#define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) 123#define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) 124 125/* TX WD INFO DWORD 2 */ 126#define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 127#define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) 128#define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) 129#define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8) 130#define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 131 132/* TX WD INFO DWORD 3 */ 133 134/* TX WD INFO DWORD 4 */ 135#define RTW89_TXWD_INFO4_RTS_EN BIT(27) 136#define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) 137 138/* TX WD INFO DWORD 5 */ 139 140/* TX WD BODY DWORD 0 */ 141#define BE_TXD_BODY0_EN_HWSEQ_MODE GENMASK(1, 0) 142#define BE_TXD_BODY0_HW_SSN_SEL GENMASK(4, 2) 143#define BE_TXD_BODY0_HWAMSDU BIT(5) 144#define BE_TXD_BODY0_HW_SEC_IV BIT(6) 145#define BE_TXD_BODY0_WD_PAGE BIT(7) 146#define BE_TXD_BODY0_CHK_EN BIT(8) 147#define BE_TXD_BODY0_WP_INT BIT(9) 148#define BE_TXD_BODY0_STF_MODE BIT(10) 149#define BE_TXD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 150#define BE_TXD_BODY0_CH_DMA GENMASK(19, 16) 151#define BE_TXD_BODY0_SMH_EN BIT(20) 152#define BE_TXD_BODY0_PKT_OFFSET BIT(21) 153#define BE_TXD_BODY0_WDINFO_EN BIT(22) 154#define BE_TXD_BODY0_MOREDATA BIT(23) 155#define BE_TXD_BODY0_WP_OFFSET_V1 GENMASK(27, 24) 156#define BE_TXD_BODY0_AZ_FTM_SEC_V1 BIT(28) 157#define BE_TXD_BODY0_WD_SOURCE GENMASK(30, 29) 158#define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31) 159 160/* TX WD BODY DWORD 1 */ 161#define BE_TXD_BODY1_DMA_TXAGG_NUM GENMASK(6, 0) 162#define BE_TXD_BODY1_REUSE_NUM GENMASK(11, 7) 163#define BE_TXD_BODY1_SEC_TYPE GENMASK(15, 12) 164#define BE_TXD_BODY1_SEC_KEYID GENMASK(17, 16) 165#define BE_TXD_BODY1_SW_SEC_IV BIT(18) 166#define BE_TXD_BODY1_REUSE_SIZE GENMASK(23, 20) 167#define BE_TXD_BODY1_REUSE_START_OFFSET GENMASK(25, 24) 168#define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26) 169 170/* TX WD BODY DWORD 2 */ 171#define BE_TXD_BODY2_TXPKTSIZE GENMASK(13, 0) 172#define BE_TXD_BODY2_AGG_EN BIT(14) 173#define BE_TXD_BODY2_BK BIT(15) 174#define BE_TXD_BODY2_MACID_EXTEND BIT(16) 175#define BE_TXD_BODY2_QSEL GENMASK(22, 17) 176#define BE_TXD_BODY2_TID_IND BIT(23) 177#define BE_TXD_BODY2_MACID GENMASK(31, 24) 178 179/* TX WD BODY DWORD 3 */ 180#define BE_TXD_BODY3_WIFI_SEQ GENMASK(11, 0) 181#define BE_TXD_BODY3_MLO_FLAG BIT(12) 182#define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13) 183#define BE_TXD_BODY3_TRY_RATE BIT(14) 184#define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15) 185#define BE_TXD_BODY3_BAND0_SU_TC_V1 GENMASK(21, 16) 186#define BE_TXD_BODY3_TOTAL_TC GENMASK(27, 22) 187#define BE_TXD_BODY3_RU_RTY BIT(28) 188#define BE_TXD_BODY3_MU_PRI_RTY BIT(29) 189#define BE_TXD_BODY3_MU_2ND_RTY BIT(30) 190#define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31) 191 192/* TX WD BODY DWORD 4 */ 193#define BE_TXD_BODY4_TXDESC_CHECKSUM GENMASK(15, 0) 194#define BE_TXD_BODY4_SEC_IV_L0 GENMASK(23, 16) 195#define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24) 196 197/* TX WD BODY DWORD 5 */ 198#define BE_TXD_BODY5_SEC_IV_H2 GENMASK(7, 0) 199#define BE_TXD_BODY5_SEC_IV_H3 GENMASK(15, 8) 200#define BE_TXD_BODY5_SEC_IV_H4 GENMASK(23, 16) 201#define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24) 202 203/* TX WD BODY DWORD 6 */ 204#define BE_TXD_BODY6_MU_TC GENMASK(4, 0) 205#define BE_TXD_BODY6_RU_TC GENMASK(9, 5) 206#define BE_TXD_BODY6_PS160 BIT(10) 207#define BE_TXD_BODY6_BMC BIT(11) 208#define BE_TXD_BODY6_NO_ACK BIT(12) 209#define BE_TXD_BODY6_UPD_WLAN_HDR BIT(13) 210#define BE_TXD_BODY6_A4_HDR BIT(14) 211#define BE_TXD_BODY6_EOSP_BIT BIT(15) 212#define BE_TXD_BODY6_S_IDX GENMASK(23, 16) 213#define BE_TXD_BODY6_RU_POS GENMASK(31, 24) 214 215/* TX WD BODY DWORD 7 */ 216#define BE_TXD_BODY7_RTS_TC GENMASK(5, 0) 217#define BE_TXD_BODY7_MSDU_NUM GENMASK(9, 6) 218#define BE_TXD_BODY7_DATA_ER BIT(10) 219#define BE_TXD_BODY7_DATA_BW_ER BIT(11) 220#define BE_TXD_BODY7_DATA_DCM BIT(12) 221#define BE_TXD_BODY7_GI_LTF GENMASK(15, 13) 222#define BE_TXD_BODY7_DATARATE GENMASK(27, 16) 223#define BE_TXD_BODY7_DATA_BW GENMASK(30, 28) 224#define BE_TXD_BODY7_USERATE_SEL BIT(31) 225 226/* TX WD INFO DWORD 0 */ 227#define BE_TXD_INFO0_MBSSID GENMASK(3, 0) 228#define BE_TXD_INFO0_MULTIPORT_ID GENMASK(6, 4) 229#define BE_TXD_INFO0_DISRTSFB BIT(9) 230#define BE_TXD_INFO0_DISDATAFB BIT(10) 231#define BE_TXD_INFO0_DATA_LDPC BIT(11) 232#define BE_TXD_INFO0_DATA_STBC BIT(12) 233#define BE_TXD_INFO0_DATA_TXCNT_LMT GENMASK(21, 16) 234#define BE_TXD_INFO0_DATA_TXCNT_LMT_SEL BIT(22) 235#define BE_TXD_INFO0_RESP_PHYSTS_CSI_EN_V1 BIT(23) 236#define BE_TXD_INFO0_RLS_TO_CPUIO BIT(30) 237#define BE_TXD_INFO0_ACK_CH_INFO BIT(31) 238 239/* TX WD INFO DWORD 1 */ 240#define BE_TXD_INFO1_MAX_AGG_NUM GENMASK(7, 0) 241#define BE_TXD_INFO1_BCN_SRCH_SEQ GENMASK(9, 8) 242#define BE_TXD_INFO1_NAVUSEHDR BIT(10) 243#define BE_TXD_INFO1_A_CTRL_BQR BIT(12) 244#define BE_TXD_INFO1_A_CTRL_BSR BIT(14) 245#define BE_TXD_INFO1_A_CTRL_CAS BIT(15) 246#define BE_TXD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(27, 16) 247#define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28) 248 249/* TX WD INFO DWORD 2 */ 250#define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 251#define BE_TXD_INFO2_FORCE_KEY_EN BIT(8) 252#define BE_TXD_INFO2_LIFETIME_SEL GENMASK(15, 13) 253#define BE_TXD_INFO2_FORCE_TXOP BIT(17) 254#define BE_TXD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 255#define BE_TXD_INFO2_LSIG_TXOP_EN BIT(21) 256#define BE_TXD_INFO2_OBW_CTS2SELF_DUP_TYPE GENMASK(29, 26) 257#define BE_TXD_INFO2_SPE_RPT_V1 BIT(30) 258#define BE_TXD_INFO2_SIFS_TX_V1 BIT(31) 259 260/* TX WD INFO DWORD 3 */ 261#define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0) 262#define BE_TXD_INFO3_SPE_PKT_TYPE GENMASK(7, 4) 263#define BE_TXD_INFO3_CQI_SND BIT(8) 264#define BE_TXD_INFO3_RTT_EN BIT(9) 265#define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10) 266#define BE_TXD_INFO3_BT_NULL BIT(11) 267#define BE_TXD_INFO3_TRI_FRAME BIT(12) 268#define BE_TXD_INFO3_NULL_0 BIT(13) 269#define BE_TXD_INFO3_NULL_1 BIT(14) 270#define BE_TXD_INFO3_RAW BIT(15) 271#define BE_TXD_INFO3_GROUP_BIT_IE_OFFSET GENMASK(23, 16) 272#define BE_TXD_INFO3_SIGNALING_TA_PKT_EN BIT(25) 273#define BE_TXD_INFO3_BCNPKT_TSF_CTRL BIT(26) 274#define BE_TXD_INFO3_SIGNALING_TA_PKT_SC GENMASK(30, 27) 275#define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31) 276 277/* TX WD INFO DWORD 4 */ 278#define BE_TXD_INFO4_PUNCTURE_PATTERN GENMASK(15, 0) 279#define BE_TXD_INFO4_PUNC_MODE GENMASK(17, 16) 280#define BE_TXD_INFO4_SW_TX_OK_0 BIT(18) 281#define BE_TXD_INFO4_SW_TX_OK_1 BIT(19) 282#define BE_TXD_INFO4_SW_TX_PWR_DBM GENMASK(26, 23) 283#define BE_TXD_INFO4_RTS_EN BIT(27) 284#define BE_TXD_INFO4_CTS2SELF BIT(28) 285#define BE_TXD_INFO4_CCA_RTS GENMASK(30, 29) 286#define BE_TXD_INFO4_HW_RTS_EN BIT(31) 287 288/* TX WD INFO DWORD 5 */ 289#define BE_TXD_INFO5_SR_RATE_V1 GENMASK(4, 0) 290#define BE_TXD_INFO5_SR_EN_V1 BIT(5) 291#define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16) 292 293/* TX WD INFO DWORD 6 */ 294#define BE_TXD_INFO6_UL_APEP_LEN GENMASK(11, 0) 295#define BE_TXD_INFO6_UL_GI_LTF GENMASK(14, 12) 296#define BE_TXD_INFO6_UL_DOPPLER BIT(15) 297#define BE_TXD_INFO6_UL_STBC BIT(16) 298#define BE_TXD_INFO6_UL_LENGTH_REF GENMASK(21, 18) 299#define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22) 300 301/* TX WD INFO DWORD 7 */ 302#define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0) 303#define BE_TXD_INFO7_UL_PRI_EXP_RSSI_DBM GENMASK(7, 1) 304#define BE_TXD_INFO7_ELNA_IDX BIT(8) 305#define BE_TXD_INFO7_UL_APEP_UNIT GENMASK(10, 9) 306#define BE_TXD_INFO7_UL_TRI_PAD GENMASK(13, 11) 307#define BE_TXD_INFO7_UL_T_PE GENMASK(15, 14) 308#define BE_TXD_INFO7_UL_EHT_USR_PRES BIT(16) 309#define BE_TXD_INFO7_UL_HELTF_SYMBOL_NUM GENMASK(19, 17) 310#define BE_TXD_INFO7_ULBW GENMASK(21, 20) 311#define BE_TXD_INFO7_ULBW_EXT GENMASK(23, 22) 312#define BE_TXD_INFO7_USE_WD_UL GENMASK(25, 24) 313#define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28) 314 315/* RX WD dword0 */ 316#define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0) 317#define AX_RXD_SHIFT_MASK GENMASK(15, 14) 318#define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16) 319#define AX_RXD_BB_SEL BIT(22) 320#define AX_RXD_MAC_INFO_VLD BIT(23) 321#define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24) 322#define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28) 323#define AX_RXD_LONG_RXD BIT(31) 324 325/* RX WD dword1 */ 326#define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0) 327#define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4) 328#define AX_RXD_SR_EN BIT(7) 329#define AX_RXD_USER_ID_MASK GENMASK(15, 8) 330#define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8) 331#define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16) 332#define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25) 333#define AX_RXD_NON_SRG_PPDU BIT(28) 334#define AX_RXD_INTER_PPDU BIT(29) 335#define AX_RXD_NON_SRG_PPDU_v1 BIT(14) 336#define AX_RXD_INTER_PPDU_v1 BIT(15) 337#define AX_RXD_BW_MASK GENMASK(31, 30) 338#define AX_RXD_BW_v1_MASK GENMASK(31, 29) 339 340/* RX WD dword2 */ 341#define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0) 342 343/* RX WD dword3 */ 344#define AX_RXD_A1_MATCH BIT(0) 345#define AX_RXD_SW_DEC BIT(1) 346#define AX_RXD_HW_DEC BIT(2) 347#define AX_RXD_AMPDU BIT(3) 348#define AX_RXD_AMPDU_END_PKT BIT(4) 349#define AX_RXD_AMSDU BIT(5) 350#define AX_RXD_AMSDU_CUT BIT(6) 351#define AX_RXD_LAST_MSDU BIT(7) 352#define AX_RXD_BYPASS BIT(8) 353#define AX_RXD_CRC32_ERR BIT(9) 354#define AX_RXD_ICV_ERR BIT(10) 355#define AX_RXD_MAGIC_WAKE BIT(11) 356#define AX_RXD_UNICAST_WAKE BIT(12) 357#define AX_RXD_PATTERN_WAKE BIT(13) 358#define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14) 359#define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16) 360#define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21) 361#define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24) 362#define AX_RXD_WITH_LLC BIT(25) 363#define AX_RXD_RX_STATISTICS BIT(26) 364 365/* RX WD dword4 */ 366#define AX_RXD_TYPE_MASK GENMASK(1, 0) 367#define AX_RXD_MC BIT(2) 368#define AX_RXD_BC BIT(3) 369#define AX_RXD_MD BIT(4) 370#define AX_RXD_MF BIT(5) 371#define AX_RXD_PWR BIT(6) 372#define AX_RXD_QOS BIT(7) 373#define AX_RXD_TID_MASK GENMASK(11, 8) 374#define AX_RXD_EOSP BIT(12) 375#define AX_RXD_HTC BIT(13) 376#define AX_RXD_QNULL BIT(14) 377#define AX_RXD_SEQ_MASK GENMASK(27, 16) 378#define AX_RXD_FRAG_MASK GENMASK(31, 28) 379 380/* RX WD dword5 */ 381#define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0) 382#define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8) 383#define AX_RXD_MAC_ID_MASK GENMASK(23, 16) 384#define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24) 385#define AX_RXD_ADDR_CAM_VLD BIT(28) 386#define AX_RXD_ADDR_FWD_EN BIT(29) 387#define AX_RXD_RX_PL_MATCH BIT(30) 388 389/* RX WD dword6 */ 390#define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0) 391 392/* RX WD dword7 */ 393#define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0) 394#define AX_RXD_SMART_ANT BIT(16) 395#define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17) 396#define AX_RXD_HDR_CNV BIT(21) 397#define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22) 398#define AX_RXD_BIP_KEYID BIT(27) 399#define AX_RXD_BIP_ENC BIT(28) 400 401struct rtw89_rxinfo_user { 402 __le32 w0; 403}; 404 405#define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0) 406#define RTW89_RXINFO_USER_DATA BIT(1) 407#define RTW89_RXINFO_USER_CTRL BIT(2) 408#define RTW89_RXINFO_USER_MGMT BIT(3) 409#define RTW89_RXINFO_USER_BCM BIT(4) 410#define RTW89_RXINFO_USER_MACID GENMASK(15, 8) 411 412struct rtw89_rxinfo { 413 __le32 w0; 414 __le32 w1; 415 struct rtw89_rxinfo_user user[]; 416} __packed; 417 418#define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0) 419#define RTW89_RXINFO_W0_USR_NUM_V1 GENMASK(4, 0) 420#define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8) 421#define RTW89_RXINFO_W0_PLCP_LEN_V1 GENMASK(23, 16) 422#define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16) 423#define RTW89_RXINFO_W0_INVALID_V1 BIT(27) 424#define RTW89_RXINFO_W0_IS_TO_SELF BIT(28) 425#define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29) 426#define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30) 427#define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0) 428#define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16) 429 430struct rtw89_phy_sts_hdr { 431 __le32 w0; 432 __le32 w1; 433} __packed; 434 435#define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0) 436#define RTW89_PHY_STS_HDR_W0_VALID BIT(7) 437#define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8) 438#define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24) 439#define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0) 440#define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8) 441#define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16) 442#define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24) 443 444struct rtw89_phy_sts_iehdr { 445 __le32 w0; 446}; 447 448#define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0) 449#define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5) 450 451/* BE RXD dword0 */ 452#define BE_RXD_RPKT_LEN_MASK GENMASK(13, 0) 453#define BE_RXD_SHIFT_MASK GENMASK(15, 14) 454#define BE_RXD_DRV_INFO_SZ_MASK GENMASK(19, 18) 455#define BE_RXD_HDR_CNV_SZ_MASK GENMASK(21, 20) 456#define BE_RXD_PHY_RPT_SZ_MASK GENMASK(23, 22) 457#define BE_RXD_RPKT_TYPE_MASK GENMASK(29, 24) 458#define BE_RXD_BB_SEL BIT(30) 459#define BE_RXD_LONG_RXD BIT(31) 460 461/* BE RXD dword1 */ 462#define BE_RXD_PKT_ID_MASK GENMASK(11, 0) 463#define BE_RXD_FWD_TARGET_MASK GENMASK(23, 16) 464#define BE_RXD_BCN_FW_INFO_MASK GENMASK(25, 24) 465#define BE_RXD_FW_RLS BIT(26) 466 467/* BE RXD dword2 */ 468#define BE_RXD_MAC_ID_MASK GENMASK(7, 0) 469#define BE_RXD_TYPE_MASK GENMASK(11, 10) 470#define BE_RXD_LAST_MSDU BIT(12) 471#define BE_RXD_AMSDU_CUT BIT(13) 472#define BE_RXD_ADDR_CAM_VLD BIT(14) 473#define BE_RXD_REORDER BIT(15) 474#define BE_RXD_SEQ_MASK GENMASK(27, 16) 475#define BE_RXD_TID_MASK GENMASK(31, 28) 476 477/* BE RXD dword3 */ 478#define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0) 479#define BE_RXD_BIP_KEYID BIT(4) 480#define BE_RXD_BIP_ENC BIT(5) 481#define BE_RXD_CRC32_ERR BIT(6) 482#define BE_RXD_ICV_ERR BIT(7) 483#define BE_RXD_HW_DEC BIT(8) 484#define BE_RXD_SW_DEC BIT(9) 485#define BE_RXD_A1_MATCH BIT(10) 486#define BE_RXD_AMPDU BIT(11) 487#define BE_RXD_AMPDU_EOF BIT(12) 488#define BE_RXD_AMSDU BIT(13) 489#define BE_RXD_MC BIT(14) 490#define BE_RXD_BC BIT(15) 491#define BE_RXD_MD BIT(16) 492#define BE_RXD_MF BIT(17) 493#define BE_RXD_PWR BIT(18) 494#define BE_RXD_QOS BIT(19) 495#define BE_RXD_EOSP BIT(20) 496#define BE_RXD_HTC BIT(21) 497#define BE_RXD_QNULL BIT(22) 498#define BE_RXD_A4_FRAME BIT(23) 499#define BE_RXD_FRAG_MASK GENMASK(27, 24) 500#define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30) 501 502/* BE RXD dword4 */ 503#define BE_RXD_PPDU_TYPE_MASK GENMASK(7, 0) 504#define BE_RXD_PPDU_CNT_MASK GENMASK(10, 8) 505#define BE_RXD_BW_MASK GENMASK(14, 12) 506#define BE_RXD_RX_GI_LTF_MASK GENMASK(18, 16) 507#define BE_RXD_RX_REORDER_FIELD_EN BIT(19) 508#define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20) 509 510/* BE RXD dword5 */ 511#define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0) 512 513/* BE RXD dword6 */ 514#define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0) 515#define BE_RXD_SR_EN BIT(13) 516#define BE_RXD_NON_SRG_PPDU BIT(14) 517#define BE_RXD_INTER_PPDU BIT(15) 518#define BE_RXD_USER_ID_MASK GENMASK(21, 16) 519#define BE_RXD_RX_STATISTICS BIT(22) 520#define BE_RXD_SMART_ANT BIT(23) 521#define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24) 522 523/* BE RXD dword7 */ 524#define BE_RXD_PATTERN_IDX_MASK GENMASK(4, 0) 525#define BE_RXD_MAGIC_WAKE BIT(5) 526#define BE_RXD_UNICAST_WAKE BIT(6) 527#define BE_RXD_PATTERN_WAKE BIT(7) 528#define BE_RXD_RX_PL_MATCH BIT(8) 529#define BE_RXD_RX_PL_ID_MASK GENMASK(15, 12) 530#define BE_RXD_HDR_CNV BIT(16) 531#define BE_RXD_NAT25_HIT BIT(17) 532#define BE_RXD_IS_DA BIT(18) 533#define BE_RXD_CHKSUM_OFFLOAD_EN BIT(19) 534#define BE_RXD_RXSC_ENTRY_MASK GENMASK(22, 20) 535#define BE_RXD_RXSC_HIT BIT(23) 536#define BE_RXD_WITH_LLC BIT(24) 537#define BE_RXD_RX_AGG_FIELD_EN BIT(25) 538 539/* BE RXD dword8 */ 540#define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0) 541 542/* BE RXD dword9 */ 543#define BE_RXD_MAC_ADDR_H_MASK GENMASK(15, 0) 544#define BE_RXD_HDR_OFFSET_MASK GENMASK(20, 16) 545#define BE_RXD_WL_HD_IV_LEN_MASK GENMASK(26, 21) 546 547struct rtw89_phy_sts_ie0 { 548 __le32 w0; 549 __le32 w1; 550 __le32 w2; 551} __packed; 552 553#define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16) 554#define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8) 555#define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20) 556#define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0) 557#define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8) 558#define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16) 559 560enum rtw89_tx_channel { 561 RTW89_TXCH_ACH0 = 0, 562 RTW89_TXCH_ACH1 = 1, 563 RTW89_TXCH_ACH2 = 2, 564 RTW89_TXCH_ACH3 = 3, 565 RTW89_TXCH_ACH4 = 4, 566 RTW89_TXCH_ACH5 = 5, 567 RTW89_TXCH_ACH6 = 6, 568 RTW89_TXCH_ACH7 = 7, 569 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ 570 RTW89_TXCH_CH9 = 9, /* HI Band 0 */ 571 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ 572 RTW89_TXCH_CH11 = 11, /* HI Band 1 */ 573 RTW89_TXCH_CH12 = 12, /* FW CMD */ 574 575 /* keep last */ 576 RTW89_TXCH_NUM, 577 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 578}; 579 580enum rtw89_rx_channel { 581 RTW89_RXCH_RXQ = 0, 582 RTW89_RXCH_RPQ = 1, 583 584 /* keep last */ 585 RTW89_RXCH_NUM, 586 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 587}; 588 589enum rtw89_tx_qsel { 590 RTW89_TX_QSEL_BE_0 = 0x00, 591 RTW89_TX_QSEL_BK_0 = 0x01, 592 RTW89_TX_QSEL_VI_0 = 0x02, 593 RTW89_TX_QSEL_VO_0 = 0x03, 594 RTW89_TX_QSEL_BE_1 = 0x04, 595 RTW89_TX_QSEL_BK_1 = 0x05, 596 RTW89_TX_QSEL_VI_1 = 0x06, 597 RTW89_TX_QSEL_VO_1 = 0x07, 598 RTW89_TX_QSEL_BE_2 = 0x08, 599 RTW89_TX_QSEL_BK_2 = 0x09, 600 RTW89_TX_QSEL_VI_2 = 0x0a, 601 RTW89_TX_QSEL_VO_2 = 0x0b, 602 RTW89_TX_QSEL_BE_3 = 0x0c, 603 RTW89_TX_QSEL_BK_3 = 0x0d, 604 RTW89_TX_QSEL_VI_3 = 0x0e, 605 RTW89_TX_QSEL_VO_3 = 0x0f, 606 RTW89_TX_QSEL_B0_BCN = 0x10, 607 RTW89_TX_QSEL_B0_HI = 0x11, 608 RTW89_TX_QSEL_B0_MGMT = 0x12, 609 RTW89_TX_QSEL_B0_NOPS = 0x13, 610 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, 611 /* reserved */ 612 /* reserved */ 613 /* reserved */ 614 RTW89_TX_QSEL_B1_BCN = 0x18, 615 RTW89_TX_QSEL_B1_HI = 0x19, 616 RTW89_TX_QSEL_B1_MGMT = 0x1a, 617 RTW89_TX_QSEL_B1_NOPS = 0x1b, 618 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, 619 /* reserved */ 620 /* reserved */ 621 /* reserved */ 622}; 623 624static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) 625{ 626 switch (tid) { 627 default: 628 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 629 fallthrough; 630 case 0: 631 case 3: 632 return RTW89_TX_QSEL_BE_0; 633 case 1: 634 case 2: 635 return RTW89_TX_QSEL_BK_0; 636 case 4: 637 case 5: 638 return RTW89_TX_QSEL_VI_0; 639 case 6: 640 case 7: 641 return RTW89_TX_QSEL_VO_0; 642 } 643} 644 645static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 646{ 647 switch (qsel) { 648 default: 649 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 650 fallthrough; 651 case RTW89_TX_QSEL_BE_0: 652 return RTW89_TXCH_ACH0; 653 case RTW89_TX_QSEL_BK_0: 654 return RTW89_TXCH_ACH1; 655 case RTW89_TX_QSEL_VI_0: 656 return RTW89_TXCH_ACH2; 657 case RTW89_TX_QSEL_VO_0: 658 return RTW89_TXCH_ACH3; 659 case RTW89_TX_QSEL_B0_MGMT: 660 return RTW89_TXCH_CH8; 661 case RTW89_TX_QSEL_B0_HI: 662 return RTW89_TXCH_CH9; 663 case RTW89_TX_QSEL_B1_MGMT: 664 return RTW89_TXCH_CH10; 665 case RTW89_TX_QSEL_B1_HI: 666 return RTW89_TXCH_CH11; 667 } 668} 669 670static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) 671{ 672 switch (tid) { 673 case 3: 674 case 2: 675 case 5: 676 case 7: 677 return 1; 678 default: 679 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 680 fallthrough; 681 case 0: 682 case 1: 683 case 4: 684 case 6: 685 return 0; 686 } 687} 688 689#endif 690