1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2023  Realtek Corporation
3 */
4
5#ifndef __RTW89_8922A_H__
6#define __RTW89_8922A_H__
7
8#include "core.h"
9
10#define RF_PATH_NUM_8922A 2
11#define BB_PATH_NUM_8922A 2
12
13struct rtw8922a_tssi_offset {
14	u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
15	u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
16	u8 rsvd[7];
17	u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
18	u8 bw_diff_5g[10];
19} __packed;
20
21struct rtw8922a_rx_gain {
22	u8 _2g_ofdm;
23	u8 _2g_cck;
24	u8 _5g_low;
25	u8 _5g_mid;
26	u8 _5g_high;
27} __packed;
28
29struct rtw8922a_rx_gain_6g {
30	u8 _6g_l0;
31	u8 _6g_l1;
32	u8 _6g_m0;
33	u8 _6g_m1;
34	u8 _6g_h0;
35	u8 _6g_h1;
36	u8 _6g_uh0;
37	u8 _6g_uh1;
38} __packed;
39
40struct rtw8922a_efuse {
41	u8 country_code[2];
42	u8 rsvd[0xe];
43	struct rtw8922a_tssi_offset path_a_tssi;
44	struct rtw8922a_tssi_offset path_b_tssi;
45	u8 rsvd1[0x54];
46	u8 channel_plan;
47	u8 xtal_k;
48	u8 rsvd2[0x7];
49	u8 board_info;
50	u8 rsvd3[0x8];
51	u8 rfe_type;
52	u8 rsvd4[0x5];
53	u8 path_a_therm;
54	u8 path_b_therm;
55	u8 rsvd5[0x2];
56	struct rtw8922a_rx_gain rx_gain_a;
57	struct rtw8922a_rx_gain rx_gain_b;
58	u8 rsvd6[0x22];
59	u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM];
60	u8 rsvd7[0xa];
61	u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM];
62	u8 rsvd8[0xa];
63	u8 bw40_1s_tssi_6g_c[TSSI_MCS_6G_CH_GROUP_NUM];
64	u8 rsvd9[0xa];
65	u8 bw40_1s_tssi_6g_d[TSSI_MCS_6G_CH_GROUP_NUM];
66	u8 rsvd10[0xa];
67	struct rtw8922a_rx_gain_6g rx_gain_6g_a;
68	struct rtw8922a_rx_gain_6g rx_gain_6g_b;
69} __packed;
70
71extern const struct rtw89_chip_info rtw8922a_chip_info;
72
73#endif
74