1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#ifndef __RTW_PHY_H_ 6#define __RTW_PHY_H_ 7 8#include "debug.h" 9 10extern u8 rtw_cck_rates[]; 11extern u8 rtw_ofdm_rates[]; 12extern u8 rtw_ht_1s_rates[]; 13extern u8 rtw_ht_2s_rates[]; 14extern u8 rtw_vht_1s_rates[]; 15extern u8 rtw_vht_2s_rates[]; 16extern u8 *rtw_rate_section[]; 17extern u8 rtw_rate_size[]; 18 19void rtw_phy_init(struct rtw_dev *rtwdev); 20void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev); 21u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num); 22u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 23 u32 addr, u32 mask); 24u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 25 u32 addr, u32 mask); 26bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 27 u32 addr, u32 mask, u32 data); 28bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 29 u32 addr, u32 mask, u32 data); 30bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 31 u32 addr, u32 mask, u32 data); 32void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg); 33void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 34void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 35void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 36void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 37 u32 addr, u32 data); 38void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 39 u32 addr, u32 data); 40void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 41 u32 addr, u32 data); 42void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 43 u32 addr, u32 data); 44void rtw_phy_init_tx_power(struct rtw_dev *rtwdev); 45void rtw_phy_load_tables(struct rtw_dev *rtwdev); 46u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate, 47 enum rtw_bandwidth bw, u8 channel, u8 regd); 48void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel); 49void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal); 50void rtw_phy_tx_power_limit_config(struct rtw_hal *hal); 51void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path); 52bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal, 53 u8 path); 54u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path); 55s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev, 56 struct rtw_swing_table *swing_table, 57 u8 tbl_path, u8 therm_path, u8 delta); 58bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev); 59bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev); 60void rtw_phy_config_swing_table(struct rtw_dev *rtwdev, 61 struct rtw_swing_table *swing_table); 62void rtw_phy_set_edcca_th(struct rtw_dev *rtwdev, u8 l2h, u8 h2l); 63void rtw_phy_adaptivity_set_mode(struct rtw_dev *rtwdev); 64void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev, 65 struct rtw_rx_pkt_stat *pkt_stat); 66void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev); 67 68struct rtw_txpwr_lmt_cfg_pair { 69 u8 regd; 70 u8 band; 71 u8 bw; 72 u8 rs; 73 u8 ch; 74 s8 txpwr_lmt; 75}; 76 77struct rtw_phy_pg_cfg_pair { 78 u32 band; 79 u32 rf_path; 80 u32 tx_num; 81 u32 addr; 82 u32 bitmask; 83 u32 data; 84}; 85 86#define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \ 87const struct rtw_table name ## _tbl = { \ 88 .data = name, \ 89 .size = ARRAY_SIZE(name), \ 90 .parse = rtw_parse_tbl_phy_cond, \ 91 .do_cfg = cfg, \ 92 .rf_path = path, \ 93} 94 95#define RTW_DECL_TABLE_PHY_COND(name, cfg) \ 96 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0) 97 98#define RTW_DECL_TABLE_RF_RADIO(name, path) \ 99 RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path) 100 101#define RTW_DECL_TABLE_BB_PG(name) \ 102const struct rtw_table name ## _tbl = { \ 103 .data = name, \ 104 .size = ARRAY_SIZE(name), \ 105 .parse = rtw_parse_tbl_bb_pg, \ 106} 107 108#define RTW_DECL_TABLE_TXPWR_LMT(name) \ 109const struct rtw_table name ## _tbl = { \ 110 .data = name, \ 111 .size = ARRAY_SIZE(name), \ 112 .parse = rtw_parse_tbl_txpwr_lmt, \ 113} 114 115static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev) 116{ 117 const struct rtw_chip_info *chip = rtwdev->chip; 118 struct rtw_efuse *efuse = &rtwdev->efuse; 119 const struct rtw_rfe_def *rfe_def = NULL; 120 121 if (chip->rfe_defs_size == 0) 122 return NULL; 123 124 if (efuse->rfe_option < chip->rfe_defs_size) 125 rfe_def = &chip->rfe_defs[efuse->rfe_option]; 126 127 rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option); 128 return rfe_def; 129} 130 131static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev) 132{ 133 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 134 135 if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) { 136 rtw_err(rtwdev, "rfe %d isn't supported\n", 137 rtwdev->efuse.rfe_option); 138 return -ENODEV; 139 } 140 141 return 0; 142} 143 144void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi); 145 146struct rtw_power_params { 147 u8 pwr_base; 148 s8 pwr_offset; 149 s8 pwr_limit; 150 s8 pwr_remnant; 151 s8 pwr_sar; 152}; 153 154void 155rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, 156 u8 rate, u8 bw, u8 ch, u8 regd, 157 struct rtw_power_params *pwr_param); 158 159enum rtw_phy_cck_pd_lv { 160 CCK_PD_LV0, 161 CCK_PD_LV1, 162 CCK_PD_LV2, 163 CCK_PD_LV3, 164 CCK_PD_LV4, 165 CCK_PD_LV_MAX, 166}; 167 168#define MASKBYTE0 0xff 169#define MASKBYTE1 0xff00 170#define MASKBYTE2 0xff0000 171#define MASKBYTE3 0xff000000 172#define MASKHWORD 0xffff0000 173#define MASKLWORD 0x0000ffff 174#define MASKDWORD 0xffffffff 175#define RFREG_MASK 0xfffff 176 177#define MASK7BITS 0x7f 178#define MASK12BITS 0xfff 179#define MASKH4BITS 0xf0000000 180#define MASK20BITS 0xfffff 181#define MASK24BITS 0xffffff 182 183#define MASKH3BYTES 0xffffff00 184#define MASKL3BYTES 0x00ffffff 185#define MASKBYTE2HIGHNIBBLE 0x00f00000 186#define MASKBYTE3LOWNIBBLE 0x0f000000 187#define MASKL3BYTES 0x00ffffff 188 189#define CCK_FA_AVG_RESET 0xffffffff 190 191#define LSSI_READ_ADDR_MASK 0x7f800000 192#define LSSI_READ_EDGE_MASK 0x80000000 193#define LSSI_READ_DATA_MASK 0xfffff 194 195#define RRSR_RATE_ORDER_MAX 0xfffff 196#define RRSR_RATE_ORDER_CCK_LEN 4 197 198#endif 199