1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2009-2013 Realtek Corporation.*/ 3 4#ifndef __RTL92C_REG_H__ 5#define __RTL92C_REG_H__ 6 7#define TXPKT_BUF_SELECT 0x69 8#define RXPKT_BUF_SELECT 0xA5 9#define DISABLE_TRXPKT_BUF_ACCESS 0x0 10 11#define REG_SYS_ISO_CTRL 0x0000 12#define REG_SYS_FUNC_EN 0x0002 13#define REG_APS_FSMCO 0x0004 14#define REG_SYS_CLKR 0x0008 15#define REG_9346CR 0x000A 16#define REG_EE_VPD 0x000C 17#define REG_AFE_MISC 0x0010 18#define REG_SPS0_CTRL 0x0011 19#define REG_SPS_OCP_CFG 0x0018 20#define REG_RSV_CTRL 0x001C 21#define REG_RF_CTRL 0x001F 22#define REG_LDOA15_CTRL 0x0020 23#define REG_LDOV12D_CTRL 0x0021 24#define REG_LDOHCI12_CTRL 0x0022 25#define REG_LPLDO_CTRL 0x0023 26#define REG_AFE_XTAL_CTRL 0x0024 27/* 1.5v for 8188EE test chip, 1.4v for MP chip */ 28#define REG_AFE_LDO_CTRL 0x0027 29#define REG_AFE_PLL_CTRL 0x0028 30#define REG_EFUSE_CTRL 0x0030 31#define REG_EFUSE_TEST 0x0034 32#define REG_PWR_DATA 0x0038 33#define REG_CAL_TIMER 0x003C 34#define REG_ACLK_MON 0x003E 35#define REG_GPIO_MUXCFG 0x0040 36#define REG_GPIO_IO_SEL 0x0042 37#define REG_MAC_PINMUX_CFG 0x0043 38#define REG_GPIO_PIN_CTRL 0x0044 39#define REG_GPIO_INTM 0x0048 40#define REG_LEDCFG0 0x004C 41#define REG_LEDCFG1 0x004D 42#define REG_LEDCFG2 0x004E 43#define REG_LEDCFG3 0x004F 44#define REG_FSIMR 0x0050 45#define REG_FSISR 0x0054 46#define REG_HSIMR 0x0058 47#define REG_HSISR 0x005c 48#define REG_GPIO_PIN_CTRL_2 0x0060 49#define REG_GPIO_IO_SEL_2 0x0062 50#define REG_GPIO_OUTPUT 0x006c 51#define REG_AFE_XTAL_CTRL_EXT 0x0078 52#define REG_XCK_OUT_CTRL 0x007c 53#define REG_MCUFWDL 0x0080 54#define REG_WOL_EVENT 0x0081 55#define REG_MCUTSTCFG 0x0084 56 57#define REG_HIMR 0x00B0 58#define REG_HISR 0x00B4 59#define REG_HIMRE 0x00B8 60#define REG_HISRE 0x00BC 61 62#define REG_EFUSE_ACCESS 0x00CF 63 64#define REG_BIST_SCAN 0x00D0 65#define REG_BIST_RPT 0x00D4 66#define REG_BIST_ROM_RPT 0x00D8 67#define REG_USB_SIE_INTF 0x00E0 68#define REG_PCIE_MIO_INTF 0x00E4 69#define REG_PCIE_MIO_INTD 0x00E8 70#define REG_HPON_FSM 0x00EC 71#define REG_SYS_CFG 0x00F0 72 73#define REG_CR 0x0100 74#define REG_PBP 0x0104 75#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 76#define REG_TRXDMA_CTRL 0x010C 77#define REG_TRXFF_BNDY 0x0114 78#define REG_TRXFF_STATUS 0x0118 79#define REG_RXFF_PTR 0x011C 80 81#define REG_CPWM 0x012F 82#define REG_FWIMR 0x0130 83#define REG_FWISR 0x0134 84#define REG_PKTBUF_DBG_CTRL 0x0140 85#define REG_PKTBUF_DBG_DATA_L 0x0144 86#define REG_PKTBUF_DBG_DATA_H 0x0148 87#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 88 89#define REG_TC0_CTRL 0x0150 90#define REG_TC1_CTRL 0x0154 91#define REG_TC2_CTRL 0x0158 92#define REG_TC3_CTRL 0x015C 93#define REG_TC4_CTRL 0x0160 94#define REG_TCUNIT_BASE 0x0164 95#define REG_MBIST_START 0x0174 96#define REG_MBIST_DONE 0x0178 97#define REG_MBIST_FAIL 0x017C 98#define REG_32K_CTRL 0x0194 99#define REG_C2HEVT_MSG_NORMAL 0x01A0 100#define REG_C2HEVT_CLEAR 0x01AF 101#define REG_C2HEVT_MSG_TEST 0x01B8 102#define REG_MCUTST_1 0x01c0 103#define REG_FMETHR 0x01C8 104#define REG_HMETFR 0x01CC 105#define REG_HMEBOX_0 0x01D0 106#define REG_HMEBOX_1 0x01D4 107#define REG_HMEBOX_2 0x01D8 108#define REG_HMEBOX_3 0x01DC 109 110#define REG_LLT_INIT 0x01E0 111#define REG_BB_ACCEESS_CTRL 0x01E8 112#define REG_BB_ACCESS_DATA 0x01EC 113 114#define REG_HMEBOX_EXT_0 0x01F0 115#define REG_HMEBOX_EXT_1 0x01F4 116#define REG_HMEBOX_EXT_2 0x01F8 117#define REG_HMEBOX_EXT_3 0x01FC 118 119#define REG_RQPN 0x0200 120#define REG_FIFOPAGE 0x0204 121#define REG_TDECTRL 0x0208 122#define REG_TXDMA_OFFSET_CHK 0x020C 123#define REG_TXDMA_STATUS 0x0210 124#define REG_RQPN_NPQ 0x0214 125 126#define REG_RXDMA_AGG_PG_TH 0x0280 127/* FW shall update this register before 128 * FW write RXPKT_RELEASE_POLL to 1 129 */ 130#define REG_FW_UPD_RDPTR 0x0284 131/* Control the RX DMA.*/ 132#define REG_RXDMA_CONTROL 0x0286 133/* The number of packets in RXPKTBUF. */ 134#define REG_RXPKT_NUM 0x0287 135 136#define REG_PCIE_CTRL_REG 0x0300 137#define REG_INT_MIG 0x0304 138#define REG_BCNQ_DESA 0x0308 139#define REG_HQ_DESA 0x0310 140#define REG_MGQ_DESA 0x0318 141#define REG_VOQ_DESA 0x0320 142#define REG_VIQ_DESA 0x0328 143#define REG_BEQ_DESA 0x0330 144#define REG_BKQ_DESA 0x0338 145#define REG_RX_DESA 0x0340 146 147#define REG_DBI 0x0348 148#define REG_MDIO 0x0354 149#define REG_DBG_SEL 0x0360 150#define REG_PCIE_HRPWM 0x0361 151#define REG_PCIE_HCPWM 0x0363 152#define REG_UART_CTRL 0x0364 153#define REG_WATCH_DOG 0x0368 154#define REG_UART_TX_DESA 0x0370 155#define REG_UART_RX_DESA 0x0378 156 157#define REG_HDAQ_DESA_NODEF 0x0000 158#define REG_CMDQ_DESA_NODEF 0x0000 159 160#define REG_VOQ_INFORMATION 0x0400 161#define REG_VIQ_INFORMATION 0x0404 162#define REG_BEQ_INFORMATION 0x0408 163#define REG_BKQ_INFORMATION 0x040C 164#define REG_MGQ_INFORMATION 0x0410 165#define REG_HGQ_INFORMATION 0x0414 166#define REG_BCNQ_INFORMATION 0x0418 167#define REG_TXPKT_EMPTY 0x041A 168 169#define REG_CPU_MGQ_INFORMATION 0x041C 170#define REG_FWHW_TXQ_CTRL 0x0420 171#define REG_HWSEQ_CTRL 0x0423 172#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 173#define REG_TXPKTBUF_MGQ_BDNY 0x0425 174#define REG_MULTI_BCNQ_EN 0x0426 175#define REG_MULTI_BCNQ_OFFSET 0x0427 176#define REG_SPEC_SIFS 0x0428 177#define REG_RL 0x042A 178#define REG_DARFRC 0x0430 179#define REG_RARFRC 0x0438 180#define REG_RRSR 0x0440 181#define REG_ARFR0 0x0444 182#define REG_ARFR1 0x0448 183#define REG_ARFR2 0x044C 184#define REG_ARFR3 0x0450 185#define REG_AGGLEN_LMT 0x0458 186#define REG_AMPDU_MIN_SPACE 0x045C 187#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 188#define REG_FAST_EDCA_CTRL 0x0460 189#define REG_RD_RESP_PKT_TH 0x0463 190#define REG_INIRTS_RATE_SEL 0x0480 191#define REG_INIDATA_RATE_SEL 0x0484 192#define REG_POWER_STATUS 0x04A4 193#define REG_POWER_STAGE1 0x04B4 194#define REG_POWER_STAGE2 0x04B8 195#define REG_PKT_LIFE_TIME 0x04C0 196#define REG_STBC_SETTING 0x04C4 197#define REG_PROT_MODE_CTRL 0x04C8 198#define REG_BAR_MODE_CTRL 0x04CC 199#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 200#define REG_EARLY_MODE_CONTROL 0x04D0 201#define REG_NQOS_SEQ 0x04DC 202#define REG_QOS_SEQ 0x04DE 203#define REG_NEED_CPU_HANDLE 0x04E0 204#define REG_PKT_LOSE_RPT 0x04E1 205#define REG_PTCL_ERR_STATUS 0x04E2 206#define REG_TX_RPT_CTRL 0x04EC 207#define REG_TX_RPT_TIME 0x04F0 208#define REG_DUMMY 0x04FC 209 210#define REG_EDCA_VO_PARAM 0x0500 211#define REG_EDCA_VI_PARAM 0x0504 212#define REG_EDCA_BE_PARAM 0x0508 213#define REG_EDCA_BK_PARAM 0x050C 214#define REG_BCNTCFG 0x0510 215#define REG_PIFS 0x0512 216#define REG_RDG_PIFS 0x0513 217#define REG_SIFS_CTX 0x0514 218#define REG_SIFS_TRX 0x0516 219#define REG_AGGR_BREAK_TIME 0x051A 220#define REG_SLOT 0x051B 221#define REG_TX_PTCL_CTRL 0x0520 222#define REG_TXPAUSE 0x0522 223#define REG_DIS_TXREQ_CLR 0x0523 224#define REG_RD_CTRL 0x0524 225#define REG_TBTT_PROHIBIT 0x0540 226#define REG_RD_NAV_NXT 0x0544 227#define REG_NAV_PROT_LEN 0x0546 228#define REG_BCN_CTRL 0x0550 229#define REG_MBID_NUM 0x0552 230#define REG_DUAL_TSF_RST 0x0553 231#define REG_BCN_INTERVAL 0x0554 232#define REG_MBSSID_BCN_SPACE 0x0554 233#define REG_DRVERLYINT 0x0558 234#define REG_BCNDMATIM 0x0559 235#define REG_ATIMWND 0x055A 236#define REG_USTIME_TSF 0x055C 237#define REG_BCN_MAX_ERR 0x055D 238#define REG_RXTSF_OFFSET_CCK 0x055E 239#define REG_RXTSF_OFFSET_OFDM 0x055F 240#define REG_TSFTR 0x0560 241#define REG_INIT_TSFTR 0x0564 242#define REG_PSTIMER 0x0580 243#define REG_TIMER0 0x0584 244#define REG_TIMER1 0x0588 245#define REG_ACMHWCTRL 0x05C0 246#define REG_ACMRSTCTRL 0x05C1 247#define REG_ACMAVG 0x05C2 248#define REG_VO_ADMTIME 0x05C4 249#define REG_VI_ADMTIME 0x05C6 250#define REG_BE_ADMTIME 0x05C8 251#define REG_EDCA_RANDOM_GEN 0x05CC 252#define REG_SCH_TXCMD 0x05D0 253 254#define REG_APSD_CTRL 0x0600 255#define REG_BWOPMODE 0x0603 256#define REG_TCR 0x0604 257#define REG_RCR 0x0608 258#define REG_RX_PKT_LIMIT 0x060C 259#define REG_RX_DLK_TIME 0x060D 260#define REG_RX_DRVINFO_SZ 0x060F 261 262#define REG_MACID 0x0610 263#define REG_BSSID 0x0618 264#define REG_MAR 0x0620 265#define REG_MBIDCAMCFG 0x0628 266 267#define REG_USTIME_EDCA 0x0638 268#define REG_MAC_SPEC_SIFS 0x063A 269#define REG_RESP_SIFS_CCK 0x063C 270#define REG_RESP_SIFS_OFDM 0x063E 271#define REG_ACKTO 0x0640 272#define REG_CTS2TO 0x0641 273#define REG_EIFS 0x0642 274 275#define REG_NAV_CTRL 0x0650 276#define REG_BACAMCMD 0x0654 277#define REG_BACAMCONTENT 0x0658 278#define REG_LBDLY 0x0660 279#define REG_FWDLY 0x0661 280#define REG_RXERR_RPT 0x0664 281#define REG_TRXPTCL_CTL 0x0668 282 283#define REG_CAMCMD 0x0670 284#define REG_CAMWRITE 0x0674 285#define REG_CAMREAD 0x0678 286#define REG_CAMDBG 0x067C 287#define REG_SECCFG 0x0680 288 289#define REG_WOW_CTRL 0x0690 290#define REG_PSSTATUS 0x0691 291#define REG_PS_RX_INFO 0x0692 292#define REG_UAPSD_TID 0x0693 293#define REG_LPNAV_CTRL 0x0694 294#define REG_WKFMCAM_NUM 0x0698 295#define REG_WKFMCAM_RWD 0x069C 296#define REG_RXFLTMAP0 0x06A0 297#define REG_RXFLTMAP1 0x06A2 298#define REG_RXFLTMAP2 0x06A4 299#define REG_BCN_PSR_RPT 0x06A8 300#define REG_CALB32K_CTRL 0x06AC 301#define REG_PKT_MON_CTRL 0x06B4 302#define REG_BT_COEX_TABLE 0x06C0 303#define REG_WMAC_RESP_TXINFO 0x06D8 304 305#define REG_USB_INFO 0xFE17 306#define REG_USB_SPECIAL_OPTION 0xFE55 307#define REG_USB_DMA_AGG_TO 0xFE5B 308#define REG_USB_AGG_TO 0xFE5C 309#define REG_USB_AGG_TH 0xFE5D 310 311#define REG_TEST_USB_TXQS 0xFE48 312#define REG_TEST_SIE_VID 0xFE60 313#define REG_TEST_SIE_PID 0xFE62 314#define REG_TEST_SIE_OPTIONAL 0xFE64 315#define REG_TEST_SIE_CHIRP_K 0xFE65 316#define REG_TEST_SIE_PHY 0xFE66 317#define REG_TEST_SIE_MAC_ADDR 0xFE70 318#define REG_TEST_SIE_STRING 0xFE80 319 320#define REG_NORMAL_SIE_VID 0xFE60 321#define REG_NORMAL_SIE_PID 0xFE62 322#define REG_NORMAL_SIE_OPTIONAL 0xFE64 323#define REG_NORMAL_SIE_EP 0xFE65 324#define REG_NORMAL_SIE_PHY 0xFE68 325#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 326#define REG_NORMAL_SIE_STRING 0xFE80 327 328#define CR9346 REG_9346CR 329#define MSR (REG_CR + 2) 330#define ISR REG_HISR 331#define TSFR REG_TSFTR 332 333#define MACIDR0 REG_MACID 334#define MACIDR4 (REG_MACID + 4) 335 336#define PBP REG_PBP 337 338#define IDR0 MACIDR0 339#define IDR4 MACIDR4 340 341#define UNUSED_REGISTER 0x1BF 342#define DCAM UNUSED_REGISTER 343#define PSR UNUSED_REGISTER 344#define BBADDR UNUSED_REGISTER 345#define PHYDATAR UNUSED_REGISTER 346 347#define INVALID_BBRF_VALUE 0x12345678 348 349#define MAX_MSS_DENSITY_2T 0x13 350#define MAX_MSS_DENSITY_1T 0x0A 351 352#define CMDEEPROM_EN BIT(5) 353#define CMDEEPROM_SEL BIT(4) 354#define CMD9346CR_9356SEL BIT(4) 355#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 356#define AUTOLOAD_EFUSE CMDEEPROM_EN 357 358#define GPIOSEL_GPIO 0 359#define GPIOSEL_ENBT BIT(5) 360 361#define GPIO_IN REG_GPIO_PIN_CTRL 362#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 363#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 364#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 365 366/*8723/8188E Host System Interrupt 367 *Mask Register (offset 0x58, 32 byte) 368 */ 369#define HSIMR_GPIO12_0_INT_EN BIT(0) 370#define HSIMR_SPS_OCP_INT_EN BIT(5) 371#define HSIMR_RON_INT_EN BIT(6) 372#define HSIMR_PDN_INT_EN BIT(7) 373#define HSIMR_GPIO9_INT_EN BIT(25) 374 375/* 8723/8188E Host System Interrupt 376 * Status Register (offset 0x5C, 32 byte) 377 */ 378#define HSISR_GPIO12_0_INT BIT(0) 379#define HSISR_SPS_OCP_INT BIT(5) 380#define HSISR_RON_INT_EN BIT(6) 381#define HSISR_PDNINT BIT(7) 382#define HSISR_GPIO9_INT BIT(25) 383 384#define MSR_NOLINK 0x00 385#define MSR_ADHOC 0x01 386#define MSR_INFRA 0x02 387#define MSR_AP 0x03 388 389#define RRSR_RSC_OFFSET 21 390#define RRSR_SHORT_OFFSET 23 391#define RRSR_RSC_BW_40M 0x600000 392#define RRSR_RSC_UPSUBCHNL 0x400000 393#define RRSR_RSC_LOWSUBCHNL 0x200000 394#define RRSR_SHORT 0x800000 395#define RRSR_1M BIT(0) 396#define RRSR_2M BIT(1) 397#define RRSR_5_5M BIT(2) 398#define RRSR_11M BIT(3) 399#define RRSR_6M BIT(4) 400#define RRSR_9M BIT(5) 401#define RRSR_12M BIT(6) 402#define RRSR_18M BIT(7) 403#define RRSR_24M BIT(8) 404#define RRSR_36M BIT(9) 405#define RRSR_48M BIT(10) 406#define RRSR_54M BIT(11) 407#define RRSR_MCS0 BIT(12) 408#define RRSR_MCS1 BIT(13) 409#define RRSR_MCS2 BIT(14) 410#define RRSR_MCS3 BIT(15) 411#define RRSR_MCS4 BIT(16) 412#define RRSR_MCS5 BIT(17) 413#define RRSR_MCS6 BIT(18) 414#define RRSR_MCS7 BIT(19) 415#define BRSR_ACKSHORTPMB BIT(23) 416 417#define RATR_1M 0x00000001 418#define RATR_2M 0x00000002 419#define RATR_55M 0x00000004 420#define RATR_11M 0x00000008 421#define RATR_6M 0x00000010 422#define RATR_9M 0x00000020 423#define RATR_12M 0x00000040 424#define RATR_18M 0x00000080 425#define RATR_24M 0x00000100 426#define RATR_36M 0x00000200 427#define RATR_48M 0x00000400 428#define RATR_54M 0x00000800 429#define RATR_MCS0 0x00001000 430#define RATR_MCS1 0x00002000 431#define RATR_MCS2 0x00004000 432#define RATR_MCS3 0x00008000 433#define RATR_MCS4 0x00010000 434#define RATR_MCS5 0x00020000 435#define RATR_MCS6 0x00040000 436#define RATR_MCS7 0x00080000 437#define RATR_MCS8 0x00100000 438#define RATR_MCS9 0x00200000 439#define RATR_MCS10 0x00400000 440#define RATR_MCS11 0x00800000 441#define RATR_MCS12 0x01000000 442#define RATR_MCS13 0x02000000 443#define RATR_MCS14 0x04000000 444#define RATR_MCS15 0x08000000 445 446#define RATE_1M BIT(0) 447#define RATE_2M BIT(1) 448#define RATE_5_5M BIT(2) 449#define RATE_11M BIT(3) 450#define RATE_6M BIT(4) 451#define RATE_9M BIT(5) 452#define RATE_12M BIT(6) 453#define RATE_18M BIT(7) 454#define RATE_24M BIT(8) 455#define RATE_36M BIT(9) 456#define RATE_48M BIT(10) 457#define RATE_54M BIT(11) 458#define RATE_MCS0 BIT(12) 459#define RATE_MCS1 BIT(13) 460#define RATE_MCS2 BIT(14) 461#define RATE_MCS3 BIT(15) 462#define RATE_MCS4 BIT(16) 463#define RATE_MCS5 BIT(17) 464#define RATE_MCS6 BIT(18) 465#define RATE_MCS7 BIT(19) 466#define RATE_MCS8 BIT(20) 467#define RATE_MCS9 BIT(21) 468#define RATE_MCS10 BIT(22) 469#define RATE_MCS11 BIT(23) 470#define RATE_MCS12 BIT(24) 471#define RATE_MCS13 BIT(25) 472#define RATE_MCS14 BIT(26) 473#define RATE_MCS15 BIT(27) 474 475#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 476#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 477 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 478#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\ 479 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\ 480 RATR_MCS6 | RATR_MCS7) 481#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\ 482 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\ 483 RATR_MCS14 | RATR_MCS15) 484 485#define BW_OPMODE_20MHZ BIT(2) 486#define BW_OPMODE_5G BIT(1) 487#define BW_OPMODE_11J BIT(0) 488 489#define CAM_VALID BIT(15) 490#define CAM_NOTVALID 0x0000 491#define CAM_USEDK BIT(5) 492 493#define CAM_NONE 0x0 494#define CAM_WEP40 0x01 495#define CAM_TKIP 0x02 496#define CAM_AES 0x04 497#define CAM_WEP104 0x05 498 499#define TOTAL_CAM_ENTRY 32 500#define HALF_CAM_ENTRY 16 501 502#define CAM_WRITE BIT(16) 503#define CAM_READ 0x00000000 504#define CAM_POLLINIG BIT(31) 505 506#define SCR_USEDK 0x01 507#define SCR_TXSEC_ENABLE 0x02 508#define SCR_RXSEC_ENABLE 0x04 509 510#define WOW_PMEN BIT(0) 511#define WOW_WOMEN BIT(1) 512#define WOW_MAGIC BIT(2) 513#define WOW_UWF BIT(3) 514 515/********************************************* 516* 8188 IMR/ISR bits 517**********************************************/ 518#define IMR_DISABLED 0x0 519/* IMR DW0(0x0060-0063) Bit 0-31 */ 520/* TXRPT interrupt when CCX bit of the packet is set */ 521#define IMR_TXCCK BIT(30) 522/* Power Save Time Out Interrupt */ 523#define IMR_PSTIMEOUT BIT(29) 524/* When GTIMER4 expires, this bit is set to 1 */ 525#define IMR_GTINT4 BIT(28) 526/* When GTIMER3 expires, this bit is set to 1 */ 527#define IMR_GTINT3 BIT(27) 528/* Transmit Beacon0 Error */ 529#define IMR_TBDER BIT(26) 530/* Transmit Beacon0 OK */ 531#define IMR_TBDOK BIT(25) 532/* TSF Timer BIT32 toggle indication interrupt */ 533#define IMR_TSF_BIT32_TOGGLE BIT(24) 534/* Beacon DMA Interrupt 0 */ 535#define IMR_BCNDMAINT0 BIT(20) 536/* Beacon Queue DMA OK0 */ 537#define IMR_BCNDOK0 BIT(16) 538/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 539#define IMR_HSISR_IND_ON_INT BIT(15) 540/* Beacon DMA Interrupt Extension for Win7 */ 541#define IMR_BCNDMAINT_E BIT(14) 542/* CTWidnow End or ATIM Window End */ 543#define IMR_ATIMEND BIT(12) 544/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/ 545#define IMR_HISR1_IND_INT BIT(11) 546/* CPU to Host Command INT Status, Write 1 clear */ 547#define IMR_C2HCMD BIT(10) 548/* CPU power Mode exchange INT Status, Write 1 clear */ 549#define IMR_CPWM2 BIT(9) 550/* CPU power Mode exchange INT Status, Write 1 clear */ 551#define IMR_CPWM BIT(8) 552/* High Queue DMA OK */ 553#define IMR_HIGHDOK BIT(7) 554/* Management Queue DMA OK */ 555#define IMR_MGNTDOK BIT(6) 556/* AC_BK DMA OK */ 557#define IMR_BKDOK BIT(5) 558/* AC_BE DMA OK */ 559#define IMR_BEDOK BIT(4) 560/* AC_VI DMA OK */ 561#define IMR_VIDOK BIT(3) 562/* AC_VO DMA OK */ 563#define IMR_VODOK BIT(2) 564/* Rx Descriptor Unavailable */ 565#define IMR_RDU BIT(1) 566/* Receive DMA OK */ 567#define IMR_ROK BIT(0) 568 569/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 570/* Beacon DMA Interrupt 7 */ 571#define IMR_BCNDMAINT7 BIT(27) 572/* Beacon DMA Interrupt 6 */ 573#define IMR_BCNDMAINT6 BIT(26) 574/* Beacon DMA Interrupt 5 */ 575#define IMR_BCNDMAINT5 BIT(25) 576/* Beacon DMA Interrupt 4 */ 577#define IMR_BCNDMAINT4 BIT(24) 578/* Beacon DMA Interrupt 3 */ 579#define IMR_BCNDMAINT3 BIT(23) 580/* Beacon DMA Interrupt 2 */ 581#define IMR_BCNDMAINT2 BIT(22) 582/* Beacon DMA Interrupt 1 */ 583#define IMR_BCNDMAINT1 BIT(21) 584/* Beacon Queue DMA OK Interrup 7 */ 585#define IMR_BCNDOK7 BIT(20) 586/* Beacon Queue DMA OK Interrup 6 */ 587#define IMR_BCNDOK6 BIT(19) 588/* Beacon Queue DMA OK Interrup 5 */ 589#define IMR_BCNDOK5 BIT(18) 590/* Beacon Queue DMA OK Interrup 4 */ 591#define IMR_BCNDOK4 BIT(17) 592/* Beacon Queue DMA OK Interrup 3 */ 593#define IMR_BCNDOK3 BIT(16) 594/* Beacon Queue DMA OK Interrup 2 */ 595#define IMR_BCNDOK2 BIT(15) 596/* Beacon Queue DMA OK Interrup 1 */ 597#define IMR_BCNDOK1 BIT(14) 598/* ATIM Window End Extension for Win7 */ 599#define IMR_ATIMEND_E BIT(13) 600/* Tx Error Flag Interrupt Status, write 1 clear. */ 601#define IMR_TXERR BIT(11) 602/* Rx Error Flag INT Status, Write 1 clear */ 603#define IMR_RXERR BIT(10) 604/* Transmit FIFO Overflow */ 605#define IMR_TXFOVW BIT(9) 606/* Receive FIFO Overflow */ 607#define IMR_RXFOVW BIT(8) 608 609#define HWSET_MAX_SIZE 512 610#define EFUSE_MAX_SECTION 64 611#define EFUSE_REAL_CONTENT_LEN 256 612/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/ 613#define EFUSE_OOB_PROTECT_BYTES 18 614 615#define EEPROM_DEFAULT_TSSI 0x0 616#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 617#define EEPROM_DEFAULT_CRYSTALCAP 0x5 618#define EEPROM_DEFAULT_BOARDTYPE 0x02 619#define EEPROM_DEFAULT_TXPOWER 0x1010 620#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 621 622#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 623#define EEPROM_DEFAULT_THERMALMETER 0x18 624#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 625#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 626#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 627#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 628#define EEPROM_DEFAULT_HT20_DIFF 2 629#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 630#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 631#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 632 633#define RF_OPTION1 0x79 634#define RF_OPTION2 0x7A 635#define RF_OPTION3 0x7B 636#define RF_OPTION4 0x7C 637 638#define EEPROM_DEFAULT_PID 0x1234 639#define EEPROM_DEFAULT_VID 0x5678 640#define EEPROM_DEFAULT_CUSTOMERID 0xAB 641#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 642#define EEPROM_DEFAULT_VERSION 0 643 644#define EEPROM_CHANNEL_PLAN_FCC 0x0 645#define EEPROM_CHANNEL_PLAN_IC 0x1 646#define EEPROM_CHANNEL_PLAN_ETSI 0x2 647#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 648#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 649#define EEPROM_CHANNEL_PLAN_MKK 0x5 650#define EEPROM_CHANNEL_PLAN_MKK1 0x6 651#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 652#define EEPROM_CHANNEL_PLAN_TELEC 0x8 653#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 654#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 655#define EEPROM_CHANNEL_PLAN_NCC 0xB 656#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 657 658#define EEPROM_CID_DEFAULT 0x0 659#define EEPROM_CID_TOSHIBA 0x4 660#define EEPROM_CID_CCX 0x10 661#define EEPROM_CID_QMI 0x0D 662#define EEPROM_CID_WHQL 0xFE 663 664#define RTL8188E_EEPROM_ID 0x8129 665 666#define EEPROM_HPON 0x02 667#define EEPROM_CLK 0x06 668#define EEPROM_TESTR 0x08 669 670#define EEPROM_TXPOWERCCK 0x10 671#define EEPROM_TXPOWERHT40_1S 0x16 672#define EEPROM_TXPOWERHT20DIFF 0x1B 673#define EEPROM_TXPOWER_OFDMDIFF 0x1B 674 675#define EEPROM_TX_PWR_INX 0x10 676 677#define EEPROM_CHANNELPLAN 0xB8 678#define EEPROM_XTAL_88E 0xB9 679#define EEPROM_THERMAL_METER_88E 0xBA 680#define EEPROM_IQK_LCK_88E 0xBB 681 682#define EEPROM_RF_BOARD_OPTION_88E 0xC1 683#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 684#define EEPROM_RF_BT_SETTING_88E 0xC3 685#define EEPROM_VERSION 0xC4 686#define EEPROM_CUSTOMER_ID 0xC5 687#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 688 689#define EEPROM_MAC_ADDR 0xD0 690#define EEPROM_VID 0xD6 691#define EEPROM_DID 0xD8 692#define EEPROM_SVID 0xDA 693#define EEPROM_SMID 0xDC 694 695#define STOPBECON BIT(6) 696#define STOPHIGHT BIT(5) 697#define STOPMGT BIT(4) 698#define STOPVO BIT(3) 699#define STOPVI BIT(2) 700#define STOPBE BIT(1) 701#define STOPBK BIT(0) 702 703#define RCR_APPFCS BIT(31) 704#define RCR_APP_MIC BIT(30) 705#define RCR_APP_ICV BIT(29) 706#define RCR_APP_PHYST_RXFF BIT(28) 707#define RCR_APP_BA_SSN BIT(27) 708#define RCR_ENMBID BIT(24) 709#define RCR_LSIGEN BIT(23) 710#define RCR_MFBEN BIT(22) 711#define RCR_HTC_LOC_CTRL BIT(14) 712#define RCR_AMF BIT(13) 713#define RCR_ACF BIT(12) 714#define RCR_ADF BIT(11) 715#define RCR_AICV BIT(9) 716#define RCR_ACRC32 BIT(8) 717#define RCR_CBSSID_BCN BIT(7) 718#define RCR_CBSSID_DATA BIT(6) 719#define RCR_CBSSID RCR_CBSSID_DATA 720#define RCR_APWRMGT BIT(5) 721#define RCR_ADD3 BIT(4) 722#define RCR_AB BIT(3) 723#define RCR_AM BIT(2) 724#define RCR_APM BIT(1) 725#define RCR_AAP BIT(0) 726#define RCR_MXDMA_OFFSET 8 727#define RCR_FIFO_OFFSET 13 728 729#define RSV_CTRL 0x001C 730#define RD_CTRL 0x0524 731 732#define REG_USB_INFO 0xFE17 733#define REG_USB_SPECIAL_OPTION 0xFE55 734#define REG_USB_DMA_AGG_TO 0xFE5B 735#define REG_USB_AGG_TO 0xFE5C 736#define REG_USB_AGG_TH 0xFE5D 737 738#define REG_USB_VID 0xFE60 739#define REG_USB_PID 0xFE62 740#define REG_USB_OPTIONAL 0xFE64 741#define REG_USB_CHIRP_K 0xFE65 742#define REG_USB_PHY 0xFE66 743#define REG_USB_MAC_ADDR 0xFE70 744#define REG_USB_HRPWM 0xFE58 745#define REG_USB_HCPWM 0xFE57 746 747#define SW18_FPWM BIT(3) 748 749#define ISO_MD2PP BIT(0) 750#define ISO_UA2USB BIT(1) 751#define ISO_UD2CORE BIT(2) 752#define ISO_PA2PCIE BIT(3) 753#define ISO_PD2CORE BIT(4) 754#define ISO_IP2MAC BIT(5) 755#define ISO_DIOP BIT(6) 756#define ISO_DIOE BIT(7) 757#define ISO_EB2CORE BIT(8) 758#define ISO_DIOR BIT(9) 759 760#define PWC_EV25V BIT(14) 761#define PWC_EV12V BIT(15) 762 763#define FEN_BBRSTB BIT(0) 764#define FEN_BB_GLB_RSTN BIT(1) 765#define FEN_USBA BIT(2) 766#define FEN_UPLL BIT(3) 767#define FEN_USBD BIT(4) 768#define FEN_DIO_PCIE BIT(5) 769#define FEN_PCIEA BIT(6) 770#define FEN_PPLL BIT(7) 771#define FEN_PCIED BIT(8) 772#define FEN_DIOE BIT(9) 773#define FEN_CPUEN BIT(10) 774#define FEN_DCORE BIT(11) 775#define FEN_ELDR BIT(12) 776#define FEN_DIO_RF BIT(13) 777#define FEN_HWPDN BIT(14) 778#define FEN_MREGEN BIT(15) 779 780#define PFM_LDALL BIT(0) 781#define PFM_ALDN BIT(1) 782#define PFM_LDKP BIT(2) 783#define PFM_WOWL BIT(3) 784#define ENPDN BIT(4) 785#define PDN_PL BIT(5) 786#define APFM_ONMAC BIT(8) 787#define APFM_OFF BIT(9) 788#define APFM_RSM BIT(10) 789#define AFSM_HSUS BIT(11) 790#define AFSM_PCIE BIT(12) 791#define APDM_MAC BIT(13) 792#define APDM_HOST BIT(14) 793#define APDM_HPDN BIT(15) 794#define RDY_MACON BIT(16) 795#define SUS_HOST BIT(17) 796#define ROP_ALD BIT(20) 797#define ROP_PWR BIT(21) 798#define ROP_SPS BIT(22) 799#define SOP_MRST BIT(25) 800#define SOP_FUSE BIT(26) 801#define SOP_ABG BIT(27) 802#define SOP_AMB BIT(28) 803#define SOP_RCK BIT(29) 804#define SOP_A8M BIT(30) 805#define XOP_BTCK BIT(31) 806 807#define ANAD16V_EN BIT(0) 808#define ANA8M BIT(1) 809#define MACSLP BIT(4) 810#define LOADER_CLK_EN BIT(5) 811#define _80M_SSC_DIS BIT(7) 812#define _80M_SSC_EN_HO BIT(8) 813#define PHY_SSC_RSTB BIT(9) 814#define SEC_CLK_EN BIT(10) 815#define MAC_CLK_EN BIT(11) 816#define SYS_CLK_EN BIT(12) 817#define RING_CLK_EN BIT(13) 818 819#define BOOT_FROM_EEPROM BIT(4) 820#define EEPROM_EN BIT(5) 821 822#define AFE_BGEN BIT(0) 823#define AFE_MBEN BIT(1) 824#define MAC_ID_EN BIT(7) 825 826#define WLOCK_ALL BIT(0) 827#define WLOCK_00 BIT(1) 828#define WLOCK_04 BIT(2) 829#define WLOCK_08 BIT(3) 830#define WLOCK_40 BIT(4) 831#define R_DIS_PRST_0 BIT(5) 832#define R_DIS_PRST_1 BIT(6) 833#define LOCK_ALL_EN BIT(7) 834 835#define RF_EN BIT(0) 836#define RF_RSTB BIT(1) 837#define RF_SDMRSTB BIT(2) 838 839#define LDA15_EN BIT(0) 840#define LDA15_STBY BIT(1) 841#define LDA15_OBUF BIT(2) 842#define LDA15_REG_VOS BIT(3) 843#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 844 845#define LDV12_EN BIT(0) 846#define LDV12_SDBY BIT(1) 847#define LPLDO_HSM BIT(2) 848#define LPLDO_LSM_DIS BIT(3) 849#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 850 851#define XTAL_EN BIT(0) 852#define XTAL_BSEL BIT(1) 853#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 854#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 855#define XTAL_GATE_USB BIT(8) 856#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 857#define XTAL_GATE_AFE BIT(11) 858#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 859#define XTAL_RF_GATE BIT(14) 860#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 861#define XTAL_GATE_DIG BIT(17) 862#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 863#define XTAL_BT_GATE BIT(20) 864#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 865#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 866 867#define CKDLY_AFE BIT(26) 868#define CKDLY_USB BIT(27) 869#define CKDLY_DIG BIT(28) 870#define CKDLY_BT BIT(29) 871 872#define APLL_EN BIT(0) 873#define APLL_320_EN BIT(1) 874#define APLL_FREF_SEL BIT(2) 875#define APLL_EDGE_SEL BIT(3) 876#define APLL_WDOGB BIT(4) 877#define APLL_LPFEN BIT(5) 878 879#define APLL_REF_CLK_13MHZ 0x1 880#define APLL_REF_CLK_19_2MHZ 0x2 881#define APLL_REF_CLK_20MHZ 0x3 882#define APLL_REF_CLK_25MHZ 0x4 883#define APLL_REF_CLK_26MHZ 0x5 884#define APLL_REF_CLK_38_4MHZ 0x6 885#define APLL_REF_CLK_40MHZ 0x7 886 887#define APLL_320EN BIT(14) 888#define APLL_80EN BIT(15) 889#define APLL_1MEN BIT(24) 890 891#define ALD_EN BIT(18) 892#define EF_PD BIT(19) 893#define EF_FLAG BIT(31) 894 895#define EF_TRPT BIT(7) 896#define LDOE25_EN BIT(31) 897 898#define RSM_EN BIT(0) 899#define TIMER_EN BIT(4) 900 901#define TRSW0EN BIT(2) 902#define TRSW1EN BIT(3) 903#define EROM_EN BIT(4) 904#define ENBT BIT(5) 905#define ENUART BIT(8) 906#define UART_910 BIT(9) 907#define ENPMAC BIT(10) 908#define SIC_SWRST BIT(11) 909#define ENSIC BIT(12) 910#define SIC_23 BIT(13) 911#define ENHDP BIT(14) 912#define SIC_LBK BIT(15) 913 914#define LED0PL BIT(4) 915#define LED1PL BIT(12) 916#define LED0DIS BIT(7) 917 918#define MCUFWDL_EN BIT(0) 919#define MCUFWDL_RDY BIT(1) 920#define FWDL_CHKSUM_RPT BIT(2) 921#define MACINI_RDY BIT(3) 922#define BBINI_RDY BIT(4) 923#define RFINI_RDY BIT(5) 924#define WINTINI_RDY BIT(6) 925#define CPRST BIT(23) 926 927#define XCLK_VLD BIT(0) 928#define ACLK_VLD BIT(1) 929#define UCLK_VLD BIT(2) 930#define PCLK_VLD BIT(3) 931#define PCIRSTB BIT(4) 932#define V15_VLD BIT(5) 933#define TRP_B15V_EN BIT(7) 934#define SIC_IDLE BIT(8) 935#define BD_MAC2 BIT(9) 936#define BD_MAC1 BIT(10) 937#define IC_MACPHY_MODE BIT(11) 938#define VENDOR_ID BIT(19) 939#define PAD_HWPD_IDN BIT(22) 940#define TRP_VAUX_EN BIT(23) 941#define TRP_BT_EN BIT(24) 942#define BD_PKG_SEL BIT(25) 943#define BD_HCI_SEL BIT(26) 944#define TYPE_ID BIT(27) 945 946#define CHIP_VER_RTL_MASK 0xF000 947#define CHIP_VER_RTL_SHIFT 12 948 949#define REG_LBMODE (REG_CR + 3) 950 951#define HCI_TXDMA_EN BIT(0) 952#define HCI_RXDMA_EN BIT(1) 953#define TXDMA_EN BIT(2) 954#define RXDMA_EN BIT(3) 955#define PROTOCOL_EN BIT(4) 956#define SCHEDULE_EN BIT(5) 957#define MACTXEN BIT(6) 958#define MACRXEN BIT(7) 959#define ENSWBCN BIT(8) 960#define ENSEC BIT(9) 961 962#define _NETTYPE(x) (((x) & 0x3) << 16) 963#define MASK_NETTYPE 0x30000 964#define NT_NO_LINK 0x0 965#define NT_LINK_AD_HOC 0x1 966#define NT_LINK_AP 0x2 967#define NT_AS_AP 0x3 968 969#define _LBMODE(x) (((x) & 0xF) << 24) 970#define MASK_LBMODE 0xF000000 971#define LOOPBACK_NORMAL 0x0 972#define LOOPBACK_IMMEDIATELY 0xB 973#define LOOPBACK_MAC_DELAY 0x3 974#define LOOPBACK_PHY 0x1 975#define LOOPBACK_DMA 0x7 976 977#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 978#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 979#define _PSRX_MASK 0xF 980#define _PSTX_MASK 0xF0 981#define _PSRX(x) (x) 982#define _PSTX(x) ((x) << 4) 983 984#define PBP_64 0x0 985#define PBP_128 0x1 986#define PBP_256 0x2 987#define PBP_512 0x3 988#define PBP_1024 0x4 989 990#define RXDMA_ARBBW_EN BIT(0) 991#define RXSHFT_EN BIT(1) 992#define RXDMA_AGG_EN BIT(2) 993#define QS_VO_QUEUE BIT(8) 994#define QS_VI_QUEUE BIT(9) 995#define QS_BE_QUEUE BIT(10) 996#define QS_BK_QUEUE BIT(11) 997#define QS_MANAGER_QUEUE BIT(12) 998#define QS_HIGH_QUEUE BIT(13) 999 1000#define HQSEL_VOQ BIT(0) 1001#define HQSEL_VIQ BIT(1) 1002#define HQSEL_BEQ BIT(2) 1003#define HQSEL_BKQ BIT(3) 1004#define HQSEL_MGTQ BIT(4) 1005#define HQSEL_HIQ BIT(5) 1006 1007#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 1008#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 1009#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 1010#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 1011#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 1012#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 1013 1014#define QUEUE_LOW 1 1015#define QUEUE_NORMAL 2 1016#define QUEUE_HIGH 3 1017 1018#define _LLT_NO_ACTIVE 0x0 1019#define _LLT_WRITE_ACCESS 0x1 1020#define _LLT_READ_ACCESS 0x2 1021 1022#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1023#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1024#define _LLT_OP(x) (((x) & 0x3) << 30) 1025#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1026 1027#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1028#define BB_WRITE_EN BIT(30) 1029#define BB_READ_EN BIT(31) 1030 1031#define _HPQ(x) ((x) & 0xFF) 1032#define _LPQ(x) (((x) & 0xFF) << 8) 1033#define _PUBQ(x) (((x) & 0xFF) << 16) 1034#define _NPQ(x) ((x) & 0xFF) 1035 1036#define HPQ_PUBLIC_DIS BIT(24) 1037#define LPQ_PUBLIC_DIS BIT(25) 1038#define LD_RQPN BIT(31) 1039 1040#define BCN_VALID BIT(16) 1041#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1042#define BCN_HEAD_MASK 0xFF00 1043 1044#define BLK_DESC_NUM_SHIFT 4 1045#define BLK_DESC_NUM_MASK 0xF 1046 1047#define DROP_DATA_EN BIT(9) 1048 1049#define EN_AMPDU_RTY_NEW BIT(7) 1050 1051#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1052 1053#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1054#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1055 1056#define RATE_REG_BITMAP_ALL 0xFFFFF 1057 1058#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1059 1060#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1061#define RRSR_RSC_RESERVED 0x0 1062#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1063#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1064#define RRSR_RSC_DUPLICATE_MODE 0x3 1065 1066#define USE_SHORT_G1 BIT(20) 1067 1068#define _AGGLMT_MCS0(x) ((x) & 0xF) 1069#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1070#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1071#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1072#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1073#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1074#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1075#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1076 1077#define RETRY_LIMIT_SHORT_SHIFT 8 1078#define RETRY_LIMIT_LONG_SHIFT 0 1079 1080#define _DARF_RC1(x) ((x) & 0x1F) 1081#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1082#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1083#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1084#define _DARF_RC5(x) ((x) & 0x1F) 1085#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1086#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1087#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1088 1089#define _RARF_RC1(x) ((x) & 0x1F) 1090#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1091#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1092#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1093#define _RARF_RC5(x) ((x) & 0x1F) 1094#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1095#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1096#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1097 1098#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1099#define AC_PARAM_ECW_MAX_OFFSET 12 1100#define AC_PARAM_ECW_MIN_OFFSET 8 1101#define AC_PARAM_AIFS_OFFSET 0 1102 1103#define _AIFS(x) (x) 1104#define _ECW_MAX_MIN(x) ((x) << 8) 1105#define _TXOP_LIMIT(x) ((x) << 16) 1106 1107#define _BCNIFS(x) ((x) & 0xFF) 1108#define _BCNECW(x) ((((x) & 0xF)) << 8) 1109 1110#define _LRL(x) ((x) & 0x3F) 1111#define _SRL(x) (((x) & 0x3F) << 8) 1112 1113#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1114#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); 1115 1116#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1117#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); 1118 1119#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1120 1121#define DIS_EDCA_CNT_DWN BIT(11) 1122 1123#define EN_MBSSID BIT(1) 1124#define EN_TXBCN_RPT BIT(2) 1125#define EN_BCN_FUNCTION BIT(3) 1126 1127#define TSFTR_RST BIT(0) 1128#define TSFTR1_RST BIT(1) 1129 1130#define STOP_BCNQ BIT(6) 1131 1132#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1133#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1134 1135#define ACMHW_HWEN BIT(0) 1136#define ACMHW_BEQEN BIT(1) 1137#define ACMHW_VIQEN BIT(2) 1138#define ACMHW_VOQEN BIT(3) 1139#define ACMHW_BEQSTATUS BIT(4) 1140#define ACMHW_VIQSTATUS BIT(5) 1141#define ACMHW_VOQSTATUS BIT(6) 1142 1143#define APSDOFF BIT(6) 1144#define APSDOFF_STATUS BIT(7) 1145 1146#define BW_20MHZ BIT(2) 1147 1148#define RATE_BITMAP_ALL 0xFFFFF 1149 1150#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1151 1152#define TSFRST BIT(0) 1153#define DIS_GCLK BIT(1) 1154#define PAD_SEL BIT(2) 1155#define PWR_ST BIT(6) 1156#define PWRBIT_OW_EN BIT(7) 1157#define ACRC BIT(8) 1158#define CFENDFORM BIT(9) 1159#define ICV BIT(10) 1160 1161#define AAP BIT(0) 1162#define APM BIT(1) 1163#define AM BIT(2) 1164#define AB BIT(3) 1165#define ADD3 BIT(4) 1166#define APWRMGT BIT(5) 1167#define CBSSID BIT(6) 1168#define CBSSID_DATA BIT(6) 1169#define CBSSID_BCN BIT(7) 1170#define ACRC32 BIT(8) 1171#define AICV BIT(9) 1172#define ADF BIT(11) 1173#define ACF BIT(12) 1174#define AMF BIT(13) 1175#define HTC_LOC_CTRL BIT(14) 1176#define UC_DATA_EN BIT(16) 1177#define BM_DATA_EN BIT(17) 1178#define MFBEN BIT(22) 1179#define LSIGEN BIT(23) 1180#define ENMBID BIT(24) 1181#define APP_BASSN BIT(27) 1182#define APP_PHYSTS BIT(28) 1183#define APP_ICV BIT(29) 1184#define APP_MIC BIT(30) 1185#define APP_FCS BIT(31) 1186 1187#define _MIN_SPACE(x) ((x) & 0x7) 1188#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1189 1190#define RXERR_TYPE_OFDM_PPDU 0 1191#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1192#define RXERR_TYPE_OFDM_MPDU_OK 2 1193#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1194#define RXERR_TYPE_CCK_PPDU 4 1195#define RXERR_TYPE_CCK_FALSE_ALARM 5 1196#define RXERR_TYPE_CCK_MPDU_OK 6 1197#define RXERR_TYPE_CCK_MPDU_FAIL 7 1198#define RXERR_TYPE_HT_PPDU 8 1199#define RXERR_TYPE_HT_FALSE_ALARM 9 1200#define RXERR_TYPE_HT_MPDU_TOTAL 10 1201#define RXERR_TYPE_HT_MPDU_OK 11 1202#define RXERR_TYPE_HT_MPDU_FAIL 12 1203#define RXERR_TYPE_RX_FULL_DROP 15 1204 1205#define RXERR_COUNTER_MASK 0xFFFFF 1206#define RXERR_RPT_RST BIT(27) 1207#define _RXERR_RPT_SEL(type) ((type) << 28) 1208 1209#define SCR_TXUSEDK BIT(0) 1210#define SCR_RXUSEDK BIT(1) 1211#define SCR_TXENCENABLE BIT(2) 1212#define SCR_RXDECENABLE BIT(3) 1213#define SCR_SKBYA2 BIT(4) 1214#define SCR_NOSKMC BIT(5) 1215#define SCR_TXBCUSEDK BIT(6) 1216#define SCR_RXBCUSEDK BIT(7) 1217 1218#define USB_IS_HIGH_SPEED 0 1219#define USB_IS_FULL_SPEED 1 1220#define USB_SPEED_MASK BIT(5) 1221 1222#define USB_NORMAL_SIE_EP_MASK 0xF 1223#define USB_NORMAL_SIE_EP_SHIFT 4 1224 1225#define USB_TEST_EP_MASK 0x30 1226#define USB_TEST_EP_SHIFT 4 1227 1228#define USB_AGG_EN BIT(3) 1229 1230#define MAC_ADDR_LEN 6 1231#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/ 1232 1233#define POLLING_LLT_THRESHOLD 20 1234#define POLLING_READY_TIMEOUT_COUNT 3000 1235 1236#define MAX_MSS_DENSITY_2T 0x13 1237#define MAX_MSS_DENSITY_1T 0x0A 1238 1239#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1240#define EPROM_CMD_CONFIG 0x3 1241#define EPROM_CMD_LOAD 1 1242 1243#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1244 1245#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1246 1247#define RPMAC_RESET 0x100 1248#define RPMAC_TXSTART 0x104 1249#define RPMAC_TXLEGACYSIG 0x108 1250#define RPMAC_TXHTSIG1 0x10c 1251#define RPMAC_TXHTSIG2 0x110 1252#define RPMAC_PHYDEBUG 0x114 1253#define RPMAC_TXPACKETNUM 0x118 1254#define RPMAC_TXIDLE 0x11c 1255#define RPMAC_TXMACHEADER0 0x120 1256#define RPMAC_TXMACHEADER1 0x124 1257#define RPMAC_TXMACHEADER2 0x128 1258#define RPMAC_TXMACHEADER3 0x12c 1259#define RPMAC_TXMACHEADER4 0x130 1260#define RPMAC_TXMACHEADER5 0x134 1261#define RPMAC_TXDADATYPE 0x138 1262#define RPMAC_TXRANDOMSEED 0x13c 1263#define RPMAC_CCKPLCPPREAMBLE 0x140 1264#define RPMAC_CCKPLCPHEADER 0x144 1265#define RPMAC_CCKCRC16 0x148 1266#define RPMAC_OFDMRXCRC32OK 0x170 1267#define RPMAC_OFDMRXCRC32ER 0x174 1268#define RPMAC_OFDMRXPARITYER 0x178 1269#define RPMAC_OFDMRXCRC8ER 0x17c 1270#define RPMAC_CCKCRXRC16ER 0x180 1271#define RPMAC_CCKCRXRC32ER 0x184 1272#define RPMAC_CCKCRXRC32OK 0x188 1273#define RPMAC_TXSTATUS 0x18c 1274 1275#define RFPGA0_RFMOD 0x800 1276 1277#define RFPGA0_TXINFO 0x804 1278#define RFPGA0_PSDFUNCTION 0x808 1279 1280#define RFPGA0_TXGAINSTAGE 0x80c 1281 1282#define RFPGA0_RFTIMING1 0x810 1283#define RFPGA0_RFTIMING2 0x814 1284 1285#define RFPGA0_XA_HSSIPARAMETER1 0x820 1286#define RFPGA0_XA_HSSIPARAMETER2 0x824 1287#define RFPGA0_XB_HSSIPARAMETER1 0x828 1288#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1289 1290#define RFPGA0_XA_LSSIPARAMETER 0x840 1291#define RFPGA0_XB_LSSIPARAMETER 0x844 1292 1293#define RFPGA0_RFWAKEUPPARAMETER 0x850 1294#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1295 1296#define RFPGA0_XAB_SWITCHCONTROL 0x858 1297#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1298 1299#define RFPGA0_XA_RFINTERFACEOE 0x860 1300#define RFPGA0_XB_RFINTERFACEOE 0x864 1301 1302#define RFPGA0_XAB_RFINTERFACESW 0x870 1303#define RFPGA0_XCD_RFINTERFACESW 0x874 1304 1305#define RFPGA0_XAB_RFPARAMETER 0x878 1306#define RFPGA0_XCD_RFPARAMETER 0x87c 1307 1308#define RFPGA0_ANALOGPARAMETER1 0x880 1309#define RFPGA0_ANALOGPARAMETER2 0x884 1310#define RFPGA0_ANALOGPARAMETER3 0x888 1311#define RFPGA0_ANALOGPARAMETER4 0x88c 1312 1313#define RFPGA0_XA_LSSIREADBACK 0x8a0 1314#define RFPGA0_XB_LSSIREADBACK 0x8a4 1315#define RFPGA0_XC_LSSIREADBACK 0x8a8 1316#define RFPGA0_XD_LSSIREADBACK 0x8ac 1317 1318#define RFPGA0_PSDREPORT 0x8b4 1319#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1320#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1321#define REG_SC_CNT 0x8c4 1322#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1323#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1324 1325#define RFPGA1_RFMOD 0x900 1326 1327#define RFPGA1_TXBLOCK 0x904 1328#define RFPGA1_DEBUGSELECT 0x908 1329#define RFPGA1_TXINFO 0x90c 1330 1331#define RCCK0_SYSTEM 0xa00 1332 1333#define RCCK0_AFESETTING 0xa04 1334#define RCCK0_CCA 0xa08 1335 1336#define RCCK0_RXAGC1 0xa0c 1337#define RCCK0_RXAGC2 0xa10 1338 1339#define RCCK0_RXHP 0xa14 1340 1341#define RCCK0_DSPPARAMETER1 0xa18 1342#define RCCK0_DSPPARAMETER2 0xa1c 1343 1344#define RCCK0_TXFILTER1 0xa20 1345#define RCCK0_TXFILTER2 0xa24 1346#define RCCK0_DEBUGPORT 0xa28 1347#define RCCK0_FALSEALARMREPORT 0xa2c 1348#define RCCK0_TRSSIREPORT 0xa50 1349#define RCCK0_RXREPORT 0xa54 1350#define RCCK0_FACOUNTERLOWER 0xa5c 1351#define RCCK0_FACOUNTERUPPER 0xa58 1352#define RCCK0_CCA_CNT 0xa60 1353 1354/* PageB(0xB00) */ 1355#define RPDP_ANTA 0xb00 1356#define RPDP_ANTA_4 0xb04 1357#define RPDP_ANTA_8 0xb08 1358#define RPDP_ANTA_C 0xb0c 1359#define RPDP_ANTA_10 0xb10 1360#define RPDP_ANTA_14 0xb14 1361#define RPDP_ANTA_18 0xb18 1362#define RPDP_ANTA_1C 0xb1c 1363#define RPDP_ANTA_20 0xb20 1364#define RPDP_ANTA_24 0xb24 1365 1366#define RCONFIG_PMPD_ANTA 0xb28 1367#define RCONFIG_RAM64x16 0xb2c 1368 1369#define RBNDA 0xb30 1370#define RHSSIPAR 0xb34 1371 1372#define RCONFIG_ANTA 0xb68 1373#define RCONFIG_ANTB 0xb6c 1374 1375#define RPDP_ANTB 0xb70 1376#define RPDP_ANTB_4 0xb74 1377#define RPDP_ANTB_8 0xb78 1378#define RPDP_ANTB_C 0xb7c 1379#define RPDP_ANTB_10 0xb80 1380#define RPDP_ANTB_14 0xb84 1381#define RPDP_ANTB_18 0xb88 1382#define RPDP_ANTB_1C 0xb8c 1383#define RPDP_ANTB_20 0xb90 1384#define RPDP_ANTB_24 0xb94 1385 1386#define RCONFIG_PMPD_ANTB 0xb98 1387 1388#define RBNDB 0xba0 1389 1390#define RAPK 0xbd8 1391#define RPM_RX0_ANTA 0xbdc 1392#define RPM_RX1_ANTA 0xbe0 1393#define RPM_RX2_ANTA 0xbe4 1394#define RPM_RX3_ANTA 0xbe8 1395#define RPM_RX0_ANTB 0xbec 1396#define RPM_RX1_ANTB 0xbf0 1397#define RPM_RX2_ANTB 0xbf4 1398#define RPM_RX3_ANTB 0xbf8 1399 1400/*Page C*/ 1401#define ROFDM0_LSTF 0xc00 1402 1403#define ROFDM0_TRXPATHENABLE 0xc04 1404#define ROFDM0_TRMUXPAR 0xc08 1405#define ROFDM0_TRSWISOLATION 0xc0c 1406 1407#define ROFDM0_XARXAFE 0xc10 1408#define ROFDM0_XARXIQIMBALANCE 0xc14 1409#define ROFDM0_XBRXAFE 0xc18 1410#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1411#define ROFDM0_XCRXAFE 0xc20 1412#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1413#define ROFDM0_XDRXAFE 0xc28 1414#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1415 1416#define ROFDM0_RXDETECTOR1 0xc30 1417#define ROFDM0_RXDETECTOR2 0xc34 1418#define ROFDM0_RXDETECTOR3 0xc38 1419#define ROFDM0_RXDETECTOR4 0xc3c 1420 1421#define ROFDM0_RXDSP 0xc40 1422#define ROFDM0_CFOANDDAGC 0xc44 1423#define ROFDM0_CCADROPTHRESHOLD 0xc48 1424#define ROFDM0_ECCATHRESHOLD 0xc4c 1425 1426#define ROFDM0_XAAGCCORE1 0xc50 1427#define ROFDM0_XAAGCCORE2 0xc54 1428#define ROFDM0_XBAGCCORE1 0xc58 1429#define ROFDM0_XBAGCCORE2 0xc5c 1430#define ROFDM0_XCAGCCORE1 0xc60 1431#define ROFDM0_XCAGCCORE2 0xc64 1432#define ROFDM0_XDAGCCORE1 0xc68 1433#define ROFDM0_XDAGCCORE2 0xc6c 1434 1435#define ROFDM0_AGCPARAMETER1 0xc70 1436#define ROFDM0_AGCPARAMETER2 0xc74 1437#define ROFDM0_AGCRSSITABLE 0xc78 1438#define ROFDM0_HTSTFAGC 0xc7c 1439 1440#define ROFDM0_XATXIQIMBALANCE 0xc80 1441#define ROFDM0_XATXAFE 0xc84 1442#define ROFDM0_XBTXIQIMBALANCE 0xc88 1443#define ROFDM0_XBTXAFE 0xc8c 1444#define ROFDM0_XCTXIQIMBALANCE 0xc90 1445#define ROFDM0_XCTXAFE 0xc94 1446#define ROFDM0_XDTXIQIMBALANCE 0xc98 1447#define ROFDM0_XDTXAFE 0xc9c 1448 1449#define ROFDM0_RXIQEXTANTA 0xca0 1450#define ROFDM0_TXCOEFF1 0xca4 1451#define ROFDM0_TXCOEFF2 0xca8 1452#define ROFDM0_TXCOEFF3 0xcac 1453#define ROFDM0_TXCOEFF4 0xcb0 1454#define ROFDM0_TXCOEFF5 0xcb4 1455#define ROFDM0_TXCOEFF6 0xcb8 1456 1457#define ROFDM0_RXHPPARAMETER 0xce0 1458#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1459#define ROFDM0_FRAMESYNC 0xcf0 1460#define ROFDM0_DFSREPORT 0xcf4 1461 1462#define ROFDM1_LSTF 0xd00 1463#define ROFDM1_TRXPATHENABLE 0xd04 1464 1465#define ROFDM1_CF0 0xd08 1466#define ROFDM1_CSI1 0xd10 1467#define ROFDM1_SBD 0xd14 1468#define ROFDM1_CSI2 0xd18 1469#define ROFDM1_CFOTRACKING 0xd2c 1470#define ROFDM1_TRXMESAURE1 0xd34 1471#define ROFDM1_INTFDET 0xd3c 1472#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1473#define ROFDM1_PSEUDONOISESTATECD 0xd54 1474#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1475 1476#define ROFDM_PHYCOUNTER1 0xda0 1477#define ROFDM_PHYCOUNTER2 0xda4 1478#define ROFDM_PHYCOUNTER3 0xda8 1479 1480#define ROFDM_SHORTCFOAB 0xdac 1481#define ROFDM_SHORTCFOCD 0xdb0 1482#define ROFDM_LONGCFOAB 0xdb4 1483#define ROFDM_LONGCFOCD 0xdb8 1484#define ROFDM_TAILCF0AB 0xdbc 1485#define ROFDM_TAILCF0CD 0xdc0 1486#define ROFDM_PWMEASURE1 0xdc4 1487#define ROFDM_PWMEASURE2 0xdc8 1488#define ROFDM_BWREPORT 0xdcc 1489#define ROFDM_AGCREPORT 0xdd0 1490#define ROFDM_RXSNR 0xdd4 1491#define ROFDM_RXEVMCSI 0xdd8 1492#define ROFDM_SIGREPORT 0xddc 1493 1494#define RTXAGC_A_RATE18_06 0xe00 1495#define RTXAGC_A_RATE54_24 0xe04 1496#define RTXAGC_A_CCK1_MCS32 0xe08 1497#define RTXAGC_A_MCS03_MCS00 0xe10 1498#define RTXAGC_A_MCS07_MCS04 0xe14 1499#define RTXAGC_A_MCS11_MCS08 0xe18 1500#define RTXAGC_A_MCS15_MCS12 0xe1c 1501 1502#define RTXAGC_B_RATE18_06 0x830 1503#define RTXAGC_B_RATE54_24 0x834 1504#define RTXAGC_B_CCK1_55_MCS32 0x838 1505#define RTXAGC_B_MCS03_MCS00 0x83c 1506#define RTXAGC_B_MCS07_MCS04 0x848 1507#define RTXAGC_B_MCS11_MCS08 0x84c 1508#define RTXAGC_B_MCS15_MCS12 0x868 1509#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1510 1511#define RFPGA0_IQK 0xe28 1512#define RTX_IQK_TONE_A 0xe30 1513#define RRX_IQK_TONE_A 0xe34 1514#define RTX_IQK_PI_A 0xe38 1515#define RRX_IQK_PI_A 0xe3c 1516 1517#define RTX_IQK 0xe40 1518#define RRX_IQK 0xe44 1519#define RIQK_AGC_PTS 0xe48 1520#define RIQK_AGC_RSP 0xe4c 1521#define RTX_IQK_TONE_B 0xe50 1522#define RRX_IQK_TONE_B 0xe54 1523#define RTX_IQK_PI_B 0xe58 1524#define RRX_IQK_PI_B 0xe5c 1525#define RIQK_AGC_CONT 0xe60 1526 1527#define RBLUE_TOOTH 0xe6c 1528#define RRX_WAIT_CCA 0xe70 1529#define RTX_CCK_RFON 0xe74 1530#define RTX_CCK_BBON 0xe78 1531#define RTX_OFDM_RFON 0xe7c 1532#define RTX_OFDM_BBON 0xe80 1533#define RTX_TO_RX 0xe84 1534#define RTX_TO_TX 0xe88 1535#define RRX_CCK 0xe8c 1536 1537#define RTX_POWER_BEFORE_IQK_A 0xe94 1538#define RTX_POWER_AFTER_IQK_A 0xe9c 1539 1540#define RRX_POWER_BEFORE_IQK_A 0xea0 1541#define RRX_POWER_BEFORE_IQK_A_2 0xea4 1542#define RRX_POWER_AFTER_IQK_A 0xea8 1543#define RRX_POWER_AFTER_IQK_A_2 0xeac 1544 1545#define RTX_POWER_BEFORE_IQK_B 0xeb4 1546#define RTX_POWER_AFTER_IQK_B 0xebc 1547 1548#define RRX_POWER_BEFORE_IQK_B 0xec0 1549#define RRX_POWER_BEFORE_IQK_B_2 0xec4 1550#define RRX_POWER_AFTER_IQK_B 0xec8 1551#define RRX_POWER_AFTER_IQK_B_2 0xecc 1552 1553#define RRX_OFDM 0xed0 1554#define RRX_WAIT_RIFS 0xed4 1555#define RRX_TO_RX 0xed8 1556#define RSTANDBY 0xedc 1557#define RSLEEP 0xee0 1558#define RPMPD_ANAEN 0xeec 1559 1560#define RZEBRA1_HSSIENABLE 0x0 1561#define RZEBRA1_TRXENABLE1 0x1 1562#define RZEBRA1_TRXENABLE2 0x2 1563#define RZEBRA1_AGC 0x4 1564#define RZEBRA1_CHARGEPUMP 0x5 1565#define RZEBRA1_CHANNEL 0x7 1566 1567#define RZEBRA1_TXGAIN 0x8 1568#define RZEBRA1_TXLPF 0x9 1569#define RZEBRA1_RXLPF 0xb 1570#define RZEBRA1_RXHPFCORNER 0xc 1571 1572#define RGLOBALCTRL 0 1573#define RRTL8256_TXLPF 19 1574#define RRTL8256_RXLPF 11 1575#define RRTL8258_TXLPF 0x11 1576#define RRTL8258_RXLPF 0x13 1577#define RRTL8258_RSSILPF 0xa 1578 1579#define RF_AC 0x00 1580 1581#define RF_IQADJ_G1 0x01 1582#define RF_IQADJ_G2 0x02 1583#define RF_POW_TRSW 0x05 1584 1585#define RF_GAIN_RX 0x06 1586#define RF_GAIN_TX 0x07 1587 1588#define RF_TXM_IDAC 0x08 1589#define RF_BS_IQGEN 0x0F 1590 1591#define RF_MODE1 0x10 1592#define RF_MODE2 0x11 1593 1594#define RF_RX_AGC_HP 0x12 1595#define RF_TX_AGC 0x13 1596#define RF_BIAS 0x14 1597#define RF_IPA 0x15 1598#define RF_POW_ABILITY 0x17 1599#define RF_MODE_AG 0x18 1600#define RRFCHANNEL 0x18 1601#define RF_CHNLBW 0x18 1602#define RF_TOP 0x19 1603 1604#define RF_RX_G1 0x1A 1605#define RF_RX_G2 0x1B 1606 1607#define RF_RX_BB2 0x1C 1608#define RF_RX_BB1 0x1D 1609 1610#define RF_RCK1 0x1E 1611#define RF_RCK2 0x1F 1612 1613#define RF_TX_G1 0x20 1614#define RF_TX_G2 0x21 1615#define RF_TX_G3 0x22 1616 1617#define RF_TX_BB1 0x23 1618#define RF_T_METER 0x42 1619 1620#define RF_SYN_G1 0x25 1621#define RF_SYN_G2 0x26 1622#define RF_SYN_G3 0x27 1623#define RF_SYN_G4 0x28 1624#define RF_SYN_G5 0x29 1625#define RF_SYN_G6 0x2A 1626#define RF_SYN_G7 0x2B 1627#define RF_SYN_G8 0x2C 1628 1629#define RF_RCK_OS 0x30 1630#define RF_TXPA_G1 0x31 1631#define RF_TXPA_G2 0x32 1632#define RF_TXPA_G3 0x33 1633 1634#define RF_TX_BIAS_A 0x35 1635#define RF_TX_BIAS_D 0x36 1636#define RF_LOBF_9 0x38 1637#define RF_RXRF_A3 0x3C 1638#define RF_TRSW 0x3F 1639 1640#define RF_TXRF_A2 0x41 1641#define RF_TXPA_G4 0x46 1642#define RF_TXPA_A4 0x4B 1643 1644#define RF_WE_LUT 0xEF 1645 1646#define BBBRESETB 0x100 1647#define BGLOBALRESETB 0x200 1648#define BOFDMTXSTART 0x4 1649#define BCCKTXSTART 0x8 1650#define BCRC32DEBUG 0x100 1651#define BPMACLOOPBACK 0x10 1652#define BTXLSIG 0xffffff 1653#define BOFDMTXRATE 0xf 1654#define BOFDMTXRESERVED 0x10 1655#define BOFDMTXLENGTH 0x1ffe0 1656#define BOFDMTXPARITY 0x20000 1657#define BTXHTSIG1 0xffffff 1658#define BTXHTMCSRATE 0x7f 1659#define BTXHTBW 0x80 1660#define BTXHTLENGTH 0xffff00 1661#define BTXHTSIG2 0xffffff 1662#define BTXHTSMOOTHING 0x1 1663#define BTXHTSOUNDING 0x2 1664#define BTXHTRESERVED 0x4 1665#define BTXHTAGGREATION 0x8 1666#define BTXHTSTBC 0x30 1667#define BTXHTADVANCECODING 0x40 1668#define BTXHTSHORTGI 0x80 1669#define BTXHTNUMBERHT_LTF 0x300 1670#define BTXHTCRC8 0x3fc00 1671#define BCOUNTERRESET 0x10000 1672#define BNUMOFOFDMTX 0xffff 1673#define BNUMOFCCKTX 0xffff0000 1674#define BTXIDLEINTERVAL 0xffff 1675#define BOFDMSERVICE 0xffff0000 1676#define BTXMACHEADER 0xffffffff 1677#define BTXDATAINIT 0xff 1678#define BTXHTMODE 0x100 1679#define BTXDATATYPE 0x30000 1680#define BTXRANDOMSEED 0xffffffff 1681#define BCCKTXPREAMBLE 0x1 1682#define BCCKTXSFD 0xffff0000 1683#define BCCKTXSIG 0xff 1684#define BCCKTXSERVICE 0xff00 1685#define BCCKLENGTHEXT 0x8000 1686#define BCCKTXLENGHT 0xffff0000 1687#define BCCKTXCRC16 0xffff 1688#define BCCKTXSTATUS 0x1 1689#define BOFDMTXSTATUS 0x2 1690#define IS_BB_REG_OFFSET_92S(_offset) \ 1691 ((_offset >= 0x800) && (_offset <= 0xfff)) 1692 1693#define BRFMOD 0x1 1694#define BJAPANMODE 0x2 1695#define BCCKTXSC 0x30 1696#define BCCKEN 0x1000000 1697#define BOFDMEN 0x2000000 1698 1699#define BOFDMRXADCPHASE 0x10000 1700#define BOFDMTXDACPHASE 0x40000 1701#define BXATXAGC 0x3f 1702 1703#define BXBTXAGC 0xf00 1704#define BXCTXAGC 0xf000 1705#define BXDTXAGC 0xf0000 1706 1707#define BPASTART 0xf0000000 1708#define BTRSTART 0x00f00000 1709#define BRFSTART 0x0000f000 1710#define BBBSTART 0x000000f0 1711#define BBBCCKSTART 0x0000000f 1712#define BPAEND 0xf 1713#define BTREND 0x0f000000 1714#define BRFEND 0x000f0000 1715#define BCCAMASK 0x000000f0 1716#define BR2RCCAMASK 0x00000f00 1717#define BHSSI_R2TDELAY 0xf8000000 1718#define BHSSI_T2RDELAY 0xf80000 1719#define BCONTXHSSI 0x400 1720#define BIGFROMCCK 0x200 1721#define BAGCADDRESS 0x3f 1722#define BRXHPTX 0x7000 1723#define BRXHP2RX 0x38000 1724#define BRXHPCCKINI 0xc0000 1725#define BAGCTXCODE 0xc00000 1726#define BAGCRXCODE 0x300000 1727 1728#define B3WIREDATALENGTH 0x800 1729#define B3WIREADDREAALENGTH 0x400 1730 1731#define B3WIRERFPOWERDOWN 0x1 1732#define B5GPAPEPOLARITY 0x40000000 1733#define B2GPAPEPOLARITY 0x80000000 1734#define BRFSW_TXDEFAULTANT 0x3 1735#define BRFSW_TXOPTIONANT 0x30 1736#define BRFSW_RXDEFAULTANT 0x300 1737#define BRFSW_RXOPTIONANT 0x3000 1738#define BRFSI_3WIREDATA 0x1 1739#define BRFSI_3WIRECLOCK 0x2 1740#define BRFSI_3WIRELOAD 0x4 1741#define BRFSI_3WIRERW 0x8 1742#define BRFSI_3WIRE 0xf 1743 1744#define BRFSI_RFENV 0x10 1745 1746#define BRFSI_TRSW 0x20 1747#define BRFSI_TRSWB 0x40 1748#define BRFSI_ANTSW 0x100 1749#define BRFSI_ANTSWB 0x200 1750#define BRFSI_PAPE 0x400 1751#define BRFSI_PAPE5G 0x800 1752#define BBANDSELECT 0x1 1753#define BHTSIG2_GI 0x80 1754#define BHTSIG2_SMOOTHING 0x01 1755#define BHTSIG2_SOUNDING 0x02 1756#define BHTSIG2_AGGREATON 0x08 1757#define BHTSIG2_STBC 0x30 1758#define BHTSIG2_ADVCODING 0x40 1759#define BHTSIG2_NUMOFHTLTF 0x300 1760#define BHTSIG2_CRC8 0x3fc 1761#define BHTSIG1_MCS 0x7f 1762#define BHTSIG1_BANDWIDTH 0x80 1763#define BHTSIG1_HTLENGTH 0xffff 1764#define BLSIG_RATE 0xf 1765#define BLSIG_RESERVED 0x10 1766#define BLSIG_LENGTH 0x1fffe 1767#define BLSIG_PARITY 0x20 1768#define BCCKRXPHASE 0x4 1769 1770#define BLSSIREADADDRESS 0x7f800000 1771#define BLSSIREADEDGE 0x80000000 1772 1773#define BLSSIREADBACKDATA 0xfffff 1774 1775#define BLSSIREADOKFLAG 0x1000 1776#define BCCKSAMPLERATE 0x8 1777#define BREGULATOR0STANDBY 0x1 1778#define BREGULATORPLLSTANDBY 0x2 1779#define BREGULATOR1STANDBY 0x4 1780#define BPLLPOWERUP 0x8 1781#define BDPLLPOWERUP 0x10 1782#define BDA10POWERUP 0x20 1783#define BAD7POWERUP 0x200 1784#define BDA6POWERUP 0x2000 1785#define BXTALPOWERUP 0x4000 1786#define B40MDCLKPOWERUP 0x8000 1787#define BDA6DEBUGMODE 0x20000 1788#define BDA6SWING 0x380000 1789 1790#define BADCLKPHASE 0x4000000 1791#define B80MCLKDELAY 0x18000000 1792#define BAFEWATCHDOGENABLE 0x20000000 1793 1794#define BXTALCAP01 0xc0000000 1795#define BXTALCAP23 0x3 1796#define BXTALCAP92X 0x0f000000 1797#define BXTALCAP 0x0f000000 1798 1799#define BINTDIFCLKENABLE 0x400 1800#define BEXTSIGCLKENABLE 0x800 1801#define BBANDGAP_MBIAS_POWERUP 0x10000 1802#define BAD11SH_GAIN 0xc0000 1803#define BAD11NPUT_RANGE 0x700000 1804#define BAD110P_CURRENT 0x3800000 1805#define BLPATH_LOOPBACK 0x4000000 1806#define BQPATH_LOOPBACK 0x8000000 1807#define BAFE_LOOPBACK 0x10000000 1808#define BDA10_SWING 0x7e0 1809#define BDA10_REVERSE 0x800 1810#define BDA_CLK_SOURCE 0x1000 1811#define BDA7INPUT_RANGE 0x6000 1812#define BDA7_GAIN 0x38000 1813#define BDA7OUTPUT_CM_MODE 0x40000 1814#define BDA7INPUT_CM_MODE 0x380000 1815#define BDA7CURRENT 0xc00000 1816#define BREGULATOR_ADJUST 0x7000000 1817#define BAD11POWERUP_ATTX 0x1 1818#define BDA10PS_ATTX 0x10 1819#define BAD11POWERUP_ATRX 0x100 1820#define BDA10PS_ATRX 0x1000 1821#define BCCKRX_AGC_FORMAT 0x200 1822#define BPSDFFT_SAMPLE_POINT 0xc000 1823#define BPSD_AVERAGE_NUM 0x3000 1824#define BIQPATH_CONTROL 0xc00 1825#define BPSD_FREQ 0x3ff 1826#define BPSD_ANTENNA_PATH 0x30 1827#define BPSD_IQ_SWITCH 0x40 1828#define BPSD_RX_TRIGGER 0x400000 1829#define BPSD_TX_TRIGGER 0x80000000 1830#define BPSD_SINE_TONE_SCALE 0x7f000000 1831#define BPSD_REPORT 0xffff 1832 1833#define BOFDM_TXSC 0x30000000 1834#define BCCK_TXON 0x1 1835#define BOFDM_TXON 0x2 1836#define BDEBUG_PAGE 0xfff 1837#define BDEBUG_ITEM 0xff 1838#define BANTL 0x10 1839#define BANT_NONHT 0x100 1840#define BANT_HT1 0x1000 1841#define BANT_HT2 0x10000 1842#define BANT_HT1S1 0x100000 1843#define BANT_NONHTS1 0x1000000 1844 1845#define BCCK_BBMODE 0x3 1846#define BCCK_TXPOWERSAVING 0x80 1847#define BCCK_RXPOWERSAVING 0x40 1848 1849#define BCCK_SIDEBAND 0x10 1850 1851#define BCCK_SCRAMBLE 0x8 1852#define BCCK_ANTDIVERSITY 0x8000 1853#define BCCK_CARRIER_RECOVERY 0x4000 1854#define BCCK_TXRATE 0x3000 1855#define BCCK_DCCANCEL 0x0800 1856#define BCCK_ISICANCEL 0x0400 1857#define BCCK_MATCH_FILTER 0x0200 1858#define BCCK_EQUALIZER 0x0100 1859#define BCCK_PREAMBLE_DETECT 0x800000 1860#define BCCK_FAST_FALSECCA 0x400000 1861#define BCCK_CH_ESTSTART 0x300000 1862#define BCCK_CCA_COUNT 0x080000 1863#define BCCK_CS_LIM 0x070000 1864#define BCCK_BIST_MODE 0x80000000 1865#define BCCK_CCAMASK 0x40000000 1866#define BCCK_TX_DAC_PHASE 0x4 1867#define BCCK_RX_ADC_PHASE 0x20000000 1868#define BCCKR_CP_MODE 0x0100 1869#define BCCK_TXDC_OFFSET 0xf0 1870#define BCCK_RXDC_OFFSET 0xf 1871#define BCCK_CCA_MODE 0xc000 1872#define BCCK_FALSECS_LIM 0x3f00 1873#define BCCK_CS_RATIO 0xc00000 1874#define BCCK_CORGBIT_SEL 0x300000 1875#define BCCK_PD_LIM 0x0f0000 1876#define BCCK_NEWCCA 0x80000000 1877#define BCCK_RXHP_OF_IG 0x8000 1878#define BCCK_RXIG 0x7f00 1879#define BCCK_LNA_POLARITY 0x800000 1880#define BCCK_RX1ST_BAIN 0x7f0000 1881#define BCCK_RF_EXTEND 0x20000000 1882#define BCCK_RXAGC_SATLEVEL 0x1f000000 1883#define BCCK_RXAGC_SATCOUNT 0xe0 1884#define BCCKRXRFSETTLE 0x1f 1885#define BCCK_FIXED_RXAGC 0x8000 1886#define BCCK_ANTENNA_POLARITY 0x2000 1887#define BCCK_TXFILTER_TYPE 0x0c00 1888#define BCCK_RXAGC_REPORTTYPE 0x0300 1889#define BCCK_RXDAGC_EN 0x80000000 1890#define BCCK_RXDAGC_PERIOD 0x20000000 1891#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1892#define BCCK_TIMING_RECOVERY 0x800000 1893#define BCCK_TXC0 0x3f0000 1894#define BCCK_TXC1 0x3f000000 1895#define BCCK_TXC2 0x3f 1896#define BCCK_TXC3 0x3f00 1897#define BCCK_TXC4 0x3f0000 1898#define BCCK_TXC5 0x3f000000 1899#define BCCK_TXC6 0x3f 1900#define BCCK_TXC7 0x3f00 1901#define BCCK_DEBUGPORT 0xff0000 1902#define BCCK_DAC_DEBUG 0x0f000000 1903#define BCCK_FALSEALARM_ENABLE 0x8000 1904#define BCCK_FALSEALARM_READ 0x4000 1905#define BCCK_TRSSI 0x7f 1906#define BCCK_RXAGC_REPORT 0xfe 1907#define BCCK_RXREPORT_ANTSEL 0x80000000 1908#define BCCK_RXREPORT_MFOFF 0x40000000 1909#define BCCK_RXREPORT_SQLOSS 0x20000000 1910#define BCCK_RXREPORT_PKTLOSS 0x10000000 1911#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1912#define BCCK_RXREPORT_RATEERROR 0x04000000 1913#define BCCK_RXREPORT_RXRATE 0x03000000 1914#define BCCK_RXFA_COUNTER_LOWER 0xff 1915#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1916#define BCCK_RXHPAGC_START 0xe000 1917#define BCCK_RXHPAGC_FINAL 0x1c00 1918#define BCCK_RXFALSEALARM_ENABLE 0x8000 1919#define BCCK_FACOUNTER_FREEZE 0x4000 1920#define BCCK_TXPATH_SEL 0x10000000 1921#define BCCK_DEFAULT_RXPATH 0xc000000 1922#define BCCK_OPTION_RXPATH 0x3000000 1923 1924#define BNUM_OFSTF 0x3 1925#define BSHIFT_L 0xc0 1926#define BGI_TH 0xc 1927#define BRXPATH_A 0x1 1928#define BRXPATH_B 0x2 1929#define BRXPATH_C 0x4 1930#define BRXPATH_D 0x8 1931#define BTXPATH_A 0x1 1932#define BTXPATH_B 0x2 1933#define BTXPATH_C 0x4 1934#define BTXPATH_D 0x8 1935#define BTRSSI_FREQ 0x200 1936#define BADC_BACKOFF 0x3000 1937#define BDFIR_BACKOFF 0xc000 1938#define BTRSSI_LATCH_PHASE 0x10000 1939#define BRX_LDC_OFFSET 0xff 1940#define BRX_QDC_OFFSET 0xff00 1941#define BRX_DFIR_MODE 0x1800000 1942#define BRX_DCNF_TYPE 0xe000000 1943#define BRXIQIMB_A 0x3ff 1944#define BRXIQIMB_B 0xfc00 1945#define BRXIQIMB_C 0x3f0000 1946#define BRXIQIMB_D 0xffc00000 1947#define BDC_DC_NOTCH 0x60000 1948#define BRXNB_NOTCH 0x1f000000 1949#define BPD_TH 0xf 1950#define BPD_TH_OPT2 0xc000 1951#define BPWED_TH 0x700 1952#define BIFMF_WIN_L 0x800 1953#define BPD_OPTION 0x1000 1954#define BMF_WIN_L 0xe000 1955#define BBW_SEARCH_L 0x30000 1956#define BWIN_ENH_L 0xc0000 1957#define BBW_TH 0x700000 1958#define BED_TH2 0x3800000 1959#define BBW_OPTION 0x4000000 1960#define BRADIO_TH 0x18000000 1961#define BWINDOW_L 0xe0000000 1962#define BSBD_OPTION 0x1 1963#define BFRAME_TH 0x1c 1964#define BFS_OPTION 0x60 1965#define BDC_SLOPE_CHECK 0x80 1966#define BFGUARD_COUNTER_DC_L 0xe00 1967#define BFRAME_WEIGHT_SHORT 0x7000 1968#define BSUB_TUNE 0xe00000 1969#define BFRAME_DC_LENGTH 0xe000000 1970#define BSBD_START_OFFSET 0x30000000 1971#define BFRAME_TH_2 0x7 1972#define BFRAME_GI2_TH 0x38 1973#define BGI2_SYNC_EN 0x40 1974#define BSARCH_SHORT_EARLY 0x300 1975#define BSARCH_SHORT_LATE 0xc00 1976#define BSARCH_GI2_LATE 0x70000 1977#define BCFOANTSUM 0x1 1978#define BCFOACC 0x2 1979#define BCFOSTARTOFFSET 0xc 1980#define BCFOLOOPBACK 0x70 1981#define BCFOSUMWEIGHT 0x80 1982#define BDAGCENABLE 0x10000 1983#define BTXIQIMB_A 0x3ff 1984#define BTXIQIMB_b 0xfc00 1985#define BTXIQIMB_C 0x3f0000 1986#define BTXIQIMB_D 0xffc00000 1987#define BTXIDCOFFSET 0xff 1988#define BTXIQDCOFFSET 0xff00 1989#define BTXDFIRMODE 0x10000 1990#define BTXPESUDO_NOISEON 0x4000000 1991#define BTXPESUDO_NOISE_A 0xff 1992#define BTXPESUDO_NOISE_B 0xff00 1993#define BTXPESUDO_NOISE_C 0xff0000 1994#define BTXPESUDO_NOISE_D 0xff000000 1995#define BCCA_DROPOPTION 0x20000 1996#define BCCA_DROPTHRES 0xfff00000 1997#define BEDCCA_H 0xf 1998#define BEDCCA_L 0xf0 1999#define BLAMBDA_ED 0x300 2000#define BRX_INITIALGAIN 0x7f 2001#define BRX_ANTDIV_EN 0x80 2002#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 2003#define BRX_HIGHPOWER_FLOW 0x8000 2004#define BRX_AGC_FREEZE_THRES 0xc0000 2005#define BRX_FREEZESTEP_AGC1 0x300000 2006#define BRX_FREEZESTEP_AGC2 0xc00000 2007#define BRX_FREEZESTEP_AGC3 0x3000000 2008#define BRX_FREEZESTEP_AGC0 0xc000000 2009#define BRXRSSI_CMP_EN 0x10000000 2010#define BRXQUICK_AGCEN 0x20000000 2011#define BRXAGC_FREEZE_THRES_MODE 0x40000000 2012#define BRX_OVERFLOW_CHECKTYPE 0x80000000 2013#define BRX_AGCSHIFT 0x7f 2014#define BTRSW_TRI_ONLY 0x80 2015#define BPOWER_THRES 0x300 2016#define BRXAGC_EN 0x1 2017#define BRXAGC_TOGETHER_EN 0x2 2018#define BRXAGC_MIN 0x4 2019#define BRXHP_INI 0x7 2020#define BRXHP_TRLNA 0x70 2021#define BRXHP_RSSI 0x700 2022#define BRXHP_BBP1 0x7000 2023#define BRXHP_BBP2 0x70000 2024#define BRXHP_BBP3 0x700000 2025#define BRSSI_H 0x7f0000 2026#define BRSSI_GEN 0x7f000000 2027#define BRXSETTLE_TRSW 0x7 2028#define BRXSETTLE_LNA 0x38 2029#define BRXSETTLE_RSSI 0x1c0 2030#define BRXSETTLE_BBP 0xe00 2031#define BRXSETTLE_RXHP 0x7000 2032#define BRXSETTLE_ANTSW_RSSI 0x38000 2033#define BRXSETTLE_ANTSW 0xc0000 2034#define BRXPROCESS_TIME_DAGC 0x300000 2035#define BRXSETTLE_HSSI 0x400000 2036#define BRXPROCESS_TIME_BBPPW 0x800000 2037#define BRXANTENNA_POWER_SHIFT 0x3000000 2038#define BRSSI_TABLE_SELECT 0xc000000 2039#define BRXHP_FINAL 0x7000000 2040#define BRXHPSETTLE_BBP 0x7 2041#define BRXHTSETTLE_HSSI 0x8 2042#define BRXHTSETTLE_RXHP 0x70 2043#define BRXHTSETTLE_BBPPW 0x80 2044#define BRXHTSETTLE_IDLE 0x300 2045#define BRXHTSETTLE_RESERVED 0x1c00 2046#define BRXHT_RXHP_EN 0x8000 2047#define BRXAGC_FREEZE_THRES 0x30000 2048#define BRXAGC_TOGETHEREN 0x40000 2049#define BRXHTAGC_MIN 0x80000 2050#define BRXHTAGC_EN 0x100000 2051#define BRXHTDAGC_EN 0x200000 2052#define BRXHT_RXHP_BBP 0x1c00000 2053#define BRXHT_RXHP_FINAL 0xe0000000 2054#define BRXPW_RADIO_TH 0x3 2055#define BRXPW_RADIO_EN 0x4 2056#define BRXMF_HOLD 0x3800 2057#define BRXPD_DELAY_TH1 0x38 2058#define BRXPD_DELAY_TH2 0x1c0 2059#define BRXPD_DC_COUNT_MAX 0x600 2060#define BRXPD_DELAY_TH 0x8000 2061#define BRXPROCESS_DELAY 0xf0000 2062#define BRXSEARCHRANGE_GI2_EARLY 0x700000 2063#define BRXFRAME_FUARD_COUNTER_L 0x3800000 2064#define BRXSGI_GUARD_L 0xc000000 2065#define BRXSGI_SEARCH_L 0x30000000 2066#define BRXSGI_TH 0xc0000000 2067#define BDFSCNT0 0xff 2068#define BDFSCNT1 0xff00 2069#define BDFSFLAG 0xf0000 2070#define BMF_WEIGHT_SUM 0x300000 2071#define BMINIDX_TH 0x7f000000 2072#define BDAFORMAT 0x40000 2073#define BTXCH_EMU_ENABLE 0x01000000 2074#define BTRSW_ISOLATION_A 0x7f 2075#define BTRSW_ISOLATION_B 0x7f00 2076#define BTRSW_ISOLATION_C 0x7f0000 2077#define BTRSW_ISOLATION_D 0x7f000000 2078#define BEXT_LNA_GAIN 0x7c00 2079 2080#define BSTBC_EN 0x4 2081#define BANTENNA_MAPPING 0x10 2082#define BNSS 0x20 2083#define BCFO_ANTSUM_ID 0x200 2084#define BPHY_COUNTER_RESET 0x8000000 2085#define BCFO_REPORT_GET 0x4000000 2086#define BOFDM_CONTINUE_TX 0x10000000 2087#define BOFDM_SINGLE_CARRIER 0x20000000 2088#define BOFDM_SINGLE_TONE 0x40000000 2089#define BHT_DETECT 0x100 2090#define BCFOEN 0x10000 2091#define BCFOVALUE 0xfff00000 2092#define BSIGTONE_RE 0x3f 2093#define BSIGTONE_IM 0x7f00 2094#define BCOUNTER_CCA 0xffff 2095#define BCOUNTER_PARITYFAIL 0xffff0000 2096#define BCOUNTER_RATEILLEGAL 0xffff 2097#define BCOUNTER_CRC8FAIL 0xffff0000 2098#define BCOUNTER_MCSNOSUPPORT 0xffff 2099#define BCOUNTER_FASTSYNC 0xffff 2100#define BSHORTCFO 0xfff 2101#define BSHORTCFOT_LENGTH 12 2102#define BSHORTCFOF_LENGTH 11 2103#define BLONGCFO 0x7ff 2104#define BLONGCFOT_LENGTH 11 2105#define BLONGCFOF_LENGTH 11 2106#define BTAILCFO 0x1fff 2107#define BTAILCFOT_LENGTH 13 2108#define BTAILCFOF_LENGTH 12 2109#define BNOISE_EN_PWDB 0xffff 2110#define BCC_POWER_DB 0xffff0000 2111#define BMOISE_PWDB 0xffff 2112#define BPOWERMEAST_LENGTH 10 2113#define BPOWERMEASF_LENGTH 3 2114#define BRX_HT_BW 0x1 2115#define BRXSC 0x6 2116#define BRX_HT 0x8 2117#define BNB_INTF_DET_ON 0x1 2118#define BINTF_WIN_LEN_CFG 0x30 2119#define BNB_INTF_TH_CFG 0x1c0 2120#define BRFGAIN 0x3f 2121#define BTABLESEL 0x40 2122#define BTRSW 0x80 2123#define BRXSNR_A 0xff 2124#define BRXSNR_B 0xff00 2125#define BRXSNR_C 0xff0000 2126#define BRXSNR_D 0xff000000 2127#define BSNR_EVMT_LENGTH 8 2128#define BSNR_EVMF_LENGTH 1 2129#define BCSI1ST 0xff 2130#define BCSI2ND 0xff00 2131#define BRXEVM1ST 0xff0000 2132#define BRXEVM2ND 0xff000000 2133#define BSIGEVM 0xff 2134#define BPWDB 0xff00 2135#define BSGIEN 0x10000 2136 2137#define BSFACTOR_QMA1 0xf 2138#define BSFACTOR_QMA2 0xf0 2139#define BSFACTOR_QMA3 0xf00 2140#define BSFACTOR_QMA4 0xf000 2141#define BSFACTOR_QMA5 0xf0000 2142#define BSFACTOR_QMA6 0xf0000 2143#define BSFACTOR_QMA7 0xf00000 2144#define BSFACTOR_QMA8 0xf000000 2145#define BSFACTOR_QMA9 0xf0000000 2146#define BCSI_SCHEME 0x100000 2147 2148#define BNOISE_LVL_TOP_SET 0x3 2149#define BCHSMOOTH 0x4 2150#define BCHSMOOTH_CFG1 0x38 2151#define BCHSMOOTH_CFG2 0x1c0 2152#define BCHSMOOTH_CFG3 0xe00 2153#define BCHSMOOTH_CFG4 0x7000 2154#define BMRCMODE 0x800000 2155#define BTHEVMCFG 0x7000000 2156 2157#define BLOOP_FIT_TYPE 0x1 2158#define BUPD_CFO 0x40 2159#define BUPD_CFO_OFFDATA 0x80 2160#define BADV_UPD_CFO 0x100 2161#define BADV_TIME_CTRL 0x800 2162#define BUPD_CLKO 0x1000 2163#define BFC 0x6000 2164#define BTRACKING_MODE 0x8000 2165#define BPHCMP_ENABLE 0x10000 2166#define BUPD_CLKO_LTF 0x20000 2167#define BCOM_CH_CFO 0x40000 2168#define BCSI_ESTI_MODE 0x80000 2169#define BADV_UPD_EQZ 0x100000 2170#define BUCHCFG 0x7000000 2171#define BUPDEQZ 0x8000000 2172 2173#define BRX_PESUDO_NOISE_ON 0x20000000 2174#define BRX_PESUDO_NOISE_A 0xff 2175#define BRX_PESUDO_NOISE_B 0xff00 2176#define BRX_PESUDO_NOISE_C 0xff0000 2177#define BRX_PESUDO_NOISE_D 0xff000000 2178#define BRX_PESUDO_NOISESTATE_A 0xffff 2179#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2180#define BRX_PESUDO_NOISESTATE_C 0xffff 2181#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2182 2183#define BZEBRA1_HSSIENABLE 0x8 2184#define BZEBRA1_TRXCONTROL 0xc00 2185#define BZEBRA1_TRXGAINSETTING 0x07f 2186#define BZEBRA1_RXCOUNTER 0xc00 2187#define BZEBRA1_TXCHANGEPUMP 0x38 2188#define BZEBRA1_RXCHANGEPUMP 0x7 2189#define BZEBRA1_CHANNEL_NUM 0xf80 2190#define BZEBRA1_TXLPFBW 0x400 2191#define BZEBRA1_RXLPFBW 0x600 2192 2193#define BRTL8256REG_MODE_CTRL1 0x100 2194#define BRTL8256REG_MODE_CTRL0 0x40 2195#define BRTL8256REG_TXLPFBW 0x18 2196#define BRTL8256REG_RXLPFBW 0x600 2197 2198#define BRTL8258_TXLPFBW 0xc 2199#define BRTL8258_RXLPFBW 0xc00 2200#define BRTL8258_RSSILPFBW 0xc0 2201 2202#define BBYTE0 0x1 2203#define BBYTE1 0x2 2204#define BBYTE2 0x4 2205#define BBYTE3 0x8 2206#define BWORD0 0x3 2207#define BWORD1 0xc 2208#define BWORD 0xf 2209 2210#define MASKBYTE0 0xff 2211#define MASKBYTE1 0xff00 2212#define MASKBYTE2 0xff0000 2213#define MASKBYTE3 0xff000000 2214#define MASKHWORD 0xffff0000 2215#define MASKLWORD 0x0000ffff 2216#define MASKDWORD 0xffffffff 2217#define MASK12BITS 0xfff 2218#define MASKH4BITS 0xf0000000 2219#define MASKOFDM_D 0xffc00000 2220#define MASKCCK 0x3f3f3f3f 2221 2222#define MASK4BITS 0x0f 2223#define MASK20BITS 0xfffff 2224#define RFREG_OFFSET_MASK 0xfffff 2225 2226#define BENABLE 0x1 2227#define BDISABLE 0x0 2228 2229#define LEFT_ANTENNA 0x0 2230#define RIGHT_ANTENNA 0x1 2231 2232#define TCHECK_TXSTATUS 500 2233#define TUPDATE_RXCOUNTER 100 2234 2235#define REG_UN_used_register 0x01bf 2236 2237/* WOL bit information */ 2238#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) 2239#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) 2240#define HAL92C_WOL_DISASSOC_EVENT BIT(2) 2241#define HAL92C_WOL_DEAUTH_EVENT BIT(3) 2242#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) 2243 2244#define WOL_REASON_PTK_UPDATE BIT(0) 2245#define WOL_REASON_GTK_UPDATE BIT(1) 2246#define WOL_REASON_DISASSOC BIT(2) 2247#define WOL_REASON_DEAUTH BIT(3) 2248#define WOL_REASON_FW_DISCONNECT BIT(4) 2249#endif 2250