1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5 */
6
7#ifndef __MT7601U_EEPROM_H
8#define __MT7601U_EEPROM_H
9
10struct mt7601u_dev;
11
12#define MT7601U_EE_MAX_VER			0x0d
13#define MT7601U_EEPROM_SIZE			256
14
15#define MT7601U_DEFAULT_TX_POWER		6
16
17enum mt76_eeprom_field {
18	MT_EE_CHIP_ID =				0x00,
19	MT_EE_VERSION_FAE =			0x02,
20	MT_EE_VERSION_EE =			0x03,
21	MT_EE_MAC_ADDR =			0x04,
22	MT_EE_NIC_CONF_0 =			0x34,
23	MT_EE_NIC_CONF_1 =			0x36,
24	MT_EE_COUNTRY_REGION =			0x39,
25	MT_EE_FREQ_OFFSET =			0x3a,
26	MT_EE_NIC_CONF_2 =			0x42,
27
28	MT_EE_LNA_GAIN =			0x44,
29	MT_EE_RSSI_OFFSET =			0x46,
30
31	MT_EE_TX_POWER_DELTA_BW40 =		0x50,
32	MT_EE_TX_POWER_OFFSET =			0x52,
33
34	MT_EE_TX_TSSI_SLOPE =			0x6e,
35	MT_EE_TX_TSSI_OFFSET_GROUP =		0x6f,
36	MT_EE_TX_TSSI_OFFSET =			0x76,
37
38	MT_EE_TX_TSSI_TARGET_POWER =		0xd0,
39	MT_EE_REF_TEMP =			0xd1,
40	MT_EE_FREQ_OFFSET_COMPENSATION =	0xdb,
41	MT_EE_TX_POWER_BYRATE_BASE =		0xde,
42
43	MT_EE_USAGE_MAP_START =			0x1e0,
44	MT_EE_USAGE_MAP_END =			0x1fc,
45};
46
47#define MT_EE_NIC_CONF_0_RX_PATH		GENMASK(3, 0)
48#define MT_EE_NIC_CONF_0_TX_PATH		GENMASK(7, 4)
49#define MT_EE_NIC_CONF_0_BOARD_TYPE		GENMASK(13, 12)
50
51#define MT_EE_NIC_CONF_1_HW_RF_CTRL		BIT(0)
52#define MT_EE_NIC_CONF_1_TEMP_TX_ALC		BIT(1)
53#define MT_EE_NIC_CONF_1_LNA_EXT_2G		BIT(2)
54#define MT_EE_NIC_CONF_1_LNA_EXT_5G		BIT(3)
55#define MT_EE_NIC_CONF_1_TX_ALC_EN		BIT(13)
56
57#define MT_EE_NIC_CONF_2_RX_STREAM		GENMASK(3, 0)
58#define MT_EE_NIC_CONF_2_TX_STREAM		GENMASK(7, 4)
59#define MT_EE_NIC_CONF_2_HW_ANTDIV		BIT(8)
60#define MT_EE_NIC_CONF_2_XTAL_OPTION		GENMASK(10, 9)
61#define MT_EE_NIC_CONF_2_TEMP_DISABLE		BIT(11)
62#define MT_EE_NIC_CONF_2_COEX_METHOD		GENMASK(15, 13)
63
64#define MT_EE_TX_POWER_BYRATE(i)		(MT_EE_TX_POWER_BYRATE_BASE + \
65						 (i) * 4)
66
67#define MT_EFUSE_USAGE_MAP_SIZE			(MT_EE_USAGE_MAP_END -	\
68						 MT_EE_USAGE_MAP_START + 1)
69
70enum mt7601u_eeprom_access_modes {
71	MT_EE_READ = 0,
72	MT_EE_PHYSICAL_READ = 1,
73};
74
75struct power_per_rate  {
76	u8 raw;  /* validated s6 value */
77	s8 bw20; /* sign-extended int */
78	s8 bw40; /* sign-extended int */
79};
80
81/* Power per rate - one value per two rates */
82struct mt7601u_rate_power {
83	struct power_per_rate cck[2];
84	struct power_per_rate ofdm[4];
85	struct power_per_rate ht[4];
86};
87
88struct reg_channel_bounds {
89	u8 start;
90	u8 num;
91};
92
93struct mt7601u_eeprom_params {
94	bool tssi_enabled;
95	u8 rf_freq_off;
96	s8 rssi_offset[2];
97	s8 ref_temp;
98	s8 lna_gain;
99
100	u8 chan_pwr[14];
101	struct mt7601u_rate_power power_rate_table;
102	s8 real_cck_bw20[2];
103
104	/* TSSI stuff - only with internal TX ALC */
105	struct tssi_data {
106		int tx0_delta_offset;
107		u8 slope;
108		u8 offset[3];
109	} tssi_data;
110
111	struct reg_channel_bounds reg;
112};
113
114int mt7601u_eeprom_init(struct mt7601u_dev *dev);
115
116static inline u32 s6_validate(u32 reg)
117{
118	WARN_ON(reg & ~GENMASK(5, 0));
119	return reg & GENMASK(5, 0);
120}
121
122static inline int s6_to_int(u32 reg)
123{
124	int s6;
125
126	s6 = s6_validate(reg);
127	if (s6 & BIT(5))
128		s6 -= BIT(6);
129
130	return s6;
131}
132
133static inline u32 int_to_s6(int val)
134{
135	if (val < -0x20)
136		return 0x20;
137	if (val > 0x1f)
138		return 0x1f;
139
140	return val & 0x3f;
141}
142
143#endif
144