1// SPDX-License-Identifier: ISC 2/* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6#include <linux/kernel.h> 7#include <linux/module.h> 8#include <linux/pci.h> 9#include <linux/of.h> 10 11#include "mt7921.h" 12#include "../mt76_connac2_mac.h" 13#include "../dma.h" 14#include "mcu.h" 15 16static const struct pci_device_id mt7921_pci_device_table[] = { 17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961), 18 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922), 20 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 21 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922), 22 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608), 24 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616), 26 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 27 { }, 28}; 29 30static bool mt7921_disable_aspm; 31module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 32MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 33 34static int mt7921e_init_reset(struct mt792x_dev *dev) 35{ 36 return mt792x_wpdma_reset(dev, true); 37} 38 39static void mt7921e_unregister_device(struct mt792x_dev *dev) 40{ 41 int i; 42 struct mt76_connac_pm *pm = &dev->pm; 43 44 cancel_work_sync(&dev->init_work); 45 mt76_unregister_device(&dev->mt76); 46 mt76_for_each_q_rx(&dev->mt76, i) 47 napi_disable(&dev->mt76.napi[i]); 48 cancel_delayed_work_sync(&pm->ps_work); 49 cancel_work_sync(&pm->wake_work); 50 cancel_work_sync(&dev->reset_work); 51 52 mt76_connac2_tx_token_put(&dev->mt76); 53 __mt792x_mcu_drv_pmctrl(dev); 54 mt792x_dma_cleanup(dev); 55 mt792x_wfsys_reset(dev); 56 skb_queue_purge(&dev->mt76.mcu.res_q); 57 58 tasklet_disable(&dev->mt76.irq_tasklet); 59} 60 61static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr) 62{ 63 static const struct mt76_connac_reg_map fixed_map[] = { 64 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 65 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 66 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 67 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 68 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 69 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 70 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 71 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 72 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 73 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 74 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 75 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 76 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 77 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 78 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 79 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 80 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 81 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 82 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 83 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 84 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 85 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 86 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */ 87 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */ 88 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */ 89 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 90 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 91 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 92 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 93 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 94 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 95 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 96 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 97 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 98 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 99 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 100 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 101 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 102 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 103 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 104 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 105 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 106 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 107 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 108 }; 109 int i; 110 111 if (addr < 0x100000) 112 return addr; 113 114 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 115 u32 ofs; 116 117 if (addr < fixed_map[i].phys) 118 continue; 119 120 ofs = addr - fixed_map[i].phys; 121 if (ofs > fixed_map[i].size) 122 continue; 123 124 return fixed_map[i].maps + ofs; 125 } 126 127 if ((addr >= 0x18000000 && addr < 0x18c00000) || 128 (addr >= 0x70000000 && addr < 0x78000000) || 129 (addr >= 0x7c000000 && addr < 0x7c400000)) 130 return mt7921_reg_map_l1(dev, addr); 131 132 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 133 addr); 134 135 return 0; 136} 137 138static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 139{ 140 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 141 u32 addr = __mt7921_reg_addr(dev, offset); 142 143 return dev->bus_ops->rr(mdev, addr); 144} 145 146static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 147{ 148 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 149 u32 addr = __mt7921_reg_addr(dev, offset); 150 151 dev->bus_ops->wr(mdev, addr, val); 152} 153 154static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 155{ 156 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 157 u32 addr = __mt7921_reg_addr(dev, offset); 158 159 return dev->bus_ops->rmw(mdev, addr, mask, val); 160} 161 162static int mt7921_dma_init(struct mt792x_dev *dev) 163{ 164 int ret; 165 166 mt76_dma_attach(&dev->mt76); 167 168 ret = mt792x_dma_disable(dev, true); 169 if (ret) 170 return ret; 171 172 /* init tx queue */ 173 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0, 174 MT7921_TX_RING_SIZE, 175 MT_TX_RING_BASE, NULL, 0); 176 if (ret) 177 return ret; 178 179 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4); 180 181 /* command to WM */ 182 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM, 183 MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 184 if (ret) 185 return ret; 186 187 /* firmware download */ 188 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL, 189 MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 190 if (ret) 191 return ret; 192 193 /* event from WM before firmware download */ 194 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 195 MT7921_RXQ_MCU_WM, 196 MT7921_RX_MCU_RING_SIZE, 197 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE); 198 if (ret) 199 return ret; 200 201 /* Change mcu queue after firmware download */ 202 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 203 MT7921_RXQ_MCU_WM, 204 MT7921_RX_MCU_WA_RING_SIZE, 205 MT_RX_BUF_SIZE, MT_WFDMA0(0x540)); 206 if (ret) 207 return ret; 208 209 /* rx data */ 210 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 211 MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE, 212 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE); 213 if (ret) 214 return ret; 215 216 ret = mt76_init_queues(dev, mt792x_poll_rx); 217 if (ret < 0) 218 return ret; 219 220 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 221 mt792x_poll_tx); 222 napi_enable(&dev->mt76.tx_napi); 223 224 return mt792x_dma_enable(dev); 225} 226 227static int mt7921_pci_probe(struct pci_dev *pdev, 228 const struct pci_device_id *id) 229{ 230 static const struct mt76_driver_ops drv_ops = { 231 /* txwi_size = txd size + txp size */ 232 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp), 233 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 234 MT_DRV_AMSDU_OFFLOAD, 235 .survey_flags = SURVEY_INFO_TIME_TX | 236 SURVEY_INFO_TIME_RX | 237 SURVEY_INFO_TIME_BSS_RX, 238 .token_size = MT7921_TOKEN_SIZE, 239 .tx_prepare_skb = mt7921e_tx_prepare_skb, 240 .tx_complete_skb = mt76_connac_tx_complete_skb, 241 .rx_check = mt7921_rx_check, 242 .rx_skb = mt7921_queue_rx_skb, 243 .rx_poll_complete = mt792x_rx_poll_complete, 244 .sta_add = mt7921_mac_sta_add, 245 .sta_assoc = mt7921_mac_sta_assoc, 246 .sta_remove = mt7921_mac_sta_remove, 247 .update_survey = mt792x_update_channel, 248 }; 249 static const struct mt792x_hif_ops mt7921_pcie_ops = { 250 .init_reset = mt7921e_init_reset, 251 .reset = mt7921e_mac_reset, 252 .mcu_init = mt7921e_mcu_init, 253 .drv_own = mt792xe_mcu_drv_pmctrl, 254 .fw_own = mt792xe_mcu_fw_pmctrl, 255 }; 256 static const struct mt792x_irq_map irq_map = { 257 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA, 258 .tx = { 259 .all_complete_mask = MT_INT_TX_DONE_ALL, 260 .mcu_complete_mask = MT_INT_TX_DONE_MCU, 261 }, 262 .rx = { 263 .data_complete_mask = MT_INT_RX_DONE_DATA, 264 .wm_complete_mask = MT_INT_RX_DONE_WM, 265 .wm2_complete_mask = MT_INT_RX_DONE_WM2, 266 }, 267 }; 268 struct ieee80211_ops *ops; 269 struct mt76_bus_ops *bus_ops; 270 struct mt792x_dev *dev; 271 struct mt76_dev *mdev; 272 u8 features; 273 int ret; 274 u16 cmd; 275 276 ret = pcim_enable_device(pdev); 277 if (ret) 278 return ret; 279 280 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 281 if (ret) 282 return ret; 283 284 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 285 if (!(cmd & PCI_COMMAND_MEMORY)) { 286 cmd |= PCI_COMMAND_MEMORY; 287 pci_write_config_word(pdev, PCI_COMMAND, cmd); 288 } 289 pci_set_master(pdev); 290 291 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 292 if (ret < 0) 293 return ret; 294 295 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 296 if (ret) 297 goto err_free_pci_vec; 298 299 if (mt7921_disable_aspm) 300 mt76_pci_disable_aspm(pdev); 301 302 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops, 303 (void *)id->driver_data, &features); 304 if (!ops) { 305 ret = -ENOMEM; 306 goto err_free_pci_vec; 307 } 308 309 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops); 310 if (!mdev) { 311 ret = -ENOMEM; 312 goto err_free_pci_vec; 313 } 314 315 pci_set_drvdata(pdev, mdev); 316 317 dev = container_of(mdev, struct mt792x_dev, mt76); 318 dev->fw_features = features; 319 dev->hif_ops = &mt7921_pcie_ops; 320 dev->irq_map = &irq_map; 321 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 322 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev); 323 324 dev->phy.dev = dev; 325 dev->phy.mt76 = &dev->mt76.phy; 326 dev->mt76.phy.priv = &dev->phy; 327 dev->bus_ops = dev->mt76.bus; 328 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 329 GFP_KERNEL); 330 if (!bus_ops) { 331 ret = -ENOMEM; 332 goto err_free_dev; 333 } 334 335 bus_ops->rr = mt7921_rr; 336 bus_ops->wr = mt7921_wr; 337 bus_ops->rmw = mt7921_rmw; 338 dev->mt76.bus = bus_ops; 339 340 ret = mt792xe_mcu_fw_pmctrl(dev); 341 if (ret) 342 goto err_free_dev; 343 344 ret = __mt792xe_mcu_drv_pmctrl(dev); 345 if (ret) 346 goto err_free_dev; 347 348 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) | 349 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 350 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 351 352 ret = mt792x_wfsys_reset(dev); 353 if (ret) 354 goto err_free_dev; 355 356 mt76_wr(dev, irq_map.host_irq_enable, 0); 357 358 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 359 360 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler, 361 IRQF_SHARED, KBUILD_MODNAME, dev); 362 if (ret) 363 goto err_free_dev; 364 365 ret = mt7921_dma_init(dev); 366 if (ret) 367 goto err_free_irq; 368 369 ret = mt7921_register_device(dev); 370 if (ret) 371 goto err_free_irq; 372 373 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source")) 374 device_init_wakeup(dev->mt76.dev, true); 375 376 return 0; 377 378err_free_irq: 379 devm_free_irq(&pdev->dev, pdev->irq, dev); 380err_free_dev: 381 mt76_free_device(&dev->mt76); 382err_free_pci_vec: 383 pci_free_irq_vectors(pdev); 384 385 return ret; 386} 387 388static void mt7921_pci_remove(struct pci_dev *pdev) 389{ 390 struct mt76_dev *mdev = pci_get_drvdata(pdev); 391 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 392 393 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source")) 394 device_init_wakeup(dev->mt76.dev, false); 395 396 mt7921e_unregister_device(dev); 397 set_bit(MT76_REMOVED, &mdev->phy.state); 398 devm_free_irq(&pdev->dev, pdev->irq, dev); 399 mt76_free_device(&dev->mt76); 400 pci_free_irq_vectors(pdev); 401} 402 403static int mt7921_pci_suspend(struct device *device) 404{ 405 struct pci_dev *pdev = to_pci_dev(device); 406 struct mt76_dev *mdev = pci_get_drvdata(pdev); 407 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 408 struct mt76_connac_pm *pm = &dev->pm; 409 int i, err; 410 411 pm->suspended = true; 412 flush_work(&dev->reset_work); 413 cancel_delayed_work_sync(&pm->ps_work); 414 cancel_work_sync(&pm->wake_work); 415 416 mt7921_roc_abort_sync(dev); 417 418 err = mt792x_mcu_drv_pmctrl(dev); 419 if (err < 0) 420 goto restore_suspend; 421 422 wait_event_timeout(dev->wait, 423 !dev->regd_in_progress, 5 * HZ); 424 425 err = mt76_connac_mcu_set_hif_suspend(mdev, true); 426 if (err) 427 goto restore_suspend; 428 429 /* always enable deep sleep during suspend to reduce 430 * power consumption 431 */ 432 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 433 434 napi_disable(&mdev->tx_napi); 435 mt76_worker_disable(&mdev->tx_worker); 436 437 mt76_for_each_q_rx(mdev, i) { 438 napi_disable(&mdev->napi[i]); 439 } 440 441 /* wait until dma is idle */ 442 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 443 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 444 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 445 446 /* put dma disabled */ 447 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 448 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 449 450 /* disable interrupt */ 451 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); 452 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 453 synchronize_irq(pdev->irq); 454 tasklet_kill(&mdev->irq_tasklet); 455 456 err = mt792x_mcu_fw_pmctrl(dev); 457 if (err) 458 goto restore_napi; 459 460 return 0; 461 462restore_napi: 463 mt76_for_each_q_rx(mdev, i) { 464 napi_enable(&mdev->napi[i]); 465 } 466 napi_enable(&mdev->tx_napi); 467 468 if (!pm->ds_enable) 469 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 470 471 mt76_connac_mcu_set_hif_suspend(mdev, false); 472 473restore_suspend: 474 pm->suspended = false; 475 476 if (err < 0) 477 mt792x_reset(&dev->mt76); 478 479 return err; 480} 481 482static int mt7921_pci_resume(struct device *device) 483{ 484 struct pci_dev *pdev = to_pci_dev(device); 485 struct mt76_dev *mdev = pci_get_drvdata(pdev); 486 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 487 struct mt76_connac_pm *pm = &dev->pm; 488 int i, err; 489 490 err = mt792x_mcu_drv_pmctrl(dev); 491 if (err < 0) 492 goto failed; 493 494 mt792x_wpdma_reinit_cond(dev); 495 496 /* enable interrupt */ 497 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 498 mt76_connac_irq_enable(&dev->mt76, 499 dev->irq_map->tx.all_complete_mask | 500 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD); 501 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 502 503 /* put dma enabled */ 504 mt76_set(dev, MT_WFDMA0_GLO_CFG, 505 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 506 507 mt76_worker_enable(&mdev->tx_worker); 508 509 local_bh_disable(); 510 mt76_for_each_q_rx(mdev, i) { 511 napi_enable(&mdev->napi[i]); 512 napi_schedule(&mdev->napi[i]); 513 } 514 napi_enable(&mdev->tx_napi); 515 napi_schedule(&mdev->tx_napi); 516 local_bh_enable(); 517 518 /* restore previous ds setting */ 519 if (!pm->ds_enable) 520 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 521 522 err = mt76_connac_mcu_set_hif_suspend(mdev, false); 523 524 mt7921_regd_update(dev); 525 526failed: 527 pm->suspended = false; 528 529 if (err < 0) 530 mt792x_reset(&dev->mt76); 531 532 return err; 533} 534 535static void mt7921_pci_shutdown(struct pci_dev *pdev) 536{ 537 mt7921_pci_remove(pdev); 538} 539 540static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume); 541 542static struct pci_driver mt7921_pci_driver = { 543 .name = KBUILD_MODNAME, 544 .id_table = mt7921_pci_device_table, 545 .probe = mt7921_pci_probe, 546 .remove = mt7921_pci_remove, 547 .shutdown = mt7921_pci_shutdown, 548 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops), 549}; 550 551module_pci_driver(mt7921_pci_driver); 552 553MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 554MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 555MODULE_FIRMWARE(MT7921_ROM_PATCH); 556MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 557MODULE_FIRMWARE(MT7922_ROM_PATCH); 558MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 559MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 560MODULE_DESCRIPTION("MediaTek MT7921E (PCIe) wireless driver"); 561MODULE_LICENSE("Dual BSD/GPL"); 562