1// SPDX-License-Identifier: ISC 2/* 3 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 4 */ 5 6#include "mt76x2u.h" 7#include "eeprom.h" 8 9static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev) 10{ 11 s8 offset = 0; 12 u16 eep_val; 13 14 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); 15 16 offset = eep_val & 0x7f; 17 if ((eep_val & 0xff) == 0xff) 18 offset = 0; 19 else if (eep_val & 0x80) 20 offset = 0 - offset; 21 22 eep_val >>= 8; 23 if (eep_val == 0x00 || eep_val == 0xff) { 24 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); 25 eep_val &= 0xff; 26 27 if (eep_val == 0x00 || eep_val == 0xff) 28 eep_val = 0x14; 29 } 30 31 eep_val &= 0x7f; 32 mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5), 33 MT_XO_CTRL5_C2_VAL, eep_val + offset); 34 mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL); 35 36 mt76_wr(dev, 0x504, 0x06000000); 37 mt76_wr(dev, 0x50c, 0x08800000); 38 mdelay(5); 39 mt76_wr(dev, 0x504, 0x0); 40 41 /* decrease SIFS from 16us to 13us */ 42 mt76_rmw_field(dev, MT_XIFS_TIME_CFG, 43 MT_XIFS_TIME_CFG_OFDM_SIFS, 0xd); 44 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, MT_BKOFF_SLOT_CFG_CC_DELAY, 1); 45 46 /* init fce */ 47 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 48 49 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); 50 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 51 case 0: 52 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 53 break; 54 case 1: 55 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); 56 break; 57 default: 58 break; 59 } 60} 61 62int mt76x2u_mac_reset(struct mt76x02_dev *dev) 63{ 64 mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5)); 65 66 /* init pbf regs */ 67 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); 68 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); 69 70 mt76_write_mac_initvals(dev); 71 72 mt76_wr(dev, MT_TX_LINK_CFG, 0x1020); 73 mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13); 74 mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00); 75 76 mt76_wr(dev, MT_WMM_AIFSN, 0x2273); 77 mt76_wr(dev, MT_WMM_CWMIN, 0x2344); 78 mt76_wr(dev, MT_WMM_CWMAX, 0x34aa); 79 80 mt76_clear(dev, MT_MAC_SYS_CTRL, 81 MT_MAC_SYS_CTRL_RESET_CSR | 82 MT_MAC_SYS_CTRL_RESET_BBP); 83 84 if (is_mt7612(dev)) 85 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); 86 87 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); 88 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); 89 90 mt76x2u_mac_fixup_xtal(dev); 91 92 return 0; 93} 94 95int mt76x2u_mac_stop(struct mt76x02_dev *dev) 96{ 97 int i, count = 0, val; 98 bool stopped = false; 99 u32 rts_cfg; 100 101 if (test_bit(MT76_REMOVED, &dev->mphy.state)) 102 return -EIO; 103 104 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG); 105 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT); 106 107 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 108 mt76_clear(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); 109 110 /* wait tx dma to stop */ 111 for (i = 0; i < 2000; i++) { 112 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); 113 if (!(val & MT_USB_DMA_CFG_TX_BUSY) && i > 10) 114 break; 115 usleep_range(50, 100); 116 } 117 118 /* page count on TxQ */ 119 for (i = 0; i < 200; i++) { 120 if (!(mt76_rr(dev, 0x0438) & 0xffffffff) && 121 !(mt76_rr(dev, 0x0a30) & 0x000000ff) && 122 !(mt76_rr(dev, 0x0a34) & 0xff00ff00)) 123 break; 124 usleep_range(10, 20); 125 } 126 127 /* disable tx-rx */ 128 mt76_clear(dev, MT_MAC_SYS_CTRL, 129 MT_MAC_SYS_CTRL_ENABLE_RX | 130 MT_MAC_SYS_CTRL_ENABLE_TX); 131 132 /* Wait for MAC to become idle */ 133 for (i = 0; i < 1000; i++) { 134 if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) && 135 !mt76_rr(dev, MT_BBP(IBI, 12))) { 136 stopped = true; 137 break; 138 } 139 usleep_range(10, 20); 140 } 141 142 if (!stopped) { 143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); 144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); 145 146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); 147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); 148 } 149 150 /* page count on RxQ */ 151 for (i = 0; i < 200; i++) { 152 if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) && 153 !(mt76_rr(dev, 0x0a30) & 0xffffffff) && 154 !(mt76_rr(dev, 0x0a34) & 0xffffffff) && 155 ++count > 10) 156 break; 157 msleep(50); 158 } 159 160 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 2000)) 161 dev_warn(dev->mt76.dev, "MAC RX failed to stop\n"); 162 163 /* wait rx dma to stop */ 164 for (i = 0; i < 2000; i++) { 165 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); 166 if (!(val & MT_USB_DMA_CFG_RX_BUSY) && i > 10) 167 break; 168 usleep_range(50, 100); 169 } 170 171 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg); 172 173 return 0; 174} 175