1// SPDX-License-Identifier: ISC 2 3#include <linux/etherdevice.h> 4#include "mt7603.h" 5#include "mac.h" 6#include "eeprom.h" 7 8const struct mt76_driver_ops mt7603_drv_ops = { 9 .txwi_size = MT_TXD_SIZE, 10 .drv_flags = MT_DRV_SW_RX_AIRTIME, 11 .survey_flags = SURVEY_INFO_TIME_TX, 12 .tx_prepare_skb = mt7603_tx_prepare_skb, 13 .tx_complete_skb = mt7603_tx_complete_skb, 14 .rx_skb = mt7603_queue_rx_skb, 15 .rx_poll_complete = mt7603_rx_poll_complete, 16 .sta_ps = mt7603_sta_ps, 17 .sta_add = mt7603_sta_add, 18 .sta_assoc = mt7603_sta_assoc, 19 .sta_remove = mt7603_sta_remove, 20 .update_survey = mt7603_update_channel, 21}; 22 23static void 24mt7603_set_tmac_template(struct mt7603_dev *dev) 25{ 26 u32 desc[5] = { 27 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), 28 [3] = MT_TXD5_SW_POWER_MGMT 29 }; 30 u32 addr; 31 int i; 32 33 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR); 34 addr += MT_CLIENT_TMAC_INFO_TEMPLATE; 35 for (i = 0; i < ARRAY_SIZE(desc); i++) 36 mt76_wr(dev, addr + 4 * i, desc[i]); 37} 38 39static void 40mt7603_dma_sched_init(struct mt7603_dev *dev) 41{ 42 int page_size = 128; 43 int page_count; 44 int max_len = 1792; 45 int max_amsdu_pages = 4096 / page_size; 46 int max_mcu_len = 4096; 47 int max_beacon_len = 512 * 4 + max_len; 48 int max_mcast_pages = 4 * max_len / page_size; 49 int reserved_count = 0; 50 int beacon_pages; 51 int mcu_pages; 52 int i; 53 54 page_count = mt76_get_field(dev, MT_PSE_FC_P0, 55 MT_PSE_FC_P0_MAX_QUOTA); 56 beacon_pages = 4 * (max_beacon_len / page_size); 57 mcu_pages = max_mcu_len / page_size; 58 59 mt76_wr(dev, MT_PSE_FRP, 60 FIELD_PREP(MT_PSE_FRP_P0, 7) | 61 FIELD_PREP(MT_PSE_FRP_P1, 6) | 62 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); 63 64 mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553); 65 mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555); 66 67 mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e); 68 mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c); 69 70 mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff); 71 72 mt76_wr(dev, MT_SCH_1, page_count | (2 << 28)); 73 mt76_wr(dev, MT_SCH_2, max_amsdu_pages); 74 75 for (i = 0; i <= 4; i++) 76 mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages); 77 reserved_count += 5 * max_amsdu_pages; 78 79 mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages); 80 reserved_count += mcu_pages; 81 82 mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages); 83 reserved_count += beacon_pages; 84 85 mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages); 86 reserved_count += max_mcast_pages; 87 88 if (is_mt7603(dev)) 89 reserved_count = 0; 90 91 mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count); 92 93 if (is_mt7603(dev) && mt76xx_rev(dev) >= MT7603_REV_E2) { 94 mt76_wr(dev, MT_GROUP_THRESH(0), 95 page_count - beacon_pages - mcu_pages); 96 mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages); 97 mt76_wr(dev, MT_BMAP_0, 0x0080ff5f); 98 mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages); 99 mt76_wr(dev, MT_BMAP_1, 0x00000020); 100 } else { 101 mt76_wr(dev, MT_GROUP_THRESH(0), page_count); 102 mt76_wr(dev, MT_BMAP_0, 0xffff); 103 } 104 105 mt76_wr(dev, MT_SCH_4, 0); 106 107 for (i = 0; i <= 15; i++) 108 mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff); 109 110 mt76_set(dev, MT_SCH_4, BIT(6)); 111} 112 113static void 114mt7603_phy_init(struct mt7603_dev *dev) 115{ 116 int rx_chains = dev->mphy.antenna_mask; 117 int tx_chains = hweight8(rx_chains) - 1; 118 119 mt76_rmw(dev, MT_WF_RMAC_RMCR, 120 (MT_WF_RMAC_RMCR_SMPS_MODE | 121 MT_WF_RMAC_RMCR_RX_STREAMS), 122 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | 123 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); 124 125 mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS, 126 tx_chains); 127 128 dev->agc0 = mt76_rr(dev, MT_AGC(0)); 129 dev->agc3 = mt76_rr(dev, MT_AGC(3)); 130} 131 132static void 133mt7603_mac_init(struct mt7603_dev *dev) 134{ 135 u8 bc_addr[ETH_ALEN]; 136 u32 addr; 137 int i; 138 139 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0, 140 (MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 141 (MT_AGG_SIZE_LIMIT(1) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 142 (MT_AGG_SIZE_LIMIT(2) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 143 (MT_AGG_SIZE_LIMIT(3) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT)); 144 145 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1, 146 (MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 147 (MT_AGG_SIZE_LIMIT(5) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 148 (MT_AGG_SIZE_LIMIT(6) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 149 (MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT)); 150 151 mt76_wr(dev, MT_AGG_LIMIT, 152 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | 153 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | 154 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | 155 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); 156 157 mt76_wr(dev, MT_AGG_LIMIT_1, 158 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | 159 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | 160 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | 161 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); 162 163 mt76_wr(dev, MT_AGG_CONTROL, 164 FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) | 165 FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) | 166 MT_AGG_CONTROL_NO_BA_AR_RULE); 167 168 mt76_wr(dev, MT_AGG_RETRY_CONTROL, 169 FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) | 170 FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15)); 171 172 mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP | 173 FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 4096)); 174 175 mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13)); 176 mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13)); 177 178 mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31)); 179 180 mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT); 181 mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000); 182 183 mt76_wr(dev, MT_WF_RFCR1, 0); 184 185 mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE); 186 187 if (is_mt7628(dev)) { 188 mt76_set(dev, MT_TMAC_TCR, 189 MT_TMAC_TCR_TXOP_BURST_STOP | BIT(1) | BIT(0)); 190 mt76_set(dev, MT_TXREQ, BIT(27)); 191 mt76_set(dev, MT_AGG_TMP, GENMASK(4, 2)); 192 } 193 194 mt7603_set_tmac_template(dev); 195 196 /* Enable RX group to HIF */ 197 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR); 198 mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS); 199 200 /* Enable RX group to MCU */ 201 mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11)); 202 203 mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3); 204 mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN); 205 206 /* include preamble detection in CCA trigger signal */ 207 mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2); 208 209 mt76_wr(dev, MT_RXREQ, 4); 210 211 /* Configure all rx packets to HIF */ 212 mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000); 213 214 /* Configure MCU txs selection with aggregation */ 215 mt76_wr(dev, MT_DMA_TCFR0, 216 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */ 217 MT_DMA_TCFR_TXS_AGGR_COUNT); 218 219 /* Configure HIF txs selection with aggregation */ 220 mt76_wr(dev, MT_DMA_TCFR1, 221 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */ 222 MT_DMA_TCFR_TXS_AGGR_COUNT | /* Maximum count */ 223 MT_DMA_TCFR_TXS_BIT_MAP); 224 225 mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR); 226 227 for (i = 0; i < MT7603_WTBL_SIZE; i++) 228 mt7603_wtbl_clear(dev, i); 229 230 eth_broadcast_addr(bc_addr); 231 mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, -1, bc_addr); 232 dev->global_sta.wcid.idx = MT7603_WTBL_RESERVED; 233 rcu_assign_pointer(dev->mt76.wcid[MT7603_WTBL_RESERVED], 234 &dev->global_sta.wcid); 235 236 mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2); 237 mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2); 238 239 mt76_wr(dev, MT_AGG_ARUCR, 240 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) | 241 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) | 242 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) | 243 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) | 244 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) | 245 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) | 246 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) | 247 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1)); 248 249 mt76_wr(dev, MT_AGG_ARDCR, 250 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) | 251 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) | 252 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) | 253 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) | 254 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) | 255 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) | 256 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) | 257 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1)); 258 259 mt76_wr(dev, MT_AGG_ARCR, 260 (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) | 261 MT_AGG_ARCR_RATE_DOWN_RATIO_EN | 262 FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) | 263 FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4))); 264 265 mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE); 266 267 mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER); 268 mt76_clear(dev, MT_SEC_SCR, BIT(18)); 269 270 /* Set secondary beacon time offsets */ 271 for (i = 0; i <= 4; i++) 272 mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET, 273 (i + 1) * (20 + 4096)); 274} 275 276static int 277mt7603_init_hardware(struct mt7603_dev *dev) 278{ 279 int i, ret; 280 281 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 282 283 ret = mt7603_eeprom_init(dev); 284 if (ret < 0) 285 return ret; 286 287 ret = mt7603_dma_init(dev); 288 if (ret) 289 return ret; 290 291 mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850); 292 mt7603_mac_dma_start(dev); 293 dev->rxfilter = mt76_rr(dev, MT_WF_RFCR); 294 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 295 296 for (i = 0; i < MT7603_WTBL_SIZE; i++) { 297 mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE | 298 FIELD_PREP(MT_PSE_RTA_TAG_ID, i)); 299 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); 300 } 301 302 ret = mt7603_mcu_init(dev); 303 if (ret) 304 return ret; 305 306 mt7603_dma_sched_init(dev); 307 mt7603_mcu_set_eeprom(dev); 308 mt7603_phy_init(dev); 309 mt7603_mac_init(dev); 310 311 return 0; 312} 313 314static const struct ieee80211_iface_limit if_limits[] = { 315 { 316 .max = 1, 317 .types = BIT(NL80211_IFTYPE_ADHOC) 318 }, { 319 .max = MT7603_MAX_INTERFACES, 320 .types = BIT(NL80211_IFTYPE_STATION) | 321#ifdef CONFIG_MAC80211_MESH 322 BIT(NL80211_IFTYPE_MESH_POINT) | 323#endif 324 BIT(NL80211_IFTYPE_P2P_CLIENT) | 325 BIT(NL80211_IFTYPE_P2P_GO) | 326 BIT(NL80211_IFTYPE_AP) 327 }, 328}; 329 330static const struct ieee80211_iface_combination if_comb[] = { 331 { 332 .limits = if_limits, 333 .n_limits = ARRAY_SIZE(if_limits), 334 .max_interfaces = 4, 335 .num_different_channels = 1, 336 .beacon_int_infra_match = true, 337 } 338}; 339 340static void mt7603_led_set_config(struct mt76_phy *mphy, u8 delay_on, 341 u8 delay_off) 342{ 343 struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, 344 mt76); 345 u32 val, addr; 346 347 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 348 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 349 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 350 351 addr = mt7603_reg_map(dev, MT_LED_STATUS_0(mphy->leds.pin)); 352 mt76_wr(dev, addr, val); 353 addr = mt7603_reg_map(dev, MT_LED_STATUS_1(mphy->leds.pin)); 354 mt76_wr(dev, addr, val); 355 356 val = MT_LED_CTRL_REPLAY(mphy->leds.pin) | 357 MT_LED_CTRL_KICK(mphy->leds.pin); 358 if (mphy->leds.al) 359 val |= MT_LED_CTRL_POLARITY(mphy->leds.pin); 360 addr = mt7603_reg_map(dev, MT_LED_CTRL); 361 mt76_wr(dev, addr, val); 362} 363 364static int mt7603_led_set_blink(struct led_classdev *led_cdev, 365 unsigned long *delay_on, 366 unsigned long *delay_off) 367{ 368 struct mt76_phy *mphy = container_of(led_cdev, struct mt76_phy, 369 leds.cdev); 370 u8 delta_on, delta_off; 371 372 delta_off = max_t(u8, *delay_off / 10, 1); 373 delta_on = max_t(u8, *delay_on / 10, 1); 374 375 mt7603_led_set_config(mphy, delta_on, delta_off); 376 return 0; 377} 378 379static void mt7603_led_set_brightness(struct led_classdev *led_cdev, 380 enum led_brightness brightness) 381{ 382 struct mt76_phy *mphy = container_of(led_cdev, struct mt76_phy, 383 leds.cdev); 384 385 if (!brightness) 386 mt7603_led_set_config(mphy, 0, 0xff); 387 else 388 mt7603_led_set_config(mphy, 0xff, 0); 389} 390 391static u32 __mt7603_reg_addr(struct mt7603_dev *dev, u32 addr) 392{ 393 if (addr < 0x100000) 394 return addr; 395 396 return mt7603_reg_map(dev, addr); 397} 398 399static u32 mt7603_rr(struct mt76_dev *mdev, u32 offset) 400{ 401 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 402 u32 addr = __mt7603_reg_addr(dev, offset); 403 404 return dev->bus_ops->rr(mdev, addr); 405} 406 407static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val) 408{ 409 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 410 u32 addr = __mt7603_reg_addr(dev, offset); 411 412 dev->bus_ops->wr(mdev, addr, val); 413} 414 415static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 416{ 417 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 418 u32 addr = __mt7603_reg_addr(dev, offset); 419 420 return dev->bus_ops->rmw(mdev, addr, mask, val); 421} 422 423static void 424mt7603_regd_notifier(struct wiphy *wiphy, 425 struct regulatory_request *request) 426{ 427 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 428 struct mt7603_dev *dev = hw->priv; 429 430 dev->mt76.region = request->dfs_region; 431 dev->ed_monitor = dev->ed_monitor_enabled && 432 dev->mt76.region == NL80211_DFS_ETSI; 433} 434 435static int 436mt7603_txpower_signed(int val) 437{ 438 bool sign = val & BIT(6); 439 440 if (!(val & BIT(7))) 441 return 0; 442 443 val &= GENMASK(5, 0); 444 if (!sign) 445 val = -val; 446 447 return val; 448} 449 450static void 451mt7603_init_txpower(struct mt7603_dev *dev, 452 struct ieee80211_supported_band *sband) 453{ 454 struct ieee80211_channel *chan; 455 u8 *eeprom = (u8 *)dev->mt76.eeprom.data; 456 int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7); 457 u8 *rate_power = &eeprom[MT_EE_TX_POWER_CCK]; 458 bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1); 459 int max_offset, cur_offset; 460 int i; 461 462 if (ext_pa && is_mt7603(dev)) 463 target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7); 464 465 if (target_power & BIT(6)) 466 target_power = -(target_power & GENMASK(5, 0)); 467 468 max_offset = 0; 469 for (i = 0; i < 14; i++) { 470 cur_offset = mt7603_txpower_signed(rate_power[i]); 471 max_offset = max(max_offset, cur_offset); 472 } 473 474 target_power += max_offset; 475 476 dev->tx_power_limit = target_power; 477 dev->mphy.txpower_cur = target_power; 478 479 target_power = DIV_ROUND_UP(target_power, 2); 480 481 /* add 3 dBm for 2SS devices (combined output) */ 482 if (dev->mphy.antenna_mask & BIT(1)) 483 target_power += 3; 484 485 for (i = 0; i < sband->n_channels; i++) { 486 chan = &sband->channels[i]; 487 chan->max_power = min_t(int, chan->max_reg_power, target_power); 488 chan->orig_mpwr = target_power; 489 } 490} 491 492int mt7603_register_device(struct mt7603_dev *dev) 493{ 494 struct mt76_bus_ops *bus_ops; 495 struct ieee80211_hw *hw = mt76_hw(dev); 496 struct wiphy *wiphy = hw->wiphy; 497 int ret; 498 499 dev->bus_ops = dev->mt76.bus; 500 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 501 GFP_KERNEL); 502 if (!bus_ops) 503 return -ENOMEM; 504 505 bus_ops->rr = mt7603_rr; 506 bus_ops->wr = mt7603_wr; 507 bus_ops->rmw = mt7603_rmw; 508 dev->mt76.bus = bus_ops; 509 510 spin_lock_init(&dev->ps_lock); 511 512 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7603_mac_work); 513 tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet); 514 515 dev->slottime = 9; 516 dev->sensitivity_limit = 28; 517 dev->dynamic_sensitivity = true; 518 519 ret = mt7603_init_hardware(dev); 520 if (ret) 521 return ret; 522 523 hw->queues = 4; 524 hw->max_rates = 3; 525 hw->max_report_rates = 7; 526 hw->max_rate_tries = 11; 527 hw->max_tx_fragments = 1; 528 529 hw->radiotap_timestamp.units_pos = 530 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 531 532 hw->sta_data_size = sizeof(struct mt7603_sta); 533 hw->vif_data_size = sizeof(struct mt7603_vif); 534 535 wiphy->iface_combinations = if_comb; 536 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 537 538 ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN); 539 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); 540 ieee80211_hw_set(hw, NEEDS_UNIQUE_STA_ADDR); 541 542 /* init led callbacks */ 543 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 544 dev->mphy.leds.cdev.brightness_set = mt7603_led_set_brightness; 545 dev->mphy.leds.cdev.blink_set = mt7603_led_set_blink; 546 } 547 548 wiphy->reg_notifier = mt7603_regd_notifier; 549 550 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 551 ARRAY_SIZE(mt76_rates)); 552 if (ret) 553 return ret; 554 555 mt7603_init_debugfs(dev); 556 mt7603_init_txpower(dev, &dev->mphy.sband_2g.sband); 557 558 return 0; 559} 560 561void mt7603_unregister_device(struct mt7603_dev *dev) 562{ 563 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 564 mt76_unregister_device(&dev->mt76); 565 mt7603_mcu_exit(dev); 566 mt7603_dma_cleanup(dev); 567 mt76_free_device(&dev->mt76); 568} 569