1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
5 * Copyright (C) 2018-2024 Intel Corporation
6 */
7#ifndef __IWL_CONFIG_H__
8#define __IWL_CONFIG_H__
9
10#include <linux/types.h>
11#include <linux/netdevice.h>
12#include <linux/ieee80211.h>
13#include <linux/nl80211.h>
14#include "iwl-csr.h"
15#include "iwl-drv.h"
16
17enum iwl_device_family {
18	IWL_DEVICE_FAMILY_UNDEFINED,
19	IWL_DEVICE_FAMILY_1000,
20	IWL_DEVICE_FAMILY_100,
21	IWL_DEVICE_FAMILY_2000,
22	IWL_DEVICE_FAMILY_2030,
23	IWL_DEVICE_FAMILY_105,
24	IWL_DEVICE_FAMILY_135,
25	IWL_DEVICE_FAMILY_5000,
26	IWL_DEVICE_FAMILY_5150,
27	IWL_DEVICE_FAMILY_6000,
28	IWL_DEVICE_FAMILY_6000i,
29	IWL_DEVICE_FAMILY_6005,
30	IWL_DEVICE_FAMILY_6030,
31	IWL_DEVICE_FAMILY_6050,
32	IWL_DEVICE_FAMILY_6150,
33	IWL_DEVICE_FAMILY_7000,
34	IWL_DEVICE_FAMILY_8000,
35	IWL_DEVICE_FAMILY_9000,
36	IWL_DEVICE_FAMILY_22000,
37	IWL_DEVICE_FAMILY_AX210,
38	IWL_DEVICE_FAMILY_BZ,
39	IWL_DEVICE_FAMILY_SC,
40};
41
42/*
43 * LED mode
44 *    IWL_LED_DEFAULT:  use device default
45 *    IWL_LED_RF_STATE: turn LED on/off based on RF state
46 *			LED ON  = RF ON
47 *			LED OFF = RF OFF
48 *    IWL_LED_BLINK:    adjust led blink rate based on blink table
49 *    IWL_LED_DISABLE:	led disabled
50 */
51enum iwl_led_mode {
52	IWL_LED_DEFAULT,
53	IWL_LED_RF_STATE,
54	IWL_LED_BLINK,
55	IWL_LED_DISABLE,
56};
57
58/**
59 * enum iwl_nvm_type - nvm formats
60 * @IWL_NVM: the regular format
61 * @IWL_NVM_EXT: extended NVM format
62 * @IWL_NVM_SDP: NVM format used by 3168 series
63 */
64enum iwl_nvm_type {
65	IWL_NVM,
66	IWL_NVM_EXT,
67	IWL_NVM_SDP,
68};
69
70/*
71 * This is the threshold value of plcp error rate per 100mSecs.  It is
72 * used to set and check for the validity of plcp_delta.
73 */
74#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN		1
75#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF		50
76#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF	100
77#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF	200
78#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX		255
79#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE	0
80
81/* TX queue watchdog timeouts in mSecs */
82#define IWL_WATCHDOG_DISABLED	0
83#define IWL_DEF_WD_TIMEOUT	2500
84#define IWL_LONG_WD_TIMEOUT	10000
85#define IWL_MAX_WD_TIMEOUT	120000
86
87#define IWL_DEFAULT_MAX_TX_POWER 22
88#define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\
89				 NETIF_F_TSO | NETIF_F_TSO6)
90#define IWL_CSUM_NETIF_FLAGS_MASK (IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM)
91
92/* Antenna presence definitions */
93#define	ANT_NONE	0x0
94#define	ANT_INVALID	0xff
95#define	ANT_A		BIT(0)
96#define	ANT_B		BIT(1)
97#define ANT_C		BIT(2)
98#define	ANT_AB		(ANT_A | ANT_B)
99#define	ANT_AC		(ANT_A | ANT_C)
100#define ANT_BC		(ANT_B | ANT_C)
101#define ANT_ABC		(ANT_A | ANT_B | ANT_C)
102
103
104static inline u8 num_of_ant(u8 mask)
105{
106	return  !!((mask) & ANT_A) +
107		!!((mask) & ANT_B) +
108		!!((mask) & ANT_C);
109}
110
111/**
112 * struct iwl_base_params - params not likely to change within a device family
113 * @max_ll_items: max number of OTP blocks
114 * @shadow_ram_support: shadow support for OTP memory
115 * @led_compensation: compensate on the led on/off time per HW according
116 *	to the deviation to achieve the desired led frequency.
117 *	The detail algorithm is described in iwl-led.c
118 * @wd_timeout: TX queues watchdog timeout
119 * @max_event_log_size: size of event log buffer size for ucode event logging
120 * @shadow_reg_enable: HW shadow register support
121 * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command
122 *	is in flight. This is due to a HW bug in 7260, 3160 and 7265.
123 * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled.
124 * @max_tfd_queue_size: max number of entries in tfd queue.
125 */
126struct iwl_base_params {
127	unsigned int wd_timeout;
128
129	u16 eeprom_size;
130	u16 max_event_log_size;
131
132	u8 pll_cfg:1, /* for iwl_pcie_apm_init() */
133	   shadow_ram_support:1,
134	   shadow_reg_enable:1,
135	   pcie_l1_allowed:1,
136	   apmg_wake_up_wa:1,
137	   scd_chain_ext_wa:1;
138
139	u16 num_of_queues;	/* def: HW dependent */
140	u32 max_tfd_queue_size;	/* def: HW dependent */
141
142	u8 max_ll_items;
143	u8 led_compensation;
144};
145
146/*
147 * @stbc: support Tx STBC and 1*SS Rx STBC
148 * @ldpc: support Tx/Rx with LDPC
149 * @use_rts_for_aggregation: use rts/cts protection for HT traffic
150 * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40
151 */
152struct iwl_ht_params {
153	u8 ht_greenfield_support:1,
154	   stbc:1,
155	   ldpc:1,
156	   use_rts_for_aggregation:1;
157	u8 ht40_bands;
158};
159
160/*
161 * Tx-backoff threshold
162 * @temperature: The threshold in Celsius
163 * @backoff: The tx-backoff in uSec
164 */
165struct iwl_tt_tx_backoff {
166	s32 temperature;
167	u32 backoff;
168};
169
170#define TT_TX_BACKOFF_SIZE 6
171
172/**
173 * struct iwl_tt_params - thermal throttling parameters
174 * @ct_kill_entry: CT Kill entry threshold
175 * @ct_kill_exit: CT Kill exit threshold
176 * @ct_kill_duration: The time  intervals (in uSec) in which the driver needs
177 *	to checks whether to exit CT Kill.
178 * @dynamic_smps_entry: Dynamic SMPS entry threshold
179 * @dynamic_smps_exit: Dynamic SMPS exit threshold
180 * @tx_protection_entry: TX protection entry threshold
181 * @tx_protection_exit: TX protection exit threshold
182 * @tx_backoff: Array of thresholds for tx-backoff , in ascending order.
183 * @support_ct_kill: Support CT Kill?
184 * @support_dynamic_smps: Support dynamic SMPS?
185 * @support_tx_protection: Support tx protection?
186 * @support_tx_backoff: Support tx-backoff?
187 */
188struct iwl_tt_params {
189	u32 ct_kill_entry;
190	u32 ct_kill_exit;
191	u32 ct_kill_duration;
192	u32 dynamic_smps_entry;
193	u32 dynamic_smps_exit;
194	u32 tx_protection_entry;
195	u32 tx_protection_exit;
196	struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE];
197	u8 support_ct_kill:1,
198	   support_dynamic_smps:1,
199	   support_tx_protection:1,
200	   support_tx_backoff:1;
201};
202
203/*
204 * information on how to parse the EEPROM
205 */
206#define EEPROM_REG_BAND_1_CHANNELS		0x08
207#define EEPROM_REG_BAND_2_CHANNELS		0x26
208#define EEPROM_REG_BAND_3_CHANNELS		0x42
209#define EEPROM_REG_BAND_4_CHANNELS		0x5C
210#define EEPROM_REG_BAND_5_CHANNELS		0x74
211#define EEPROM_REG_BAND_24_HT40_CHANNELS	0x82
212#define EEPROM_REG_BAND_52_HT40_CHANNELS	0x92
213#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS	0x80
214#define EEPROM_REGULATORY_BAND_NO_HT40		0
215
216/* lower blocks contain EEPROM image and calibration data */
217#define OTP_LOW_IMAGE_SIZE_2K		(2 * 512 * sizeof(u16))  /*  2 KB */
218#define OTP_LOW_IMAGE_SIZE_16K		(16 * 512 * sizeof(u16)) /* 16 KB */
219#define OTP_LOW_IMAGE_SIZE_32K		(32 * 512 * sizeof(u16)) /* 32 KB */
220
221struct iwl_eeprom_params {
222	const u8 regulatory_bands[7];
223	bool enhanced_txpower;
224};
225
226/* Tx-backoff power threshold
227 * @pwr: The power limit in mw
228 * @backoff: The tx-backoff in uSec
229 */
230struct iwl_pwr_tx_backoff {
231	u32 pwr;
232	u32 backoff;
233};
234
235enum iwl_cfg_trans_ltr_delay {
236	IWL_CFG_TRANS_LTR_DELAY_NONE	= 0,
237	IWL_CFG_TRANS_LTR_DELAY_200US	= 1,
238	IWL_CFG_TRANS_LTR_DELAY_2500US	= 2,
239	IWL_CFG_TRANS_LTR_DELAY_1820US	= 3,
240};
241
242/**
243 * struct iwl_cfg_trans - information needed to start the trans
244 *
245 * These values are specific to the device ID and do not change when
246 * multiple configs are used for a single device ID.  They values are
247 * used, among other things, to boot the NIC so that the HW REV or
248 * RFID can be read before deciding the remaining parameters to use.
249 *
250 * @base_params: pointer to basic parameters
251 * @device_family: the device family
252 * @umac_prph_offset: offset to add to UMAC periphery address
253 * @xtal_latency: power up latency to get the xtal stabilized
254 * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY
255 * @rf_id: need to read rf_id to determine the firmware image
256 * @gen2: 22000 and on transport operation
257 * @mq_rx_supported: multi-queue rx support
258 * @integrated: discrete or integrated
259 * @low_latency_xtal: use the low latency xtal if supported
260 * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
261 * @imr_enabled: use the IMR if supported.
262 */
263struct iwl_cfg_trans_params {
264	const struct iwl_base_params *base_params;
265	enum iwl_device_family device_family;
266	u32 umac_prph_offset;
267	u32 xtal_latency;
268	u32 extra_phy_cfg_flags;
269	u32 rf_id:1,
270	    gen2:1,
271	    mq_rx_supported:1,
272	    integrated:1,
273	    low_latency_xtal:1,
274	    bisr_workaround:1,
275	    ltr_delay:2,
276	    imr_enabled:1;
277};
278
279/**
280 * struct iwl_fw_mon_reg - FW monitor register info
281 * @addr: register address
282 * @mask: register mask
283 */
284struct iwl_fw_mon_reg {
285	u32 addr;
286	u32 mask;
287};
288
289/**
290 * struct iwl_fw_mon_regs - FW monitor registers
291 * @write_ptr: write pointer register
292 * @cycle_cnt: cycle count register
293 * @cur_frag: current fragment in use
294 */
295struct iwl_fw_mon_regs {
296	struct iwl_fw_mon_reg write_ptr;
297	struct iwl_fw_mon_reg cycle_cnt;
298	struct iwl_fw_mon_reg cur_frag;
299};
300
301/**
302 * struct iwl_cfg
303 * @trans: the trans-specific configuration part
304 * @name: Official name of the device
305 * @fw_name_pre: Firmware filename prefix. The api version and extension
306 *	(.ucode) will be added to filename before loading from disk. The
307 *	filename is constructed as <fw_name_pre>-<api>.ucode.
308 * @fw_name_mac: MAC name for this config, the remaining pieces of the
309 *	name will be generated dynamically
310 * @ucode_api_max: Highest version of uCode API supported by driver.
311 * @ucode_api_min: Lowest version of uCode API supported by driver.
312 * @max_inst_size: The maximal length of the fw inst section (only DVM)
313 * @max_data_size: The maximal length of the fw data section (only DVM)
314 * @valid_tx_ant: valid transmit antenna
315 * @valid_rx_ant: valid receive antenna
316 * @non_shared_ant: the antenna that is for WiFi only
317 * @nvm_ver: NVM version
318 * @nvm_calib_ver: NVM calibration version
319 * @ht_params: point to ht parameters
320 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
321 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
322 * @tx_with_siso_diversity: 1x1 device with tx antenna diversity
323 * @internal_wimax_coex: internal wifi/wimax combo device
324 * @high_temp: Is this NIC is designated to be in high temperature.
325 * @host_interrupt_operation_mode: device needs host interrupt operation
326 *	mode set
327 * @nvm_hw_section_num: the ID of the HW NVM section
328 * @mac_addr_from_csr: read HW address from CSR registers at this offset
329 * @features: hw features, any combination of feature_passlist
330 * @pwr_tx_backoffs: translation table between power limits and backoffs
331 * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
332 * @dccm_offset: offset from which DCCM begins
333 * @dccm_len: length of DCCM (including runtime stack CCM)
334 * @dccm2_offset: offset from which the second DCCM begins
335 * @dccm2_len: length of the second DCCM
336 * @smem_offset: offset from which the SMEM begins
337 * @smem_len: the length of SMEM
338 * @vht_mu_mimo_supported: VHT MU-MIMO support
339 * @cdb: CDB support
340 * @nvm_type: see &enum iwl_nvm_type
341 * @d3_debug_data_base_addr: base address where D3 debug data is stored
342 * @d3_debug_data_length: length of the D3 debug data
343 * @min_txq_size: minimum number of slots required in a TX queue
344 * @uhb_supported: ultra high band channels supported
345 * @min_ba_txq_size: minimum number of slots required in a TX queue which
346 *	based on hardware support (HE - 256, EHT - 1K).
347 * @num_rbds: number of receive buffer descriptors to use
348 *	(only used for multi-queue capable devices)
349 *
350 * We enable the driver to be backward compatible wrt. hardware features.
351 * API differences in uCode shouldn't be handled here but through TLVs
352 * and/or the uCode API version instead.
353 */
354struct iwl_cfg {
355	struct iwl_cfg_trans_params trans;
356	/* params specific to an individual device within a device family */
357	const char *name;
358	const char *fw_name_pre;
359	const char *fw_name_mac;
360	/* params likely to change within a device family */
361	const struct iwl_ht_params *ht_params;
362	const struct iwl_eeprom_params *eeprom_params;
363	const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
364	const char *default_nvm_file_C_step;
365	const struct iwl_tt_params *thermal_params;
366	enum iwl_led_mode led_mode;
367	enum iwl_nvm_type nvm_type;
368	u32 max_data_size;
369	u32 max_inst_size;
370	netdev_features_t features;
371	u32 dccm_offset;
372	u32 dccm_len;
373	u32 dccm2_offset;
374	u32 dccm2_len;
375	u32 smem_offset;
376	u32 smem_len;
377	u16 nvm_ver;
378	u16 nvm_calib_ver;
379	u32 rx_with_siso_diversity:1,
380	    tx_with_siso_diversity:1,
381	    internal_wimax_coex:1,
382	    host_interrupt_operation_mode:1,
383	    high_temp:1,
384	    mac_addr_from_csr:10,
385	    lp_xtal_workaround:1,
386	    apmg_not_supported:1,
387	    vht_mu_mimo_supported:1,
388	    cdb:1,
389	    dbgc_supported:1,
390	    uhb_supported:1;
391	u8 valid_tx_ant;
392	u8 valid_rx_ant;
393	u8 non_shared_ant;
394	u8 nvm_hw_section_num;
395	u8 max_tx_agg_size;
396	u8 ucode_api_max;
397	u8 ucode_api_min;
398	u16 num_rbds;
399	u32 min_umac_error_event_table;
400	u32 d3_debug_data_base_addr;
401	u32 d3_debug_data_length;
402	u32 min_txq_size;
403	u32 gp2_reg_addr;
404	u32 min_ba_txq_size;
405	const struct iwl_fw_mon_regs mon_dram_regs;
406	const struct iwl_fw_mon_regs mon_smem_regs;
407	const struct iwl_fw_mon_regs mon_dbgi_regs;
408};
409
410#define IWL_CFG_ANY (~0)
411
412#define IWL_CFG_MAC_TYPE_PU		0x31
413#define IWL_CFG_MAC_TYPE_TH		0x32
414#define IWL_CFG_MAC_TYPE_QU		0x33
415#define IWL_CFG_MAC_TYPE_QUZ		0x35
416#define IWL_CFG_MAC_TYPE_SO		0x37
417#define IWL_CFG_MAC_TYPE_SOF		0x43
418#define IWL_CFG_MAC_TYPE_MA		0x44
419#define IWL_CFG_MAC_TYPE_BZ		0x46
420#define IWL_CFG_MAC_TYPE_GL		0x47
421#define IWL_CFG_MAC_TYPE_SC		0x48
422#define IWL_CFG_MAC_TYPE_SC2		0x49
423#define IWL_CFG_MAC_TYPE_SC2F		0x4A
424
425#define IWL_CFG_RF_TYPE_TH		0x105
426#define IWL_CFG_RF_TYPE_TH1		0x108
427#define IWL_CFG_RF_TYPE_JF2		0x105
428#define IWL_CFG_RF_TYPE_JF1		0x108
429#define IWL_CFG_RF_TYPE_HR2		0x10A
430#define IWL_CFG_RF_TYPE_HR1		0x10C
431#define IWL_CFG_RF_TYPE_GF		0x10D
432#define IWL_CFG_RF_TYPE_MR		0x110
433#define IWL_CFG_RF_TYPE_MS		0x111
434#define IWL_CFG_RF_TYPE_FM		0x112
435#define IWL_CFG_RF_TYPE_WH		0x113
436
437#define IWL_CFG_RF_ID_TH		0x1
438#define IWL_CFG_RF_ID_TH1		0x1
439#define IWL_CFG_RF_ID_JF		0x3
440#define IWL_CFG_RF_ID_JF1		0x6
441#define IWL_CFG_RF_ID_JF1_DIV		0xA
442#define IWL_CFG_RF_ID_HR		0x7
443#define IWL_CFG_RF_ID_HR1		0x4
444
445#define IWL_CFG_NO_160			0x1
446#define IWL_CFG_160			0x0
447
448#define IWL_CFG_NO_320			0x1
449#define IWL_CFG_320			0x0
450
451#define IWL_CFG_CORES_BT		0x0
452#define IWL_CFG_CORES_BT_GNSS		0x5
453
454#define IWL_CFG_NO_CDB			0x0
455#define IWL_CFG_CDB			0x1
456
457#define IWL_CFG_NO_JACKET		0x0
458#define IWL_CFG_IS_JACKET		0x1
459
460#define IWL_SUBDEVICE_RF_ID(subdevice)	((u16)((subdevice) & 0x00F0) >> 4)
461#define IWL_SUBDEVICE_NO_160(subdevice)	((u16)((subdevice) & 0x0200) >> 9)
462#define IWL_SUBDEVICE_CORES(subdevice)	((u16)((subdevice) & 0x1C00) >> 10)
463
464struct iwl_dev_info {
465	u16 device;
466	u16 subdevice;
467	u16 mac_type;
468	u16 rf_type;
469	u8 mac_step;
470	u8 rf_step;
471	u8 rf_id;
472	u8 no_160;
473	u8 cores;
474	u8 cdb;
475	u8 jacket;
476	const struct iwl_cfg *cfg;
477	const char *name;
478};
479
480#if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS)
481extern const struct iwl_dev_info iwl_dev_info_table[];
482extern const unsigned int iwl_dev_info_table_size;
483const struct iwl_dev_info *
484iwl_pci_find_dev_info(u16 device, u16 subsystem_device,
485		      u16 mac_type, u8 mac_step, u16 rf_type, u8 cdb,
486		      u8 jacket, u8 rf_id, u8 no_160, u8 cores, u8 rf_step);
487#endif
488
489/*
490 * This list declares the config structures for all devices.
491 */
492extern const struct iwl_cfg_trans_params iwl9000_trans_cfg;
493extern const struct iwl_cfg_trans_params iwl9560_trans_cfg;
494extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg;
495extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg;
496extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg;
497extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg;
498extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg;
499extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
500extern const struct iwl_cfg_trans_params iwl_so_trans_cfg;
501extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg;
502extern const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg;
503extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
504extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg;
505extern const struct iwl_cfg_trans_params iwl_sc_trans_cfg;
506extern const char iwl9162_name[];
507extern const char iwl9260_name[];
508extern const char iwl9260_1_name[];
509extern const char iwl9270_name[];
510extern const char iwl9461_name[];
511extern const char iwl9462_name[];
512extern const char iwl9560_name[];
513extern const char iwl9162_160_name[];
514extern const char iwl9260_160_name[];
515extern const char iwl9270_160_name[];
516extern const char iwl9461_160_name[];
517extern const char iwl9462_160_name[];
518extern const char iwl9560_160_name[];
519extern const char iwl9260_killer_1550_name[];
520extern const char iwl9560_killer_1550i_name[];
521extern const char iwl9560_killer_1550s_name[];
522extern const char iwl_ax200_name[];
523extern const char iwl_ax203_name[];
524extern const char iwl_ax204_name[];
525extern const char iwl_ax201_name[];
526extern const char iwl_ax101_name[];
527extern const char iwl_ax200_killer_1650w_name[];
528extern const char iwl_ax200_killer_1650x_name[];
529extern const char iwl_ax201_killer_1650s_name[];
530extern const char iwl_ax201_killer_1650i_name[];
531extern const char iwl_ax210_killer_1675w_name[];
532extern const char iwl_ax210_killer_1675x_name[];
533extern const char iwl9560_killer_1550i_160_name[];
534extern const char iwl9560_killer_1550s_160_name[];
535extern const char iwl_ax211_killer_1675s_name[];
536extern const char iwl_ax211_killer_1675i_name[];
537extern const char iwl_ax411_killer_1690s_name[];
538extern const char iwl_ax411_killer_1690i_name[];
539extern const char iwl_ax211_name[];
540extern const char iwl_ax221_name[];
541extern const char iwl_ax231_name[];
542extern const char iwl_ax411_name[];
543extern const char iwl_bz_name[];
544extern const char iwl_mtp_name[];
545extern const char iwl_sc_name[];
546extern const char iwl_sc2_name[];
547extern const char iwl_sc2f_name[];
548#if IS_ENABLED(CONFIG_IWLDVM)
549extern const struct iwl_cfg iwl5300_agn_cfg;
550extern const struct iwl_cfg iwl5100_agn_cfg;
551extern const struct iwl_cfg iwl5350_agn_cfg;
552extern const struct iwl_cfg iwl5100_bgn_cfg;
553extern const struct iwl_cfg iwl5100_abg_cfg;
554extern const struct iwl_cfg iwl5150_agn_cfg;
555extern const struct iwl_cfg iwl5150_abg_cfg;
556extern const struct iwl_cfg iwl6005_2agn_cfg;
557extern const struct iwl_cfg iwl6005_2abg_cfg;
558extern const struct iwl_cfg iwl6005_2bg_cfg;
559extern const struct iwl_cfg iwl6005_2agn_sff_cfg;
560extern const struct iwl_cfg iwl6005_2agn_d_cfg;
561extern const struct iwl_cfg iwl6005_2agn_mow1_cfg;
562extern const struct iwl_cfg iwl6005_2agn_mow2_cfg;
563extern const struct iwl_cfg iwl1030_bgn_cfg;
564extern const struct iwl_cfg iwl1030_bg_cfg;
565extern const struct iwl_cfg iwl6030_2agn_cfg;
566extern const struct iwl_cfg iwl6030_2abg_cfg;
567extern const struct iwl_cfg iwl6030_2bgn_cfg;
568extern const struct iwl_cfg iwl6030_2bg_cfg;
569extern const struct iwl_cfg iwl6000i_2agn_cfg;
570extern const struct iwl_cfg iwl6000i_2abg_cfg;
571extern const struct iwl_cfg iwl6000i_2bg_cfg;
572extern const struct iwl_cfg iwl6000_3agn_cfg;
573extern const struct iwl_cfg iwl6050_2agn_cfg;
574extern const struct iwl_cfg iwl6050_2abg_cfg;
575extern const struct iwl_cfg iwl6150_bgn_cfg;
576extern const struct iwl_cfg iwl6150_bg_cfg;
577extern const struct iwl_cfg iwl1000_bgn_cfg;
578extern const struct iwl_cfg iwl1000_bg_cfg;
579extern const struct iwl_cfg iwl100_bgn_cfg;
580extern const struct iwl_cfg iwl100_bg_cfg;
581extern const struct iwl_cfg iwl130_bgn_cfg;
582extern const struct iwl_cfg iwl130_bg_cfg;
583extern const struct iwl_cfg iwl2000_2bgn_cfg;
584extern const struct iwl_cfg iwl2000_2bgn_d_cfg;
585extern const struct iwl_cfg iwl2030_2bgn_cfg;
586extern const struct iwl_cfg iwl6035_2agn_cfg;
587extern const struct iwl_cfg iwl6035_2agn_sff_cfg;
588extern const struct iwl_cfg iwl105_bgn_cfg;
589extern const struct iwl_cfg iwl105_bgn_d_cfg;
590extern const struct iwl_cfg iwl135_bgn_cfg;
591#endif /* CONFIG_IWLDVM */
592#if IS_ENABLED(CONFIG_IWLMVM)
593extern const struct iwl_ht_params iwl_22000_ht_params;
594extern const struct iwl_cfg iwl7260_2ac_cfg;
595extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp;
596extern const struct iwl_cfg iwl7260_2n_cfg;
597extern const struct iwl_cfg iwl7260_n_cfg;
598extern const struct iwl_cfg iwl3160_2ac_cfg;
599extern const struct iwl_cfg iwl3160_2n_cfg;
600extern const struct iwl_cfg iwl3160_n_cfg;
601extern const struct iwl_cfg iwl3165_2ac_cfg;
602extern const struct iwl_cfg iwl3168_2ac_cfg;
603extern const struct iwl_cfg iwl7265_2ac_cfg;
604extern const struct iwl_cfg iwl7265_2n_cfg;
605extern const struct iwl_cfg iwl7265_n_cfg;
606extern const struct iwl_cfg iwl7265d_2ac_cfg;
607extern const struct iwl_cfg iwl7265d_2n_cfg;
608extern const struct iwl_cfg iwl7265d_n_cfg;
609extern const struct iwl_cfg iwl8260_2n_cfg;
610extern const struct iwl_cfg iwl8260_2ac_cfg;
611extern const struct iwl_cfg iwl8265_2ac_cfg;
612extern const struct iwl_cfg iwl8275_2ac_cfg;
613extern const struct iwl_cfg iwl4165_2ac_cfg;
614extern const struct iwl_cfg iwl9260_2ac_cfg;
615extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg;
616extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg;
617extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg;
618extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
619extern const struct iwl_cfg iwl_qu_b0_hr1_b0;
620extern const struct iwl_cfg iwl_qu_c0_hr1_b0;
621extern const struct iwl_cfg iwl_quz_a0_hr1_b0;
622extern const struct iwl_cfg iwl_qu_b0_hr_b0;
623extern const struct iwl_cfg iwl_qu_c0_hr_b0;
624extern const struct iwl_cfg iwl_ax200_cfg_cc;
625extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
626extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0;
627extern const struct iwl_cfg iwl_ax201_cfg_quz_hr;
628extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
629extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
630extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
631extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
632extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
633extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
634extern const struct iwl_cfg killer1650x_2ax_cfg;
635extern const struct iwl_cfg killer1650w_2ax_cfg;
636extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0;
637extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
638extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long;
639extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
640extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
641extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long;
642
643extern const struct iwl_cfg iwl_cfg_ma;
644
645extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0;
646extern const struct iwl_cfg iwl_cfg_so_a0_ms_a0;
647extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0;
648
649extern const struct iwl_cfg iwl_cfg_bz;
650extern const struct iwl_cfg iwl_cfg_gl;
651
652extern const struct iwl_cfg iwl_cfg_sc;
653extern const struct iwl_cfg iwl_cfg_sc2;
654extern const struct iwl_cfg iwl_cfg_sc2f;
655#endif /* CONFIG_IWLMVM */
656
657#endif /* __IWL_CONFIG_H__ */
658