1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2015-2016 Qualcomm Atheros, Inc.
4 */
5
6#ifndef _SWAP_H_
7#define _SWAP_H_
8
9#define ATH10K_SWAP_CODE_SEG_BIN_LEN_MAX	(512 * 1024)
10#define ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ	12
11#define ATH10K_SWAP_CODE_SEG_NUM_MAX		16
12/* Currently only one swap segment is supported */
13#define ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED	1
14
15struct ath10k_fw_file;
16
17struct ath10k_swap_code_seg_tlv {
18	__le32 address;
19	__le32 length;
20	u8 data[];
21} __packed;
22
23struct ath10k_swap_code_seg_tail {
24	u8 magic_signature[ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ];
25	__le32 bmi_write_addr;
26} __packed;
27
28union ath10k_swap_code_seg_item {
29	struct ath10k_swap_code_seg_tlv tlv;
30	struct ath10k_swap_code_seg_tail tail;
31} __packed;
32
33struct ath10k_swap_code_seg_hw_info {
34	/* Swap binary image size */
35	__le32 swap_size;
36	__le32 num_segs;
37
38	/* Swap data size */
39	__le32 size;
40	__le32 size_log2;
41	__le32 bus_addr[ATH10K_SWAP_CODE_SEG_NUM_MAX];
42	__le64 reserved[ATH10K_SWAP_CODE_SEG_NUM_MAX];
43} __packed;
44
45struct ath10k_swap_code_seg_info {
46	struct ath10k_swap_code_seg_hw_info seg_hw_info;
47	void *virt_address[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
48	u32 target_addr;
49	dma_addr_t paddr[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
50};
51
52int ath10k_swap_code_seg_configure(struct ath10k *ar,
53				   const struct ath10k_fw_file *fw_file);
54void ath10k_swap_code_seg_release(struct ath10k *ar,
55				  struct ath10k_fw_file *fw_file);
56int ath10k_swap_code_seg_init(struct ath10k *ar,
57			      struct ath10k_fw_file *fw_file);
58
59#endif
60