1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
7 */
8
9#ifndef _HW_H_
10#define _HW_H_
11
12#include "targaddrs.h"
13
14enum ath10k_bus {
15	ATH10K_BUS_PCI,
16	ATH10K_BUS_AHB,
17	ATH10K_BUS_SDIO,
18	ATH10K_BUS_USB,
19	ATH10K_BUS_SNOC,
20};
21
22#define ATH10K_FW_DIR			"ath10k"
23
24#define QCA988X_2_0_DEVICE_ID_UBNT   (0x11ac)
25#define QCA988X_2_0_DEVICE_ID   (0x003c)
26#define QCA6164_2_1_DEVICE_ID   (0x0041)
27#define QCA6174_2_1_DEVICE_ID   (0x003e)
28#define QCA6174_3_2_DEVICE_ID   (0x0042)
29#define QCA99X0_2_0_DEVICE_ID   (0x0040)
30#define QCA9888_2_0_DEVICE_ID	(0x0056)
31#define QCA9984_1_0_DEVICE_ID	(0x0046)
32#define QCA9377_1_0_DEVICE_ID   (0x0042)
33#define QCA9887_1_0_DEVICE_ID   (0x0050)
34
35/* QCA988X 1.0 definitions (unsupported) */
36#define QCA988X_HW_1_0_CHIP_ID_REV	0x0
37
38/* QCA988X 2.0 definitions */
39#define QCA988X_HW_2_0_VERSION		0x4100016c
40#define QCA988X_HW_2_0_CHIP_ID_REV	0x2
41#define QCA988X_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA988X/hw2.0"
42#define QCA988X_HW_2_0_BOARD_DATA_FILE	"board.bin"
43#define QCA988X_HW_2_0_PATCH_LOAD_ADDR	0x1234
44
45/* QCA9887 1.0 definitions */
46#define QCA9887_HW_1_0_VERSION		0x4100016d
47#define QCA9887_HW_1_0_CHIP_ID_REV	0
48#define QCA9887_HW_1_0_FW_DIR		ATH10K_FW_DIR "/QCA9887/hw1.0"
49#define QCA9887_HW_1_0_BOARD_DATA_FILE	"board.bin"
50#define QCA9887_HW_1_0_PATCH_LOAD_ADDR	0x1234
51
52/* QCA6174 target BMI version signatures */
53#define QCA6174_HW_1_0_VERSION		0x05000000
54#define QCA6174_HW_1_1_VERSION		0x05000001
55#define QCA6174_HW_1_3_VERSION		0x05000003
56#define QCA6174_HW_2_1_VERSION		0x05010000
57#define QCA6174_HW_3_0_VERSION		0x05020000
58#define QCA6174_HW_3_2_VERSION		0x05030000
59
60/* QCA9377 target BMI version signatures */
61#define QCA9377_HW_1_0_DEV_VERSION	0x05020000
62#define QCA9377_HW_1_1_DEV_VERSION	0x05020001
63
64enum qca6174_pci_rev {
65	QCA6174_PCI_REV_1_1 = 0x11,
66	QCA6174_PCI_REV_1_3 = 0x13,
67	QCA6174_PCI_REV_2_0 = 0x20,
68	QCA6174_PCI_REV_3_0 = 0x30,
69};
70
71enum qca6174_chip_id_rev {
72	QCA6174_HW_1_0_CHIP_ID_REV = 0,
73	QCA6174_HW_1_1_CHIP_ID_REV = 1,
74	QCA6174_HW_1_3_CHIP_ID_REV = 2,
75	QCA6174_HW_2_1_CHIP_ID_REV = 4,
76	QCA6174_HW_2_2_CHIP_ID_REV = 5,
77	QCA6174_HW_3_0_CHIP_ID_REV = 8,
78	QCA6174_HW_3_1_CHIP_ID_REV = 9,
79	QCA6174_HW_3_2_CHIP_ID_REV = 10,
80};
81
82enum qca9377_chip_id_rev {
83	QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
84	QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
85};
86
87#define QCA6174_HW_2_1_FW_DIR		ATH10K_FW_DIR "/QCA6174/hw2.1"
88#define QCA6174_HW_2_1_BOARD_DATA_FILE	"board.bin"
89#define QCA6174_HW_2_1_PATCH_LOAD_ADDR	0x1234
90
91#define QCA6174_HW_3_0_FW_DIR		ATH10K_FW_DIR "/QCA6174/hw3.0"
92#define QCA6174_HW_3_0_BOARD_DATA_FILE	"board.bin"
93#define QCA6174_HW_3_0_PATCH_LOAD_ADDR	0x1234
94
95/* QCA99X0 1.0 definitions (unsupported) */
96#define QCA99X0_HW_1_0_CHIP_ID_REV     0x0
97
98/* QCA99X0 2.0 definitions */
99#define QCA99X0_HW_2_0_DEV_VERSION     0x01000000
100#define QCA99X0_HW_2_0_CHIP_ID_REV     0x1
101#define QCA99X0_HW_2_0_FW_DIR          ATH10K_FW_DIR "/QCA99X0/hw2.0"
102#define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
103#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR	0x1234
104
105/* QCA9984 1.0 defines */
106#define QCA9984_HW_1_0_DEV_VERSION	0x1000000
107#define QCA9984_HW_DEV_TYPE		0xa
108#define QCA9984_HW_1_0_CHIP_ID_REV	0x0
109#define QCA9984_HW_1_0_FW_DIR		ATH10K_FW_DIR "/QCA9984/hw1.0"
110#define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin"
111#define QCA9984_HW_1_0_EBOARD_DATA_FILE "eboard.bin"
112#define QCA9984_HW_1_0_PATCH_LOAD_ADDR	0x1234
113
114/* QCA9888 2.0 defines */
115#define QCA9888_HW_2_0_DEV_VERSION	0x1000000
116#define QCA9888_HW_DEV_TYPE		0xc
117#define QCA9888_HW_2_0_CHIP_ID_REV	0x0
118#define QCA9888_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA9888/hw2.0"
119#define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin"
120#define QCA9888_HW_2_0_PATCH_LOAD_ADDR	0x1234
121
122/* QCA9377 1.0 definitions */
123#define QCA9377_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA9377/hw1.0"
124#define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
125#define QCA9377_HW_1_0_PATCH_LOAD_ADDR	0x1234
126
127/* QCA4019 1.0 definitions */
128#define QCA4019_HW_1_0_DEV_VERSION     0x01000000
129#define QCA4019_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA4019/hw1.0"
130#define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin"
131#define QCA4019_HW_1_0_PATCH_LOAD_ADDR  0x1234
132
133/* WCN3990 1.0 definitions */
134#define WCN3990_HW_1_0_DEV_VERSION	ATH10K_HW_WCN3990
135#define WCN3990_HW_1_0_FW_DIR		ATH10K_FW_DIR "/WCN3990/hw1.0"
136
137#define ATH10K_FW_FILE_BASE		"firmware"
138#define ATH10K_FW_API_MAX		6
139#define ATH10K_FW_API_MIN		2
140
141#define ATH10K_FW_API2_FILE		"firmware-2.bin"
142#define ATH10K_FW_API3_FILE		"firmware-3.bin"
143
144/* added support for ATH10K_FW_IE_WMI_OP_VERSION */
145#define ATH10K_FW_API4_FILE		"firmware-4.bin"
146
147/* HTT id conflict fix for management frames over HTT */
148#define ATH10K_FW_API5_FILE		"firmware-5.bin"
149
150/* the firmware-6.bin blob */
151#define ATH10K_FW_API6_FILE		"firmware-6.bin"
152
153#define ATH10K_FW_UTF_FILE		"utf.bin"
154#define ATH10K_FW_UTF_API2_FILE		"utf-2.bin"
155
156#define ATH10K_FW_UTF_FILE_BASE		"utf"
157
158/* includes also the null byte */
159#define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
160#define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
161
162#define ATH10K_BOARD_API2_FILE         "board-2.bin"
163
164#define REG_DUMP_COUNT_QCA988X 60
165
166struct ath10k_fw_ie {
167	__le32 id;
168	__le32 len;
169	u8 data[];
170};
171
172enum ath10k_fw_ie_type {
173	ATH10K_FW_IE_FW_VERSION = 0,
174	ATH10K_FW_IE_TIMESTAMP = 1,
175	ATH10K_FW_IE_FEATURES = 2,
176	ATH10K_FW_IE_FW_IMAGE = 3,
177	ATH10K_FW_IE_OTP_IMAGE = 4,
178
179	/* WMI "operations" interface version, 32 bit value. Supported from
180	 * FW API 4 and above.
181	 */
182	ATH10K_FW_IE_WMI_OP_VERSION = 5,
183
184	/* HTT "operations" interface version, 32 bit value. Supported from
185	 * FW API 5 and above.
186	 */
187	ATH10K_FW_IE_HTT_OP_VERSION = 6,
188
189	/* Code swap image for firmware binary */
190	ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
191};
192
193enum ath10k_fw_wmi_op_version {
194	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
195
196	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
197	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
198	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
199	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
200	ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
201	ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
202
203	/* keep last */
204	ATH10K_FW_WMI_OP_VERSION_MAX,
205};
206
207enum ath10k_fw_htt_op_version {
208	ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
209
210	ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
211
212	/* also used in 10.2 and 10.2.4 branches */
213	ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
214
215	ATH10K_FW_HTT_OP_VERSION_TLV = 3,
216
217	ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
218
219	/* keep last */
220	ATH10K_FW_HTT_OP_VERSION_MAX,
221};
222
223enum ath10k_bd_ie_type {
224	/* contains sub IEs of enum ath10k_bd_ie_board_type */
225	ATH10K_BD_IE_BOARD = 0,
226	ATH10K_BD_IE_BOARD_EXT = 1,
227};
228
229enum ath10k_bd_ie_board_type {
230	ATH10K_BD_IE_BOARD_NAME = 0,
231	ATH10K_BD_IE_BOARD_DATA = 1,
232};
233
234enum ath10k_hw_rev {
235	ATH10K_HW_QCA988X,
236	ATH10K_HW_QCA6174,
237	ATH10K_HW_QCA99X0,
238	ATH10K_HW_QCA9888,
239	ATH10K_HW_QCA9984,
240	ATH10K_HW_QCA9377,
241	ATH10K_HW_QCA4019,
242	ATH10K_HW_QCA9887,
243	ATH10K_HW_WCN3990,
244};
245
246struct ath10k_hw_regs {
247	u32 rtc_soc_base_address;
248	u32 rtc_wmac_base_address;
249	u32 soc_core_base_address;
250	u32 wlan_mac_base_address;
251	u32 ce_wrapper_base_address;
252	u32 ce0_base_address;
253	u32 ce1_base_address;
254	u32 ce2_base_address;
255	u32 ce3_base_address;
256	u32 ce4_base_address;
257	u32 ce5_base_address;
258	u32 ce6_base_address;
259	u32 ce7_base_address;
260	u32 ce8_base_address;
261	u32 ce9_base_address;
262	u32 ce10_base_address;
263	u32 ce11_base_address;
264	u32 soc_reset_control_si0_rst_mask;
265	u32 soc_reset_control_ce_rst_mask;
266	u32 soc_chip_id_address;
267	u32 scratch_3_address;
268	u32 fw_indicator_address;
269	u32 pcie_local_base_address;
270	u32 ce_wrap_intr_sum_host_msi_lsb;
271	u32 ce_wrap_intr_sum_host_msi_mask;
272	u32 pcie_intr_fw_mask;
273	u32 pcie_intr_ce_mask_all;
274	u32 pcie_intr_clr_address;
275	u32 cpu_pll_init_address;
276	u32 cpu_speed_address;
277	u32 core_clk_div_address;
278};
279
280extern const struct ath10k_hw_regs qca988x_regs;
281extern const struct ath10k_hw_regs qca6174_regs;
282extern const struct ath10k_hw_regs qca99x0_regs;
283extern const struct ath10k_hw_regs qca4019_regs;
284extern const struct ath10k_hw_regs wcn3990_regs;
285
286struct ath10k_hw_ce_regs_addr_map {
287	u32 msb;
288	u32 lsb;
289	u32 mask;
290};
291
292struct ath10k_hw_ce_ctrl1 {
293	u32 addr;
294	u32 hw_mask;
295	u32 sw_mask;
296	u32 hw_wr_mask;
297	u32 sw_wr_mask;
298	u32 reset_mask;
299	u32 reset;
300	struct ath10k_hw_ce_regs_addr_map *src_ring;
301	struct ath10k_hw_ce_regs_addr_map *dst_ring;
302	struct ath10k_hw_ce_regs_addr_map *dmax; };
303
304struct ath10k_hw_ce_cmd_halt {
305	u32 status_reset;
306	u32 msb;
307	u32 mask;
308	struct ath10k_hw_ce_regs_addr_map *status; };
309
310struct ath10k_hw_ce_host_ie {
311	u32 copy_complete_reset;
312	struct ath10k_hw_ce_regs_addr_map *copy_complete; };
313
314struct ath10k_hw_ce_host_wm_regs {
315	u32 dstr_lmask;
316	u32 dstr_hmask;
317	u32 srcr_lmask;
318	u32 srcr_hmask;
319	u32 cc_mask;
320	u32 wm_mask;
321	u32 addr;
322};
323
324struct ath10k_hw_ce_misc_regs {
325	u32 axi_err;
326	u32 dstr_add_err;
327	u32 srcr_len_err;
328	u32 dstr_mlen_vio;
329	u32 dstr_overflow;
330	u32 srcr_overflow;
331	u32 err_mask;
332	u32 addr;
333};
334
335struct ath10k_hw_ce_dst_src_wm_regs {
336	u32 addr;
337	u32 low_rst;
338	u32 high_rst;
339	struct ath10k_hw_ce_regs_addr_map *wm_low;
340	struct ath10k_hw_ce_regs_addr_map *wm_high; };
341
342struct ath10k_hw_ce_ctrl1_upd {
343	u32 shift;
344	u32 mask;
345	u32 enable;
346};
347
348struct ath10k_hw_ce_regs {
349	u32 sr_base_addr_lo;
350	u32 sr_base_addr_hi;
351	u32 sr_size_addr;
352	u32 dr_base_addr_lo;
353	u32 dr_base_addr_hi;
354	u32 dr_size_addr;
355	u32 ce_cmd_addr;
356	u32 misc_ie_addr;
357	u32 sr_wr_index_addr;
358	u32 dst_wr_index_addr;
359	u32 current_srri_addr;
360	u32 current_drri_addr;
361	u32 ddr_addr_for_rri_low;
362	u32 ddr_addr_for_rri_high;
363	u32 ce_rri_low;
364	u32 ce_rri_high;
365	u32 host_ie_addr;
366	struct ath10k_hw_ce_host_wm_regs *wm_regs;
367	struct ath10k_hw_ce_misc_regs *misc_regs;
368	struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
369	struct ath10k_hw_ce_cmd_halt *cmd_halt;
370	struct ath10k_hw_ce_host_ie *host_ie;
371	struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
372	struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
373	struct ath10k_hw_ce_ctrl1_upd *upd;
374};
375
376struct ath10k_hw_values {
377	u32 rtc_state_val_on;
378	u8 ce_count;
379	u8 msi_assign_ce_max;
380	u8 num_target_ce_config_wlan;
381	u16 ce_desc_meta_data_mask;
382	u8 ce_desc_meta_data_lsb;
383	u32 rfkill_pin;
384	u32 rfkill_cfg;
385	bool rfkill_on_level;
386};
387
388extern const struct ath10k_hw_values qca988x_values;
389extern const struct ath10k_hw_values qca6174_values;
390extern const struct ath10k_hw_values qca99x0_values;
391extern const struct ath10k_hw_values qca9888_values;
392extern const struct ath10k_hw_values qca4019_values;
393extern const struct ath10k_hw_values wcn3990_values;
394extern const struct ath10k_hw_ce_regs wcn3990_ce_regs;
395extern const struct ath10k_hw_ce_regs qcax_ce_regs;
396
397void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
398				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
399
400int ath10k_hw_diag_fast_download(struct ath10k *ar,
401				 u32 address,
402				 const void *buffer,
403				 u32 length);
404
405#define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
406#define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
407#define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
408#define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
409#define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
410#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
411#define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
412#define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
413#define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
414
415/* Known peculiarities:
416 *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
417 *  - raw have FCS, nwifi doesn't
418 *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
419 *    param, llc/snap) are aligned to 4byte boundaries each
420 */
421enum ath10k_hw_txrx_mode {
422	ATH10K_HW_TXRX_RAW = 0,
423
424	/* Native Wifi decap mode is used to align IP frames to 4-byte
425	 * boundaries and avoid a very expensive re-alignment in mac80211.
426	 */
427	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
428	ATH10K_HW_TXRX_ETHERNET = 2,
429
430	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
431	ATH10K_HW_TXRX_MGMT = 3,
432};
433
434enum ath10k_mcast2ucast_mode {
435	ATH10K_MCAST2UCAST_DISABLED = 0,
436	ATH10K_MCAST2UCAST_ENABLED = 1,
437};
438
439enum ath10k_hw_rate_ofdm {
440	ATH10K_HW_RATE_OFDM_48M = 0,
441	ATH10K_HW_RATE_OFDM_24M,
442	ATH10K_HW_RATE_OFDM_12M,
443	ATH10K_HW_RATE_OFDM_6M,
444	ATH10K_HW_RATE_OFDM_54M,
445	ATH10K_HW_RATE_OFDM_36M,
446	ATH10K_HW_RATE_OFDM_18M,
447	ATH10K_HW_RATE_OFDM_9M,
448};
449
450enum ath10k_hw_rate_cck {
451	ATH10K_HW_RATE_CCK_LP_11M = 0,
452	ATH10K_HW_RATE_CCK_LP_5_5M,
453	ATH10K_HW_RATE_CCK_LP_2M,
454	ATH10K_HW_RATE_CCK_LP_1M,
455	ATH10K_HW_RATE_CCK_SP_11M,
456	ATH10K_HW_RATE_CCK_SP_5_5M,
457	ATH10K_HW_RATE_CCK_SP_2M,
458};
459
460enum ath10k_hw_rate_rev2_cck {
461	ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
462	ATH10K_HW_RATE_REV2_CCK_LP_2M,
463	ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
464	ATH10K_HW_RATE_REV2_CCK_LP_11M,
465	ATH10K_HW_RATE_REV2_CCK_SP_2M,
466	ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
467	ATH10K_HW_RATE_REV2_CCK_SP_11M,
468};
469
470enum ath10k_hw_cc_wraparound_type {
471	ATH10K_HW_CC_WRAP_DISABLED = 0,
472
473	/* This type is when the HW chip has a quirky Cycle Counter
474	 * wraparound which resets to 0x7fffffff instead of 0. All
475	 * other CC related counters (e.g. Rx Clear Count) are divided
476	 * by 2 so they never wraparound themselves.
477	 */
478	ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,
479
480	/* Each hw counter wrapsaround independently. When the
481	 * counter overflows the repestive counter is right shifted
482	 * by 1, i.e reset to 0x7fffffff, and other counters will be
483	 * running unaffected. In this type of wraparound, it should
484	 * be possible to report accurate Rx busy time unlike the
485	 * first type.
486	 */
487	ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
488};
489
490enum ath10k_hw_refclk_speed {
491	ATH10K_HW_REFCLK_UNKNOWN = -1,
492	ATH10K_HW_REFCLK_48_MHZ = 0,
493	ATH10K_HW_REFCLK_19_2_MHZ = 1,
494	ATH10K_HW_REFCLK_24_MHZ = 2,
495	ATH10K_HW_REFCLK_26_MHZ = 3,
496	ATH10K_HW_REFCLK_37_4_MHZ = 4,
497	ATH10K_HW_REFCLK_38_4_MHZ = 5,
498	ATH10K_HW_REFCLK_40_MHZ = 6,
499	ATH10K_HW_REFCLK_52_MHZ = 7,
500
501	/* must be the last one */
502	ATH10K_HW_REFCLK_COUNT,
503};
504
505struct ath10k_hw_clk_params {
506	u32 refclk;
507	u32 div;
508	u32 rnfrac;
509	u32 settle_time;
510	u32 refdiv;
511	u32 outdiv;
512};
513
514struct htt_rx_desc_ops;
515
516struct ath10k_hw_params {
517	u32 id;
518	u16 dev_id;
519	enum ath10k_bus bus;
520	const char *name;
521	u32 patch_load_addr;
522	int uart_pin;
523	u32 otp_exe_param;
524
525	/* Type of hw cycle counter wraparound logic, for more info
526	 * refer enum ath10k_hw_cc_wraparound_type.
527	 */
528	enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
529
530	/* Some of chip expects fragment descriptor to be continuous
531	 * memory for any TX operation. Set continuous_frag_desc flag
532	 * for the hardware which have such requirement.
533	 */
534	bool continuous_frag_desc;
535
536	/* CCK hardware rate table mapping for the newer chipsets
537	 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
538	 * are in a proper order with respect to the rate/preamble
539	 */
540	bool cck_rate_map_rev2;
541
542	u32 channel_counters_freq_hz;
543
544	/* Mgmt tx descriptors threshold for limiting probe response
545	 * frames.
546	 */
547	u32 max_probe_resp_desc_thres;
548
549	u32 tx_chain_mask;
550	u32 rx_chain_mask;
551	u32 max_spatial_stream;
552	u32 cal_data_len;
553
554	struct ath10k_hw_params_fw {
555		const char *dir;
556		const char *board;
557		size_t board_size;
558		const char *eboard;
559		size_t ext_board_size;
560		size_t board_ext_size;
561	} fw;
562
563	/* qca99x0 family chips deliver broadcast/multicast management
564	 * frames encrypted and expect software do decryption.
565	 */
566	bool sw_decrypt_mcast_mgmt;
567
568	/* Rx descriptor abstraction */
569	const struct ath10k_htt_rx_desc_ops *rx_desc_ops;
570
571	const struct ath10k_hw_ops *hw_ops;
572
573	/* Number of bytes used for alignment in rx_hdr_status of rx desc. */
574	int decap_align_bytes;
575
576	/* hw specific clock control parameters */
577	const struct ath10k_hw_clk_params *hw_clk;
578	int target_cpu_freq;
579
580	/* Number of bytes to be discarded for each FFT sample */
581	int spectral_bin_discard;
582
583	/* The board may have a restricted NSS for 160 or 80+80 vs what it
584	 * can do for 80Mhz.
585	 */
586	int vht160_mcs_rx_highest;
587	int vht160_mcs_tx_highest;
588
589	/* Number of ciphers supported (i.e First N) in cipher_suites array */
590	int n_cipher_suites;
591
592	u32 num_peers;
593	u32 ast_skid_limit;
594	u32 num_wds_entries;
595
596	/* Targets supporting physical addressing capability above 32-bits */
597	bool target_64bit;
598
599	/* Target rx ring fill level */
600	u32 rx_ring_fill_level;
601
602	/* target supporting shadow register for ce write */
603	bool shadow_reg_support;
604
605	/* target supporting retention restore on ddr */
606	bool rri_on_ddr;
607
608	/* Number of bytes to be the offset for each FFT sample */
609	int spectral_bin_offset;
610
611	/* targets which require hw filter reset during boot up,
612	 * to avoid it sending spurious acks.
613	 */
614	bool hw_filter_reset_required;
615
616	/* target supporting fw download via diag ce */
617	bool fw_diag_ce_download;
618
619	/* target supporting fw download via large size BMI */
620	bool bmi_large_size_download;
621
622	/* need to set uart pin if disable uart print, workaround for a
623	 * firmware bug
624	 */
625	bool uart_pin_workaround;
626
627	/* Workaround for the credit size calculation */
628	bool credit_size_workaround;
629
630	/* tx stats support over pktlog */
631	bool tx_stats_over_pktlog;
632
633	/* provides bitrates for sta_statistics using WMI_TLV_PEER_STATS_INFO_EVENTID */
634	bool supports_peer_stats_info;
635
636	bool dynamic_sar_support;
637
638	bool hw_restart_disconnect;
639
640	bool use_fw_tx_credits;
641
642	bool delay_unmap_buffer;
643
644	/* The hardware support multicast frame registrations */
645	bool mcast_frame_registration;
646};
647
648struct htt_resp;
649struct htt_data_tx_completion_ext;
650struct htt_rx_ring_rx_desc_offsets;
651
652/* Defines needed for Rx descriptor abstraction */
653struct ath10k_hw_ops {
654	void (*set_coverage_class)(struct ath10k *ar, s16 value);
655	int (*enable_pll_clk)(struct ath10k *ar);
656	int (*tx_data_rssi_pad_bytes)(struct htt_resp *htt);
657	int (*is_rssi_enable)(struct htt_resp *resp);
658};
659
660extern const struct ath10k_hw_ops qca988x_ops;
661extern const struct ath10k_hw_ops qca99x0_ops;
662extern const struct ath10k_hw_ops qca6174_ops;
663extern const struct ath10k_hw_ops qca6174_sdio_ops;
664extern const struct ath10k_hw_ops wcn3990_ops;
665
666extern const struct ath10k_hw_clk_params qca6174_clk[];
667
668static inline int
669ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw,
670				  struct htt_resp *htt)
671{
672	if (hw->hw_ops->tx_data_rssi_pad_bytes)
673		return hw->hw_ops->tx_data_rssi_pad_bytes(htt);
674	return 0;
675}
676
677static inline int
678ath10k_is_rssi_enable(struct ath10k_hw_params *hw,
679		      struct htt_resp *resp)
680{
681	if (hw->hw_ops->is_rssi_enable)
682		return hw->hw_ops->is_rssi_enable(resp);
683	return 0;
684}
685
686/* Target specific defines for MAIN firmware */
687#define TARGET_NUM_VDEVS			8
688#define TARGET_NUM_PEER_AST			2
689#define TARGET_NUM_WDS_ENTRIES			32
690#define TARGET_DMA_BURST_SIZE			0
691#define TARGET_MAC_AGGR_DELIM			0
692#define TARGET_AST_SKID_LIMIT			16
693#define TARGET_NUM_STATIONS			16
694#define TARGET_NUM_PEERS			((TARGET_NUM_STATIONS) + \
695						 (TARGET_NUM_VDEVS))
696#define TARGET_NUM_OFFLOAD_PEERS		0
697#define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
698#define TARGET_NUM_PEER_KEYS			2
699#define TARGET_NUM_TIDS				((TARGET_NUM_PEERS) * 2)
700#define TARGET_TX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
701#define TARGET_RX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
702#define TARGET_RX_TIMEOUT_LO_PRI		100
703#define TARGET_RX_TIMEOUT_HI_PRI		40
704
705#define TARGET_SCAN_MAX_PENDING_REQS		4
706#define TARGET_BMISS_OFFLOAD_MAX_VDEV		3
707#define TARGET_ROAM_OFFLOAD_MAX_VDEV		3
708#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
709#define TARGET_GTK_OFFLOAD_MAX_VDEV		3
710#define TARGET_NUM_MCAST_GROUPS			0
711#define TARGET_NUM_MCAST_TABLE_ELEMS		0
712#define TARGET_MCAST2UCAST_MODE			ATH10K_MCAST2UCAST_DISABLED
713#define TARGET_TX_DBG_LOG_SIZE			1024
714#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
715#define TARGET_VOW_CONFIG			0
716#define TARGET_NUM_MSDU_DESC			(1024 + 400)
717#define TARGET_MAX_FRAG_ENTRIES			0
718
719/* Target specific defines for 10.X firmware */
720#define TARGET_10X_NUM_VDEVS			16
721#define TARGET_10X_NUM_PEER_AST			2
722#define TARGET_10X_NUM_WDS_ENTRIES		32
723#define TARGET_10X_DMA_BURST_SIZE		0
724#define TARGET_10X_MAC_AGGR_DELIM		0
725#define TARGET_10X_AST_SKID_LIMIT		128
726#define TARGET_10X_NUM_STATIONS			128
727#define TARGET_10X_TX_STATS_NUM_STATIONS	118
728#define TARGET_10X_NUM_PEERS			((TARGET_10X_NUM_STATIONS) + \
729						 (TARGET_10X_NUM_VDEVS))
730#define TARGET_10X_TX_STATS_NUM_PEERS		((TARGET_10X_TX_STATS_NUM_STATIONS) + \
731						 (TARGET_10X_NUM_VDEVS))
732#define TARGET_10X_NUM_OFFLOAD_PEERS		0
733#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS	0
734#define TARGET_10X_NUM_PEER_KEYS		2
735#define TARGET_10X_NUM_TIDS_MAX			256
736#define TARGET_10X_NUM_TIDS			min((TARGET_10X_NUM_TIDS_MAX), \
737						    (TARGET_10X_NUM_PEERS) * 2)
738#define TARGET_10X_TX_STATS_NUM_TIDS		min((TARGET_10X_NUM_TIDS_MAX), \
739						    (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
740#define TARGET_10X_TX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
741#define TARGET_10X_RX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
742#define TARGET_10X_RX_TIMEOUT_LO_PRI		100
743#define TARGET_10X_RX_TIMEOUT_HI_PRI		40
744#define TARGET_10X_SCAN_MAX_PENDING_REQS	4
745#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV	2
746#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV	2
747#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES	8
748#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV		3
749#define TARGET_10X_NUM_MCAST_GROUPS		0
750#define TARGET_10X_NUM_MCAST_TABLE_ELEMS	0
751#define TARGET_10X_MCAST2UCAST_MODE		ATH10K_MCAST2UCAST_DISABLED
752#define TARGET_10X_TX_DBG_LOG_SIZE		1024
753#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
754#define TARGET_10X_VOW_CONFIG			0
755#define TARGET_10X_NUM_MSDU_DESC		(1024 + 400)
756#define TARGET_10X_MAX_FRAG_ENTRIES		0
757
758/* 10.2 parameters */
759#define TARGET_10_2_DMA_BURST_SIZE		0
760
761/* Target specific defines for WMI-TLV firmware */
762#define TARGET_TLV_NUM_VDEVS			4
763#define TARGET_TLV_NUM_STATIONS			32
764#define TARGET_TLV_NUM_PEERS			33
765#define TARGET_TLV_NUM_TDLS_VDEVS		1
766#define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
767#define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)
768#define TARGET_TLV_NUM_MSDU_DESC_HL		1024
769#define TARGET_TLV_NUM_WOW_PATTERNS		22
770#define TARGET_TLV_MGMT_NUM_MSDU_DESC		(50)
771
772/* Target specific defines for WMI-HL-1.0 firmware */
773#define TARGET_HL_TLV_NUM_PEERS			33
774#define TARGET_HL_TLV_AST_SKID_LIMIT		16
775#define TARGET_HL_TLV_NUM_WDS_ENTRIES		2
776
777/* Target specific defines for QCA9377 high latency firmware */
778#define TARGET_QCA9377_HL_NUM_PEERS		15
779
780/* Diagnostic Window */
781#define CE_DIAG_PIPE	7
782
783#define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
784
785/* Target specific defines for 10.4 firmware */
786#define TARGET_10_4_NUM_VDEVS			16
787#define TARGET_10_4_NUM_STATIONS		32
788#define TARGET_10_4_NUM_PEERS			((TARGET_10_4_NUM_STATIONS) + \
789						 (TARGET_10_4_NUM_VDEVS))
790#define TARGET_10_4_ACTIVE_PEERS		0
791
792#define TARGET_10_4_NUM_QCACHE_PEERS_MAX	512
793#define TARGET_10_4_QCACHE_ACTIVE_PEERS		50
794#define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC	35
795#define TARGET_10_4_NUM_OFFLOAD_PEERS		0
796#define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS	0
797#define TARGET_10_4_NUM_PEER_KEYS		2
798#define TARGET_10_4_TGT_NUM_TIDS		((TARGET_10_4_NUM_PEERS) * 2)
799#define TARGET_10_4_NUM_MSDU_DESC		(1024 + 400)
800#define TARGET_10_4_NUM_MSDU_DESC_PFC		2500
801#define TARGET_10_4_AST_SKID_LIMIT		32
802
803/* 100 ms for video, best-effort, and background */
804#define TARGET_10_4_RX_TIMEOUT_LO_PRI		100
805
806/* 40 ms for voice */
807#define TARGET_10_4_RX_TIMEOUT_HI_PRI		40
808
809#define TARGET_10_4_RX_DECAP_MODE		ATH10K_HW_TXRX_NATIVE_WIFI
810#define TARGET_10_4_SCAN_MAX_REQS		4
811#define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV	3
812#define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV	3
813#define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES   8
814
815/* Note: mcast to ucast is disabled by default */
816#define TARGET_10_4_NUM_MCAST_GROUPS		0
817#define TARGET_10_4_NUM_MCAST_TABLE_ELEMS	0
818#define TARGET_10_4_MCAST2UCAST_MODE		0
819
820#define TARGET_10_4_TX_DBG_LOG_SIZE		1024
821#define TARGET_10_4_NUM_WDS_ENTRIES		32
822#define TARGET_10_4_DMA_BURST_SIZE		1
823#define TARGET_10_4_MAC_AGGR_DELIM		0
824#define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
825#define TARGET_10_4_VOW_CONFIG			0
826#define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV	3
827#define TARGET_10_4_11AC_TX_MAX_FRAGS		2
828#define TARGET_10_4_MAX_PEER_EXT_STATS		16
829#define TARGET_10_4_SMART_ANT_CAP		0
830#define TARGET_10_4_BK_MIN_FREE			0
831#define TARGET_10_4_BE_MIN_FREE			0
832#define TARGET_10_4_VI_MIN_FREE			0
833#define TARGET_10_4_VO_MIN_FREE			0
834#define TARGET_10_4_RX_BATCH_MODE		1
835#define TARGET_10_4_THERMAL_THROTTLING_CONFIG	0
836#define TARGET_10_4_ATF_CONFIG			0
837#define TARGET_10_4_IPHDR_PAD_CONFIG		1
838#define TARGET_10_4_QWRAP_CONFIG		0
839
840/* TDLS config */
841#define TARGET_10_4_NUM_TDLS_VDEVS		1
842#define TARGET_10_4_NUM_TDLS_BUFFER_STA		1
843#define TARGET_10_4_NUM_TDLS_SLEEP_STA		1
844
845/* Maximum number of Copy Engine's supported */
846#define CE_COUNT_MAX 12
847
848/* Number of Copy Engines supported */
849#define CE_COUNT ar->hw_values->ce_count
850
851/*
852 * Granted MSIs are assigned as follows:
853 * Firmware uses the first
854 * Remaining MSIs, if any, are used by Copy Engines
855 * This mapping is known to both Target firmware and Host software.
856 * It may be changed as long as Host and Target are kept in sync.
857 */
858/* MSI for firmware (errors, etc.) */
859#define MSI_ASSIGN_FW		0
860
861/* MSIs for Copy Engines */
862#define MSI_ASSIGN_CE_INITIAL	1
863#define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
864
865/* as of IP3.7.1 */
866#define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
867
868#define RTC_STATE_V_LSB				0
869#define RTC_STATE_V_MASK			0x00000007
870#define RTC_STATE_ADDRESS			0x0000
871#define PCIE_SOC_WAKE_V_MASK			0x00000001
872#define PCIE_SOC_WAKE_ADDRESS			0x0004
873#define PCIE_SOC_WAKE_RESET			0x00000000
874#define SOC_GLOBAL_RESET_ADDRESS		0x0008
875
876#define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
877#define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
878#define MAC_COEX_BASE_ADDRESS			0x00006000
879#define BT_COEX_BASE_ADDRESS			0x00007000
880#define SOC_PCIE_BASE_ADDRESS			0x00008000
881#define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
882#define WLAN_UART_BASE_ADDRESS			0x0000c000
883#define WLAN_SI_BASE_ADDRESS			0x00010000
884#define WLAN_GPIO_BASE_ADDRESS			0x00014000
885#define WLAN_ANALOG_INTF_BASE_ADDRESS		0x0001c000
886#define WLAN_MAC_BASE_ADDRESS			ar->regs->wlan_mac_base_address
887#define EFUSE_BASE_ADDRESS			0x00030000
888#define FPGA_REG_BASE_ADDRESS			0x00039000
889#define WLAN_UART2_BASE_ADDRESS			0x00054c00
890#define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
891#define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
892#define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
893#define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
894#define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
895#define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
896#define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
897#define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
898#define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
899#define DBI_BASE_ADDRESS			0x00060000
900#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000
901#define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
902
903#define SOC_RESET_CONTROL_ADDRESS		0x00000000
904#define SOC_RESET_CONTROL_OFFSET		0x00000000
905#define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
906#define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
907#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK	0x00000040
908#define SOC_CPU_CLOCK_OFFSET			0x00000020
909#define SOC_CPU_CLOCK_STANDARD_LSB		0
910#define SOC_CPU_CLOCK_STANDARD_MASK		0x00000003
911#define SOC_CLOCK_CONTROL_OFFSET		0x00000028
912#define SOC_CLOCK_CONTROL_SI0_CLK_MASK		0x00000001
913#define SOC_SYSTEM_SLEEP_OFFSET			0x000000c4
914#define SOC_LPO_CAL_OFFSET			0x000000e0
915#define SOC_LPO_CAL_ENABLE_LSB			20
916#define SOC_LPO_CAL_ENABLE_MASK			0x00100000
917#define SOC_LF_TIMER_CONTROL0_ADDRESS		0x00000050
918#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK	0x00000004
919
920#define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
921#define SOC_CHIP_ID_REV_LSB			8
922#define SOC_CHIP_ID_REV_MASK			0x00000f00
923
924#define WLAN_RESET_CONTROL_COLD_RST_MASK	0x00000008
925#define WLAN_RESET_CONTROL_WARM_RST_MASK	0x00000004
926#define WLAN_SYSTEM_SLEEP_DISABLE_LSB		0
927#define WLAN_SYSTEM_SLEEP_DISABLE_MASK		0x00000001
928
929#define WLAN_GPIO_PIN0_ADDRESS			0x00000028
930#define WLAN_GPIO_PIN0_CONFIG_LSB		11
931#define WLAN_GPIO_PIN0_CONFIG_MASK		0x00007800
932#define WLAN_GPIO_PIN0_PAD_PULL_LSB		5
933#define WLAN_GPIO_PIN0_PAD_PULL_MASK		0x00000060
934#define WLAN_GPIO_PIN1_ADDRESS			0x0000002c
935#define WLAN_GPIO_PIN1_CONFIG_MASK		0x00007800
936#define WLAN_GPIO_PIN10_ADDRESS			0x00000050
937#define WLAN_GPIO_PIN11_ADDRESS			0x00000054
938#define WLAN_GPIO_PIN12_ADDRESS			0x00000058
939#define WLAN_GPIO_PIN13_ADDRESS			0x0000005c
940
941#define CLOCK_GPIO_OFFSET			0xffffffff
942#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB		0
943#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK		0
944
945#define SI_CONFIG_OFFSET			0x00000000
946#define SI_CONFIG_ERR_INT_LSB			19
947#define SI_CONFIG_ERR_INT_MASK			0x00080000
948#define SI_CONFIG_BIDIR_OD_DATA_LSB		18
949#define SI_CONFIG_BIDIR_OD_DATA_MASK		0x00040000
950#define SI_CONFIG_I2C_LSB			16
951#define SI_CONFIG_I2C_MASK			0x00010000
952#define SI_CONFIG_POS_SAMPLE_LSB		7
953#define SI_CONFIG_POS_SAMPLE_MASK		0x00000080
954#define SI_CONFIG_INACTIVE_DATA_LSB		5
955#define SI_CONFIG_INACTIVE_DATA_MASK		0x00000020
956#define SI_CONFIG_INACTIVE_CLK_LSB		4
957#define SI_CONFIG_INACTIVE_CLK_MASK		0x00000010
958#define SI_CONFIG_DIVIDER_LSB			0
959#define SI_CONFIG_DIVIDER_MASK			0x0000000f
960#define SI_CS_OFFSET				0x00000004
961#define SI_CS_DONE_ERR_LSB			10
962#define SI_CS_DONE_ERR_MASK			0x00000400
963#define SI_CS_DONE_INT_LSB			9
964#define SI_CS_DONE_INT_MASK			0x00000200
965#define SI_CS_START_LSB				8
966#define SI_CS_START_MASK			0x00000100
967#define SI_CS_RX_CNT_LSB			4
968#define SI_CS_RX_CNT_MASK			0x000000f0
969#define SI_CS_TX_CNT_LSB			0
970#define SI_CS_TX_CNT_MASK			0x0000000f
971
972#define SI_TX_DATA0_OFFSET			0x00000008
973#define SI_TX_DATA1_OFFSET			0x0000000c
974#define SI_RX_DATA0_OFFSET			0x00000010
975#define SI_RX_DATA1_OFFSET			0x00000014
976
977#define CORE_CTRL_CPU_INTR_MASK			0x00002000
978#define CORE_CTRL_PCIE_REG_31_MASK		0x00000800
979#define CORE_CTRL_ADDRESS			0x0000
980#define PCIE_INTR_ENABLE_ADDRESS		0x0008
981#define PCIE_INTR_CAUSE_ADDRESS			0x000c
982#define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
983#define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
984#define CPU_INTR_ADDRESS			0x0010
985#define FW_RAM_CONFIG_ADDRESS			0x0018
986
987#define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
988
989/* Firmware indications to the Host via SCRATCH_3 register. */
990#define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
991#define FW_IND_EVENT_PENDING			1
992#define FW_IND_INITIALIZED			2
993#define FW_IND_HOST_READY			0x80000000
994
995/* HOST_REG interrupt from firmware */
996#define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
997#define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all
998
999#define DRAM_BASE_ADDRESS			0x00400000
1000
1001#define PCIE_BAR_REG_ADDRESS			0x40030
1002
1003#define MISSING 0
1004
1005#define SYSTEM_SLEEP_OFFSET			SOC_SYSTEM_SLEEP_OFFSET
1006#define WLAN_SYSTEM_SLEEP_OFFSET		SOC_SYSTEM_SLEEP_OFFSET
1007#define WLAN_RESET_CONTROL_OFFSET		SOC_RESET_CONTROL_OFFSET
1008#define CLOCK_CONTROL_OFFSET			SOC_CLOCK_CONTROL_OFFSET
1009#define CLOCK_CONTROL_SI0_CLK_MASK		SOC_CLOCK_CONTROL_SI0_CLK_MASK
1010#define RESET_CONTROL_MBOX_RST_MASK		MISSING
1011#define RESET_CONTROL_SI0_RST_MASK		SOC_RESET_CONTROL_SI0_RST_MASK
1012#define GPIO_BASE_ADDRESS			WLAN_GPIO_BASE_ADDRESS
1013#define GPIO_PIN0_OFFSET			WLAN_GPIO_PIN0_ADDRESS
1014#define GPIO_PIN1_OFFSET			WLAN_GPIO_PIN1_ADDRESS
1015#define GPIO_PIN0_CONFIG_LSB			WLAN_GPIO_PIN0_CONFIG_LSB
1016#define GPIO_PIN0_CONFIG_MASK			WLAN_GPIO_PIN0_CONFIG_MASK
1017#define GPIO_PIN0_PAD_PULL_LSB			WLAN_GPIO_PIN0_PAD_PULL_LSB
1018#define GPIO_PIN0_PAD_PULL_MASK			WLAN_GPIO_PIN0_PAD_PULL_MASK
1019#define GPIO_PIN1_CONFIG_MASK			WLAN_GPIO_PIN1_CONFIG_MASK
1020#define SI_BASE_ADDRESS				WLAN_SI_BASE_ADDRESS
1021#define SCRATCH_BASE_ADDRESS			SOC_CORE_BASE_ADDRESS
1022#define LOCAL_SCRATCH_OFFSET			0x18
1023#define CPU_CLOCK_OFFSET			SOC_CPU_CLOCK_OFFSET
1024#define LPO_CAL_OFFSET				SOC_LPO_CAL_OFFSET
1025#define GPIO_PIN10_OFFSET			WLAN_GPIO_PIN10_ADDRESS
1026#define GPIO_PIN11_OFFSET			WLAN_GPIO_PIN11_ADDRESS
1027#define GPIO_PIN12_OFFSET			WLAN_GPIO_PIN12_ADDRESS
1028#define GPIO_PIN13_OFFSET			WLAN_GPIO_PIN13_ADDRESS
1029#define CPU_CLOCK_STANDARD_LSB			SOC_CPU_CLOCK_STANDARD_LSB
1030#define CPU_CLOCK_STANDARD_MASK			SOC_CPU_CLOCK_STANDARD_MASK
1031#define LPO_CAL_ENABLE_LSB			SOC_LPO_CAL_ENABLE_LSB
1032#define LPO_CAL_ENABLE_MASK			SOC_LPO_CAL_ENABLE_MASK
1033#define ANALOG_INTF_BASE_ADDRESS		WLAN_ANALOG_INTF_BASE_ADDRESS
1034#define MBOX_BASE_ADDRESS			MISSING
1035#define INT_STATUS_ENABLE_ERROR_LSB		MISSING
1036#define INT_STATUS_ENABLE_ERROR_MASK		MISSING
1037#define INT_STATUS_ENABLE_CPU_LSB		MISSING
1038#define INT_STATUS_ENABLE_CPU_MASK		MISSING
1039#define INT_STATUS_ENABLE_COUNTER_LSB		MISSING
1040#define INT_STATUS_ENABLE_COUNTER_MASK		MISSING
1041#define INT_STATUS_ENABLE_MBOX_DATA_LSB		MISSING
1042#define INT_STATUS_ENABLE_MBOX_DATA_MASK	MISSING
1043#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB	MISSING
1044#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK	MISSING
1045#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB	MISSING
1046#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK	MISSING
1047#define COUNTER_INT_STATUS_ENABLE_BIT_LSB	MISSING
1048#define COUNTER_INT_STATUS_ENABLE_BIT_MASK	MISSING
1049#define INT_STATUS_ENABLE_ADDRESS		MISSING
1050#define CPU_INT_STATUS_ENABLE_BIT_LSB		MISSING
1051#define CPU_INT_STATUS_ENABLE_BIT_MASK		MISSING
1052#define HOST_INT_STATUS_ADDRESS			MISSING
1053#define CPU_INT_STATUS_ADDRESS			MISSING
1054#define ERROR_INT_STATUS_ADDRESS		MISSING
1055#define ERROR_INT_STATUS_WAKEUP_MASK		MISSING
1056#define ERROR_INT_STATUS_WAKEUP_LSB		MISSING
1057#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK	MISSING
1058#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB	MISSING
1059#define ERROR_INT_STATUS_TX_OVERFLOW_MASK	MISSING
1060#define ERROR_INT_STATUS_TX_OVERFLOW_LSB	MISSING
1061#define COUNT_DEC_ADDRESS			MISSING
1062#define HOST_INT_STATUS_CPU_MASK		MISSING
1063#define HOST_INT_STATUS_CPU_LSB			MISSING
1064#define HOST_INT_STATUS_ERROR_MASK		MISSING
1065#define HOST_INT_STATUS_ERROR_LSB		MISSING
1066#define HOST_INT_STATUS_COUNTER_MASK		MISSING
1067#define HOST_INT_STATUS_COUNTER_LSB		MISSING
1068#define RX_LOOKAHEAD_VALID_ADDRESS		MISSING
1069#define WINDOW_DATA_ADDRESS			MISSING
1070#define WINDOW_READ_ADDR_ADDRESS		MISSING
1071#define WINDOW_WRITE_ADDR_ADDRESS		MISSING
1072
1073#define QCA9887_1_0_I2C_SDA_GPIO_PIN		5
1074#define QCA9887_1_0_I2C_SDA_PIN_CONFIG		3
1075#define QCA9887_1_0_SI_CLK_GPIO_PIN		17
1076#define QCA9887_1_0_SI_CLK_PIN_CONFIG		3
1077#define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
1078
1079#define QCA9887_EEPROM_SELECT_READ		0xa10000a0
1080#define QCA9887_EEPROM_ADDR_HI_MASK		0x0000ff00
1081#define QCA9887_EEPROM_ADDR_HI_LSB		8
1082#define QCA9887_EEPROM_ADDR_LO_MASK		0x00ff0000
1083#define QCA9887_EEPROM_ADDR_LO_LSB		16
1084
1085#define MBOX_RESET_CONTROL_ADDRESS		0x00000000
1086#define MBOX_HOST_INT_STATUS_ADDRESS		0x00000800
1087#define MBOX_HOST_INT_STATUS_ERROR_LSB		7
1088#define MBOX_HOST_INT_STATUS_ERROR_MASK		0x00000080
1089#define MBOX_HOST_INT_STATUS_CPU_LSB		6
1090#define MBOX_HOST_INT_STATUS_CPU_MASK		0x00000040
1091#define MBOX_HOST_INT_STATUS_COUNTER_LSB	4
1092#define MBOX_HOST_INT_STATUS_COUNTER_MASK	0x00000010
1093#define MBOX_CPU_INT_STATUS_ADDRESS		0x00000801
1094#define MBOX_ERROR_INT_STATUS_ADDRESS		0x00000802
1095#define MBOX_ERROR_INT_STATUS_WAKEUP_LSB	2
1096#define MBOX_ERROR_INT_STATUS_WAKEUP_MASK	0x00000004
1097#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB	1
1098#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK	0x00000002
1099#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB	0
1100#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK	0x00000001
1101#define MBOX_COUNTER_INT_STATUS_ADDRESS		0x00000803
1102#define MBOX_COUNTER_INT_STATUS_COUNTER_LSB	0
1103#define MBOX_COUNTER_INT_STATUS_COUNTER_MASK	0x000000ff
1104#define MBOX_RX_LOOKAHEAD_VALID_ADDRESS		0x00000805
1105#define MBOX_INT_STATUS_ENABLE_ADDRESS		0x00000828
1106#define MBOX_INT_STATUS_ENABLE_ERROR_LSB	7
1107#define MBOX_INT_STATUS_ENABLE_ERROR_MASK	0x00000080
1108#define MBOX_INT_STATUS_ENABLE_CPU_LSB		6
1109#define MBOX_INT_STATUS_ENABLE_CPU_MASK		0x00000040
1110#define MBOX_INT_STATUS_ENABLE_INT_LSB		5
1111#define MBOX_INT_STATUS_ENABLE_INT_MASK		0x00000020
1112#define MBOX_INT_STATUS_ENABLE_COUNTER_LSB	4
1113#define MBOX_INT_STATUS_ENABLE_COUNTER_MASK	0x00000010
1114#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB	0
1115#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK	0x0000000f
1116#define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS	0x00000819
1117#define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB	0
1118#define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK	0x000000ff
1119#define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK 0x00000001
1120#define MBOX_ERROR_STATUS_ENABLE_ADDRESS	0x0000081a
1121#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB  1
1122#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1123#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB   0
1124#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK  0x00000001
1125#define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS	0x0000081b
1126#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB	0
1127#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK	0x000000ff
1128#define MBOX_COUNT_ADDRESS			0x00000820
1129#define MBOX_COUNT_DEC_ADDRESS			0x00000840
1130#define MBOX_WINDOW_DATA_ADDRESS		0x00000874
1131#define MBOX_WINDOW_WRITE_ADDR_ADDRESS		0x00000878
1132#define MBOX_WINDOW_READ_ADDR_ADDRESS		0x0000087c
1133#define MBOX_CPU_DBG_SEL_ADDRESS		0x00000883
1134#define MBOX_CPU_DBG_ADDRESS			0x00000884
1135#define MBOX_RTC_BASE_ADDRESS			0x00000000
1136#define MBOX_GPIO_BASE_ADDRESS			0x00005000
1137#define MBOX_MBOX_BASE_ADDRESS			0x00008000
1138
1139#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
1140
1141/* Register definitions for first generation ath10k cards. These cards include
1142 * a mac thich has a register allocation similar to ath9k and at least some
1143 * registers including the ones relevant for modifying the coverage class are
1144 * identical to the ath9k definitions.
1145 * These registers are usually managed by the ath10k firmware. However by
1146 * overriding them it is possible to support coverage class modifications.
1147 */
1148#define WAVE1_PCU_ACK_CTS_TIMEOUT		0x8014
1149#define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX		0x00003FFF
1150#define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK	0x00003FFF
1151#define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB	0
1152#define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK	0x3FFF0000
1153#define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB	16
1154
1155#define WAVE1_PCU_GBL_IFS_SLOT			0x1070
1156#define WAVE1_PCU_GBL_IFS_SLOT_MASK		0x0000FFFF
1157#define WAVE1_PCU_GBL_IFS_SLOT_MAX		0x0000FFFF
1158#define WAVE1_PCU_GBL_IFS_SLOT_LSB		0
1159#define WAVE1_PCU_GBL_IFS_SLOT_RESV0		0xFFFF0000
1160
1161#define WAVE1_PHYCLK				0x801C
1162#define WAVE1_PHYCLK_USEC_MASK			0x0000007F
1163#define WAVE1_PHYCLK_USEC_LSB			0
1164
1165/* qca6174 PLL offset/mask */
1166#define SOC_CORE_CLK_CTRL_OFFSET		0x00000114
1167#define SOC_CORE_CLK_CTRL_DIV_LSB		0
1168#define SOC_CORE_CLK_CTRL_DIV_MASK		0x00000007
1169
1170#define EFUSE_OFFSET				0x0000032c
1171#define EFUSE_XTAL_SEL_LSB			8
1172#define EFUSE_XTAL_SEL_MASK			0x00000700
1173
1174#define BB_PLL_CONFIG_OFFSET			0x000002f4
1175#define BB_PLL_CONFIG_FRAC_LSB			0
1176#define BB_PLL_CONFIG_FRAC_MASK			0x0003ffff
1177#define BB_PLL_CONFIG_OUTDIV_LSB		18
1178#define BB_PLL_CONFIG_OUTDIV_MASK		0x001c0000
1179
1180#define WLAN_PLL_SETTLE_OFFSET			0x0018
1181#define WLAN_PLL_SETTLE_TIME_LSB		0
1182#define WLAN_PLL_SETTLE_TIME_MASK		0x000007ff
1183
1184#define WLAN_PLL_CONTROL_OFFSET			0x0014
1185#define WLAN_PLL_CONTROL_DIV_LSB		0
1186#define WLAN_PLL_CONTROL_DIV_MASK		0x000003ff
1187#define WLAN_PLL_CONTROL_REFDIV_LSB		10
1188#define WLAN_PLL_CONTROL_REFDIV_MASK		0x00003c00
1189#define WLAN_PLL_CONTROL_BYPASS_LSB		16
1190#define WLAN_PLL_CONTROL_BYPASS_MASK		0x00010000
1191#define WLAN_PLL_CONTROL_NOPWD_LSB		18
1192#define WLAN_PLL_CONTROL_NOPWD_MASK		0x00040000
1193
1194#define RTC_SYNC_STATUS_OFFSET			0x0244
1195#define RTC_SYNC_STATUS_PLL_CHANGING_LSB	5
1196#define RTC_SYNC_STATUS_PLL_CHANGING_MASK	0x00000020
1197/* qca6174 PLL offset/mask end */
1198
1199/* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory
1200 * region is accessed. The memory region size is 1M.
1201 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0]
1202 * is 0xX.
1203 * The following MACROs are defined to get the 0xX and the size limit.
1204 */
1205#define CPU_ADDR_MSB_REGION_MASK	GENMASK(23, 20)
1206#define CPU_ADDR_MSB_REGION_VAL(X)	FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X)
1207#define REGION_ACCESS_SIZE_LIMIT	0x100000
1208#define REGION_ACCESS_SIZE_MASK		(REGION_ACCESS_SIZE_LIMIT - 1)
1209
1210#endif /* _HW_H_ */
1211