1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023-2024 Linaro Ltd. */
4
5#include <linux/array_size.h>
6#include <linux/bits.h>
7#include <linux/types.h>
8
9#include "../ipa_reg.h"
10#include "../ipa_version.h"
11
12static const u32 reg_flavor_0_fmask[] = {
13	[MAX_PIPES]					= GENMASK(7, 0),
14	[MAX_CONS_PIPES]				= GENMASK(15, 8),
15	[MAX_PROD_PIPES]				= GENMASK(23, 16),
16	[PROD_LOWEST]					= GENMASK(31, 24),
17};
18
19REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
20
21static const u32 reg_comp_cfg_fmask[] = {
22	[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS]		= BIT(0),
23	[GSI_SNOC_BYPASS_DIS]				= BIT(1),
24	[GEN_QMB_0_SNOC_BYPASS_DIS]			= BIT(2),
25	[GEN_QMB_1_SNOC_BYPASS_DIS]			= BIT(3),
26						/* Bit 4 reserved */
27	[IPA_QMB_SELECT_CONS_EN]			= BIT(5),
28	[IPA_QMB_SELECT_PROD_EN]			= BIT(6),
29	[GSI_MULTI_INORDER_RD_DIS]			= BIT(7),
30	[GSI_MULTI_INORDER_WR_DIS]			= BIT(8),
31	[GEN_QMB_0_MULTI_INORDER_RD_DIS]		= BIT(9),
32	[GEN_QMB_1_MULTI_INORDER_RD_DIS]		= BIT(10),
33	[GEN_QMB_0_MULTI_INORDER_WR_DIS]		= BIT(11),
34	[GEN_QMB_1_MULTI_INORDER_WR_DIS]		= BIT(12),
35	[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS]		= BIT(13),
36	[GSI_SNOC_CNOC_LOOP_PROT_DISABLE]		= BIT(14),
37	[GSI_MULTI_AXI_MASTERS_DIS]			= BIT(15),
38	[IPA_QMB_SELECT_GLOBAL_EN]			= BIT(16),
39	[FULL_FLUSH_WAIT_RS_CLOSURE_EN]			= BIT(17),
40						/* Bit 18 reserved */
41	[QMB_RAM_RD_CACHE_DISABLE]			= BIT(19),
42	[GENQMB_AOOOWR]					= BIT(20),
43	[IF_OUT_OF_BUF_STOP_RESET_MASK_EN]		= BIT(21),
44	[ATOMIC_FETCHER_ARB_LOCK_DIS]			= GENMASK(27, 22),
45						/* Bits 28-29 reserved */
46	[GEN_QMB_1_DYNAMIC_ASIZE]			= BIT(30),
47	[GEN_QMB_0_DYNAMIC_ASIZE]			= BIT(31),
48};
49
50REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
51
52static const u32 reg_clkon_cfg_fmask[] = {
53	[CLKON_RX]					= BIT(0),
54	[CLKON_PROC]					= BIT(1),
55	[TX_WRAPPER]					= BIT(2),
56	[CLKON_MISC]					= BIT(3),
57	[RAM_ARB]					= BIT(4),
58	[FTCH_HPS]					= BIT(5),
59	[FTCH_DPS]					= BIT(6),
60	[CLKON_HPS]					= BIT(7),
61	[CLKON_DPS]					= BIT(8),
62	[RX_HPS_CMDQS]					= BIT(9),
63	[HPS_DPS_CMDQS]					= BIT(10),
64	[DPS_TX_CMDQS]					= BIT(11),
65	[RSRC_MNGR]					= BIT(12),
66	[CTX_HANDLER]					= BIT(13),
67	[ACK_MNGR]					= BIT(14),
68	[D_DCPH]					= BIT(15),
69	[H_DCPH]					= BIT(16),
70						/* Bit 17 reserved */
71	[NTF_TX_CMDQS]					= BIT(18),
72	[CLKON_TX_0]					= BIT(19),
73	[CLKON_TX_1]					= BIT(20),
74	[CLKON_FNR]					= BIT(21),
75	[QSB2AXI_CMDQ_L]				= BIT(22),
76	[AGGR_WRAPPER]					= BIT(23),
77	[RAM_SLAVEWAY]					= BIT(24),
78	[CLKON_QMB]					= BIT(25),
79	[WEIGHT_ARB]					= BIT(26),
80	[GSI_IF]					= BIT(27),
81	[CLKON_GLOBAL]					= BIT(28),
82	[GLOBAL_2X_CLK]					= BIT(29),
83	[DPL_FIFO]					= BIT(30),
84	[DRBIP]						= BIT(31),
85};
86
87REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
88
89static const u32 reg_route_fmask[] = {
90	[ROUTE_DEF_PIPE]				= GENMASK(7, 0),
91	[ROUTE_FRAG_DEF_PIPE]				= GENMASK(15, 8),
92	[ROUTE_DEF_HDR_OFST]				= GENMASK(25, 16),
93	[ROUTE_DEF_HDR_TABLE]				= BIT(26),
94	[ROUTE_DEF_RETAIN_HDR]				= BIT(27),
95	[ROUTE_DIS]					= BIT(28),
96						/* Bits 29-31 reserved */
97};
98
99REG_FIELDS(ROUTE, route, 0x00000038);
100
101static const u32 reg_shared_mem_size_fmask[] = {
102	[MEM_SIZE]					= GENMASK(15, 0),
103	[MEM_BADDR]					= GENMASK(31, 16),
104};
105
106REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
107
108static const u32 reg_qsb_max_writes_fmask[] = {
109	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
110	[GEN_QMB_1_MAX_WRITES]				= GENMASK(7, 4),
111						/* Bits 8-31 reserved */
112};
113
114REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000054);
115
116static const u32 reg_qsb_max_reads_fmask[] = {
117	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
118	[GEN_QMB_1_MAX_READS]				= GENMASK(7, 4),
119						/* Bits 8-15 reserved */
120	[GEN_QMB_0_MAX_READS_BEATS]			= GENMASK(23, 16),
121	[GEN_QMB_1_MAX_READS_BEATS]			= GENMASK(31, 24),
122};
123
124REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000058);
125
126/* Valid bits defined by ipa->available */
127
128REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000100, 0x0004);
129
130static const u32 reg_filt_rout_cache_flush_fmask[] = {
131	[ROUTER_CACHE]					= BIT(0),
132						/* Bits 1-3 reserved */
133	[FILTER_CACHE]					= BIT(4),
134						/* Bits 5-31 reserved */
135};
136
137REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
138
139static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
140	[IPA_BASE_ADDR]					= GENMASK(17, 0),
141						/* Bits 18-31 reserved */
142};
143
144/* Offset must be a multiple of 8 */
145REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
146
147static const u32 reg_ipa_tx_cfg_fmask[] = {
148						/* Bits 0-1 reserved */
149	[PREFETCH_ALMOST_EMPTY_SIZE_TX0]		= GENMASK(5, 2),
150	[DMAW_SCND_OUTSD_PRED_THRESHOLD]		= GENMASK(9, 6),
151	[DMAW_SCND_OUTSD_PRED_EN]			= BIT(10),
152	[DMAW_MAX_BEATS_256_DIS]			= BIT(11),
153	[PA_MASK_EN]					= BIT(12),
154	[PREFETCH_ALMOST_EMPTY_SIZE_TX1]		= GENMASK(16, 13),
155	[DUAL_TX_ENABLE]				= BIT(17),
156	[SSPND_PA_NO_START_STATE]			= BIT(18),
157						/* Bit 19 reserved */
158	[HOLB_STICKY_DROP_EN]				= BIT(20),
159						/* Bits 21-31 reserved */
160};
161
162REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
163
164static const u32 reg_idle_indication_cfg_fmask[] = {
165	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),
166	[CONST_NON_IDLE_ENABLE]				= BIT(16),
167						/* Bits 17-31 reserved */
168};
169
170REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
171
172static const u32 reg_qtime_timestamp_cfg_fmask[] = {
173	[DPL_TIMESTAMP_LSB]				= GENMASK(4, 0),
174						/* Bits 5-6 reserved */
175	[DPL_TIMESTAMP_SEL]				= BIT(7),
176	[TAG_TIMESTAMP_LSB]				= GENMASK(12, 8),
177						/* Bits 13-15 reserved */
178	[NAT_TIMESTAMP_LSB]				= GENMASK(20, 16),
179						/* Bits 21-31 reserved */
180};
181
182REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
183
184static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
185	[DIV_VALUE]					= GENMASK(8, 0),
186						/* Bits 9-30 reserved */
187	[DIV_ENABLE]					= BIT(31),
188};
189
190REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
191
192static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
193	[PULSE_GRAN_0]					= GENMASK(2, 0),
194	[PULSE_GRAN_1]					= GENMASK(5, 3),
195	[PULSE_GRAN_2]					= GENMASK(8, 6),
196	[PULSE_GRAN_3]					= GENMASK(11, 9),
197						/* Bits 12-31 reserved */
198};
199
200REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
201
202static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
203	[X_MIN_LIM]					= GENMASK(5, 0),
204						/* Bits 6-7 reserved */
205	[X_MAX_LIM]					= GENMASK(13, 8),
206						/* Bits 14-15 reserved */
207	[Y_MIN_LIM]					= GENMASK(21, 16),
208						/* Bits 22-23 reserved */
209	[Y_MAX_LIM]					= GENMASK(29, 24),
210						/* Bits 30-31 reserved */
211};
212
213REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
214		  0x00000500, 0x0020);
215
216static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
217	[X_MIN_LIM]					= GENMASK(5, 0),
218						/* Bits 6-7 reserved */
219	[X_MAX_LIM]					= GENMASK(13, 8),
220						/* Bits 14-15 reserved */
221	[Y_MIN_LIM]					= GENMASK(21, 16),
222						/* Bits 22-23 reserved */
223	[Y_MAX_LIM]					= GENMASK(29, 24),
224						/* Bits 30-31 reserved */
225};
226
227REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
228		  0x00000504, 0x0020);
229
230static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
231	[X_MIN_LIM]					= GENMASK(5, 0),
232						/* Bits 6-7 reserved */
233	[X_MAX_LIM]					= GENMASK(13, 8),
234						/* Bits 14-15 reserved */
235	[Y_MIN_LIM]					= GENMASK(21, 16),
236						/* Bits 22-23 reserved */
237	[Y_MAX_LIM]					= GENMASK(29, 24),
238						/* Bits 30-31 reserved */
239};
240
241REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
242		  0x00000508, 0x0020);
243
244static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
245	[X_MIN_LIM]					= GENMASK(5, 0),
246						/* Bits 6-7 reserved */
247	[X_MAX_LIM]					= GENMASK(13, 8),
248						/* Bits 14-15 reserved */
249	[Y_MIN_LIM]					= GENMASK(21, 16),
250						/* Bits 22-23 reserved */
251	[Y_MAX_LIM]					= GENMASK(29, 24),
252						/* Bits 30-31 reserved */
253};
254
255REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
256		  0x0000050c, 0x0020);
257
258static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
259	[X_MIN_LIM]					= GENMASK(5, 0),
260						/* Bits 6-7 reserved */
261	[X_MAX_LIM]					= GENMASK(13, 8),
262						/* Bits 14-15 reserved */
263	[Y_MIN_LIM]					= GENMASK(21, 16),
264						/* Bits 22-23 reserved */
265	[Y_MAX_LIM]					= GENMASK(29, 24),
266						/* Bits 30-31 reserved */
267};
268
269REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
270		  0x00000600, 0x0020);
271
272static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
273	[X_MIN_LIM]					= GENMASK(5, 0),
274						/* Bits 6-7 reserved */
275	[X_MAX_LIM]					= GENMASK(13, 8),
276						/* Bits 14-15 reserved */
277	[Y_MIN_LIM]					= GENMASK(21, 16),
278						/* Bits 22-23 reserved */
279	[Y_MAX_LIM]					= GENMASK(29, 24),
280						/* Bits 30-31 reserved */
281};
282
283REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
284		  0x00000604, 0x0020);
285
286static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
287	[X_MIN_LIM]					= GENMASK(5, 0),
288						/* Bits 6-7 reserved */
289	[X_MAX_LIM]					= GENMASK(13, 8),
290						/* Bits 14-15 reserved */
291	[Y_MIN_LIM]					= GENMASK(21, 16),
292						/* Bits 22-23 reserved */
293	[Y_MAX_LIM]					= GENMASK(29, 24),
294						/* Bits 30-31 reserved */
295};
296
297REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
298		  0x00000608, 0x0020);
299
300static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
301	[X_MIN_LIM]					= GENMASK(5, 0),
302						/* Bits 6-7 reserved */
303	[X_MAX_LIM]					= GENMASK(13, 8),
304						/* Bits 14-15 reserved */
305	[Y_MIN_LIM]					= GENMASK(21, 16),
306						/* Bits 22-23 reserved */
307	[Y_MAX_LIM]					= GENMASK(29, 24),
308						/* Bits 30-31 reserved */
309};
310
311REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
312		  0x0000060c, 0x0020);
313
314/* Valid bits defined by ipa->available */
315
316REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
317
318static const u32 reg_endp_init_cfg_fmask[] = {
319	[FRAG_OFFLOAD_EN]				= BIT(0),
320	[CS_OFFLOAD_EN]					= GENMASK(2, 1),
321	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),
322						/* Bit 7 reserved */
323	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),
324						/* Bits 9-31 reserved */
325};
326
327REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
328
329static const u32 reg_endp_init_nat_fmask[] = {
330	[NAT_EN]					= GENMASK(1, 0),
331						/* Bits 2-31 reserved */
332};
333
334REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
335
336static const u32 reg_endp_init_hdr_fmask[] = {
337	[HDR_LEN]					= GENMASK(5, 0),
338	[HDR_OFST_METADATA_VALID]			= BIT(6),
339	[HDR_OFST_METADATA]				= GENMASK(12, 7),
340	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),
341	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),
342	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),
343						/* Bit 26 reserved */
344	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),
345	[HDR_LEN_MSB]					= GENMASK(29, 28),
346	[HDR_OFST_METADATA_MSB]				= GENMASK(31, 30),
347};
348
349REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
350
351static const u32 reg_endp_init_hdr_ext_fmask[] = {
352	[HDR_ENDIANNESS]				= BIT(0),
353	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),
354	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),
355	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),
356	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),
357	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),
358						/* Bits 14-15 reserved */
359	[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB]		= GENMASK(17, 16),
360	[HDR_OFST_PKT_SIZE_MSB]				= GENMASK(19, 18),
361	[HDR_ADDITIONAL_CONST_LEN_MSB]			= GENMASK(21, 20),
362	[HDR_BYTES_TO_REMOVE_VALID]			= BIT(22),
363						/* Bit 23 reserved */
364	[HDR_BYTES_TO_REMOVE]				= GENMASK(31, 24),
365};
366
367REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
368
369REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
370	   0x00001018, 0x0080);
371
372static const u32 reg_endp_init_mode_fmask[] = {
373	[ENDP_MODE]					= GENMASK(2, 0),
374	[DCPH_ENABLE]					= BIT(3),
375	[DEST_PIPE_INDEX]				= GENMASK(11, 4),
376	[BYTE_THRESHOLD]				= GENMASK(27, 12),
377	[PIPE_REPLICATION_EN]				= BIT(28),
378	[PAD_EN]					= BIT(29),
379	[DRBIP_ACL_ENABLE]				= BIT(30),
380						/* Bit 31 reserved */
381};
382
383REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
384
385static const u32 reg_endp_init_aggr_fmask[] = {
386	[AGGR_EN]					= GENMASK(1, 0),
387	[AGGR_TYPE]					= GENMASK(4, 2),
388	[BYTE_LIMIT]					= GENMASK(10, 5),
389						/* Bit 11 reserved */
390	[TIME_LIMIT]					= GENMASK(16, 12),
391	[PKT_LIMIT]					= GENMASK(22, 17),
392	[SW_EOF_ACTIVE]					= BIT(23),
393	[FORCE_CLOSE]					= BIT(24),
394						/* Bit 25 reserved */
395	[HARD_BYTE_LIMIT_EN]				= BIT(26),
396	[AGGR_GRAN_SEL]					= BIT(27),
397						/* Bits 28-31 reserved */
398};
399
400REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
401
402static const u32 reg_endp_init_hol_block_en_fmask[] = {
403	[HOL_BLOCK_EN]					= BIT(0),
404						/* Bits 1-31 reserved */
405};
406
407REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
408		  0x0000102c, 0x0080);
409
410static const u32 reg_endp_init_hol_block_timer_fmask[] = {
411	[TIMER_LIMIT]					= GENMASK(4, 0),
412						/* Bits 5-7 reserved */
413	[TIMER_GRAN_SEL]				= GENMASK(9, 8),
414						/* Bits 10-31 reserved */
415};
416
417REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
418		  0x00001030, 0x0080);
419
420static const u32 reg_endp_init_deaggr_fmask[] = {
421	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),
422	[SYSPIPE_ERR_DETECTION]				= BIT(6),
423	[PACKET_OFFSET_VALID]				= BIT(7),
424	[PACKET_OFFSET_LOCATION]			= GENMASK(13, 8),
425	[IGNORE_MIN_PKT_ERR]				= BIT(14),
426						/* Bit 15 reserved */
427	[MAX_PACKET_LEN]				= GENMASK(31, 16),
428};
429
430REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
431
432static const u32 reg_endp_init_rsrc_grp_fmask[] = {
433	[ENDP_RSRC_GRP]					= GENMASK(2, 0),
434						/* Bits 3-31 reserved */
435};
436
437REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
438
439static const u32 reg_endp_init_seq_fmask[] = {
440	[SEQ_TYPE]					= GENMASK(7, 0),
441						/* Bits 8-31 reserved */
442};
443
444REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
445
446static const u32 reg_endp_status_fmask[] = {
447	[STATUS_EN]					= BIT(0),
448	[STATUS_ENDP]					= GENMASK(8, 1),
449	[STATUS_PKT_SUPPRESS]				= BIT(9),
450						/* Bits 10-31 reserved */
451};
452
453REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
454
455static const u32 reg_endp_filter_cache_cfg_fmask[] = {
456	[CACHE_MSK_SRC_ID]				= BIT(0),
457	[CACHE_MSK_SRC_IP]				= BIT(1),
458	[CACHE_MSK_DST_IP]				= BIT(2),
459	[CACHE_MSK_SRC_PORT]				= BIT(3),
460	[CACHE_MSK_DST_PORT]				= BIT(4),
461	[CACHE_MSK_PROTOCOL]				= BIT(5),
462	[CACHE_MSK_METADATA]				= BIT(6),
463						/* Bits 7-31 reserved */
464};
465
466REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,
467		  0x0000105c, 0x0080);
468
469static const u32 reg_endp_router_cache_cfg_fmask[] = {
470	[CACHE_MSK_SRC_ID]				= BIT(0),
471	[CACHE_MSK_SRC_IP]				= BIT(1),
472	[CACHE_MSK_DST_IP]				= BIT(2),
473	[CACHE_MSK_SRC_PORT]				= BIT(3),
474	[CACHE_MSK_DST_PORT]				= BIT(4),
475	[CACHE_MSK_PROTOCOL]				= BIT(5),
476	[CACHE_MSK_METADATA]				= BIT(6),
477						/* Bits 7-31 reserved */
478};
479
480REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,
481		  0x00001070, 0x0080);
482
483/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
484REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
485
486/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
487REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
488
489/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
490REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
491
492static const u32 reg_ipa_irq_uc_fmask[] = {
493	[UC_INTR]					= BIT(0),
494						/* Bits 1-31 reserved */
495};
496
497REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
498
499/* Valid bits defined by ipa->available */
500
501REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
502	   0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
503
504/* Valid bits defined by ipa->available */
505
506REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
507	   0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
508
509/* Valid bits defined by ipa->available */
510
511REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
512	   0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);
513
514static const struct reg *reg_array[] = {
515	[COMP_CFG]			= &reg_comp_cfg,
516	[CLKON_CFG]			= &reg_clkon_cfg,
517	[ROUTE]				= &reg_route,
518	[SHARED_MEM_SIZE]		= &reg_shared_mem_size,
519	[QSB_MAX_WRITES]		= &reg_qsb_max_writes,
520	[QSB_MAX_READS]			= &reg_qsb_max_reads,
521	[FILT_ROUT_CACHE_FLUSH]		= &reg_filt_rout_cache_flush,
522	[STATE_AGGR_ACTIVE]		= &reg_state_aggr_active,
523	[LOCAL_PKT_PROC_CNTXT]		= &reg_local_pkt_proc_cntxt,
524	[AGGR_FORCE_CLOSE]		= &reg_aggr_force_close,
525	[IPA_TX_CFG]			= &reg_ipa_tx_cfg,
526	[FLAVOR_0]			= &reg_flavor_0,
527	[IDLE_INDICATION_CFG]		= &reg_idle_indication_cfg,
528	[QTIME_TIMESTAMP_CFG]		= &reg_qtime_timestamp_cfg,
529	[TIMERS_XO_CLK_DIV_CFG]		= &reg_timers_xo_clk_div_cfg,
530	[TIMERS_PULSE_GRAN_CFG]		= &reg_timers_pulse_gran_cfg,
531	[SRC_RSRC_GRP_01_RSRC_TYPE]	= &reg_src_rsrc_grp_01_rsrc_type,
532	[SRC_RSRC_GRP_23_RSRC_TYPE]	= &reg_src_rsrc_grp_23_rsrc_type,
533	[SRC_RSRC_GRP_45_RSRC_TYPE]	= &reg_src_rsrc_grp_45_rsrc_type,
534	[SRC_RSRC_GRP_67_RSRC_TYPE]	= &reg_src_rsrc_grp_67_rsrc_type,
535	[DST_RSRC_GRP_01_RSRC_TYPE]	= &reg_dst_rsrc_grp_01_rsrc_type,
536	[DST_RSRC_GRP_23_RSRC_TYPE]	= &reg_dst_rsrc_grp_23_rsrc_type,
537	[DST_RSRC_GRP_45_RSRC_TYPE]	= &reg_dst_rsrc_grp_45_rsrc_type,
538	[DST_RSRC_GRP_67_RSRC_TYPE]	= &reg_dst_rsrc_grp_67_rsrc_type,
539	[ENDP_INIT_CFG]			= &reg_endp_init_cfg,
540	[ENDP_INIT_NAT]			= &reg_endp_init_nat,
541	[ENDP_INIT_HDR]			= &reg_endp_init_hdr,
542	[ENDP_INIT_HDR_EXT]		= &reg_endp_init_hdr_ext,
543	[ENDP_INIT_HDR_METADATA_MASK]	= &reg_endp_init_hdr_metadata_mask,
544	[ENDP_INIT_MODE]		= &reg_endp_init_mode,
545	[ENDP_INIT_AGGR]		= &reg_endp_init_aggr,
546	[ENDP_INIT_HOL_BLOCK_EN]	= &reg_endp_init_hol_block_en,
547	[ENDP_INIT_HOL_BLOCK_TIMER]	= &reg_endp_init_hol_block_timer,
548	[ENDP_INIT_DEAGGR]		= &reg_endp_init_deaggr,
549	[ENDP_INIT_RSRC_GRP]		= &reg_endp_init_rsrc_grp,
550	[ENDP_INIT_SEQ]			= &reg_endp_init_seq,
551	[ENDP_STATUS]			= &reg_endp_status,
552	[ENDP_FILTER_CACHE_CFG]		= &reg_endp_filter_cache_cfg,
553	[ENDP_ROUTER_CACHE_CFG]		= &reg_endp_router_cache_cfg,
554	[IPA_IRQ_STTS]			= &reg_ipa_irq_stts,
555	[IPA_IRQ_EN]			= &reg_ipa_irq_en,
556	[IPA_IRQ_CLR]			= &reg_ipa_irq_clr,
557	[IPA_IRQ_UC]			= &reg_ipa_irq_uc,
558	[IRQ_SUSPEND_INFO]		= &reg_irq_suspend_info,
559	[IRQ_SUSPEND_EN]		= &reg_irq_suspend_en,
560	[IRQ_SUSPEND_CLR]		= &reg_irq_suspend_clr,
561};
562
563const struct regs ipa_regs_v5_0 = {
564	.reg_count	= ARRAY_SIZE(reg_array),
565	.reg		= reg_array,
566};
567