1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Definitions for Xilinx Axi Ethernet device driver. 4 * 5 * Copyright (c) 2009 Secret Lab Technologies, Ltd. 6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. 7 */ 8 9#ifndef XILINX_AXIENET_H 10#define XILINX_AXIENET_H 11 12#include <linux/netdevice.h> 13#include <linux/spinlock.h> 14#include <linux/interrupt.h> 15#include <linux/if_vlan.h> 16#include <linux/phylink.h> 17#include <linux/skbuff.h> 18 19/* Packet size info */ 20#define XAE_HDR_SIZE 14 /* Size of Ethernet header */ 21#define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */ 22#define XAE_MTU 1500 /* Max MTU of an Ethernet frame */ 23#define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */ 24 25#define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) 26#define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + VLAN_ETH_HLEN + XAE_TRL_SIZE) 27#define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) 28 29/* Configuration options */ 30 31/* Accept all incoming packets. Default: disabled (cleared) */ 32#define XAE_OPTION_PROMISC (1 << 0) 33 34/* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */ 35#define XAE_OPTION_JUMBO (1 << 1) 36 37/* VLAN Rx & Tx frame support. Default: disabled (cleared) */ 38#define XAE_OPTION_VLAN (1 << 2) 39 40/* Enable recognition of flow control frames on Rx. Default: enabled (set) */ 41#define XAE_OPTION_FLOW_CONTROL (1 << 4) 42 43/* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not 44 * stripped. Default: disabled (set) 45 */ 46#define XAE_OPTION_FCS_STRIP (1 << 5) 47 48/* Generate FCS field and add PAD automatically for outgoing frames. 49 * Default: enabled (set) 50 */ 51#define XAE_OPTION_FCS_INSERT (1 << 6) 52 53/* Enable Length/Type error checking for incoming frames. When this option is 54 * set, the MAC will filter frames that have a mismatched type/length field 55 * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these 56 * types of frames are encountered. When this option is cleared, the MAC will 57 * allow these types of frames to be received. Default: enabled (set) 58 */ 59#define XAE_OPTION_LENTYPE_ERR (1 << 7) 60 61/* Enable the transmitter. Default: enabled (set) */ 62#define XAE_OPTION_TXEN (1 << 11) 63 64/* Enable the receiver. Default: enabled (set) */ 65#define XAE_OPTION_RXEN (1 << 12) 66 67/* Default options set when device is initialized or reset */ 68#define XAE_OPTION_DEFAULTS \ 69 (XAE_OPTION_TXEN | \ 70 XAE_OPTION_FLOW_CONTROL | \ 71 XAE_OPTION_RXEN) 72 73/* Axi DMA Register definitions */ 74 75#define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */ 76#define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */ 77#define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */ 78#define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */ 79 80#define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */ 81#define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */ 82#define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */ 83#define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */ 84 85#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ 86#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ 87 88#define XAXIDMA_SR_HALT_MASK 0x00000001 /* Indicates DMA channel halted */ 89 90#define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */ 91#define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */ 92#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */ 93#define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */ 94#define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */ 95#define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */ 96#define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */ 97#define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */ 98#define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */ 99#define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */ 100#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */ 101#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */ 102 103#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */ 104#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */ 105#define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */ 106 107#define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */ 108#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 109#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 110#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ 111 112#define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */ 113#define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */ 114 115#define XAXIDMA_DELAY_SHIFT 24 116#define XAXIDMA_COALESCE_SHIFT 16 117 118#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ 119#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ 120#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */ 121#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ 122 123/* Default TX/RX Threshold and delay timer values for SGDMA mode */ 124#define XAXIDMA_DFT_TX_THRESHOLD 24 125#define XAXIDMA_DFT_TX_USEC 50 126#define XAXIDMA_DFT_RX_THRESHOLD 1 127#define XAXIDMA_DFT_RX_USEC 50 128 129#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 130#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 131#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ 132 133#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */ 134#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */ 135#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */ 136#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */ 137#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */ 138#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */ 139#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */ 140#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */ 141#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */ 142 143#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 144 145/* Axi Ethernet registers definition */ 146#define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */ 147#define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */ 148#define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/ 149#define XAE_IS_OFFSET 0x0000000C /* Interrupt status */ 150#define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */ 151#define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */ 152#define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */ 153#define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */ 154#define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */ 155#define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */ 156#define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */ 157#define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */ 158#define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */ 159#define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */ 160#define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */ 161#define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */ 162#define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */ 163#define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ 164#define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */ 165#define XAE_ID_OFFSET 0x000004F8 /* Identification register */ 166#define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ 167#define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ 168#define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */ 169#define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */ 170#define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */ 171#define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */ 172#define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */ 173#define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */ 174#define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */ 175 176#define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */ 177#define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */ 178#define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */ 179 180/* Bit Masks for Axi Ethernet RAF register */ 181/* Reject receive multicast destination address */ 182#define XAE_RAF_MCSTREJ_MASK 0x00000002 183/* Reject receive broadcast destination address */ 184#define XAE_RAF_BCSTREJ_MASK 0x00000004 185#define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */ 186#define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */ 187#define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */ 188#define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */ 189#define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */ 190/* Extended Multicast Filtering mode */ 191#define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000 192#define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */ 193#define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */ 194#define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */ 195#define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */ 196#define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/ 197#define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/ 198 199/* Bit Masks for Axi Ethernet TPF and IFGP registers */ 200#define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */ 201/* Transmit inter-frame gap adjustment value */ 202#define XAE_IFGP0_IFGP_MASK 0x0000007F 203 204/* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply 205 * for all 3 registers. 206 */ 207/* Hard register access complete */ 208#define XAE_INT_HARDACSCMPLT_MASK 0x00000001 209/* Auto negotiation complete */ 210#define XAE_INT_AUTONEG_MASK 0x00000002 211#define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */ 212#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ 213#define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */ 214#define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */ 215#define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */ 216#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ 217#define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */ 218#define XAE_INT_ALL_MASK 0x0000003F /* All the ints */ 219 220/* INT bits that indicate receive errors */ 221#define XAE_INT_RECV_ERROR_MASK \ 222 (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK) 223 224/* Bit masks for Axi Ethernet VLAN TPID Word 0 register */ 225#define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */ 226#define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */ 227 228/* Bit masks for Axi Ethernet VLAN TPID Word 1 register */ 229#define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */ 230#define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */ 231 232/* Bit masks for Axi Ethernet RCW1 register */ 233#define XAE_RCW1_RST_MASK 0x80000000 /* Reset */ 234#define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */ 235/* In-Band FCS enable (FCS not stripped) */ 236#define XAE_RCW1_FCS_MASK 0x20000000 237#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ 238#define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */ 239/* Length/type field valid check disable */ 240#define XAE_RCW1_LT_DIS_MASK 0x02000000 241/* Control frame Length check disable */ 242#define XAE_RCW1_CL_DIS_MASK 0x01000000 243/* Pause frame source address bits [47:32]. Bits [31:0] are 244 * stored in register RCW0 245 */ 246#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF 247 248/* Bit masks for Axi Ethernet TC register */ 249#define XAE_TC_RST_MASK 0x80000000 /* Reset */ 250#define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */ 251/* In-Band FCS enable (FCS not generated) */ 252#define XAE_TC_FCS_MASK 0x20000000 253#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ 254#define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */ 255/* Inter-frame gap adjustment enable */ 256#define XAE_TC_IFG_MASK 0x02000000 257 258/* Bit masks for Axi Ethernet FCC register */ 259#define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */ 260#define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */ 261 262/* Bit masks for Axi Ethernet EMMC register */ 263#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ 264#define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */ 265#define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */ 266#define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */ 267#define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */ 268#define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */ 269#define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */ 270#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ 271#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ 272#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ 273 274/* Bit masks for Axi Ethernet PHYC register */ 275#define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/ 276#define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */ 277#define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */ 278#define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */ 279#define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */ 280#define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */ 281#define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */ 282#define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */ 283#define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */ 284#define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */ 285 286/* Bit masks for Axi Ethernet MDIO interface MC register */ 287#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */ 288#define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */ 289 290/* Bit masks for Axi Ethernet MDIO interface MCR register */ 291#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ 292#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ 293#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ 294#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ 295#define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */ 296#define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */ 297#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ 298#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ 299#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ 300#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ 301 302/* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */ 303#define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */ 304 305/* Bit masks for Axi Ethernet UAW1 register */ 306/* Station address bits [47:32]; Station address 307 * bits [31:0] are stored in register UAW0 308 */ 309#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF 310 311/* Bit masks for Axi Ethernet FMI register */ 312#define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */ 313#define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */ 314 315#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ 316 317/* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */ 318#define XAE_PHY_TYPE_MII 0 319#define XAE_PHY_TYPE_GMII 1 320#define XAE_PHY_TYPE_RGMII_1_3 2 321#define XAE_PHY_TYPE_RGMII_2_0 3 322#define XAE_PHY_TYPE_SGMII 4 323#define XAE_PHY_TYPE_1000BASE_X 5 324 325 /* Total number of entries in the hardware multicast table. */ 326#define XAE_MULTICAST_CAM_TABLE_NUM 4 327 328/* Axi Ethernet Synthesis features */ 329#define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0) 330#define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1) 331#define XAE_FEATURE_FULL_RX_CSUM (1 << 2) 332#define XAE_FEATURE_FULL_TX_CSUM (1 << 3) 333#define XAE_FEATURE_DMA_64BIT (1 << 4) 334 335#define XAE_NO_CSUM_OFFLOAD 0 336 337#define XAE_FULL_CSUM_STATUS_MASK 0x00000038 338#define XAE_IP_UDP_CSUM_VALIDATED 0x00000003 339#define XAE_IP_TCP_CSUM_VALIDATED 0x00000002 340 341#define DELAY_OF_ONE_MILLISEC 1000 342 343/* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */ 344#define XLNX_MII_STD_SELECT_REG 0x11 345#define XLNX_MII_STD_SELECT_SGMII BIT(0) 346 347/** 348 * struct axidma_bd - Axi Dma buffer descriptor layout 349 * @next: MM2S/S2MM Next Descriptor Pointer 350 * @next_msb: MM2S/S2MM Next Descriptor Pointer (high 32 bits) 351 * @phys: MM2S/S2MM Buffer Address 352 * @phys_msb: MM2S/S2MM Buffer Address (high 32 bits) 353 * @reserved3: Reserved and not used 354 * @reserved4: Reserved and not used 355 * @cntrl: MM2S/S2MM Control value 356 * @status: MM2S/S2MM Status value 357 * @app0: MM2S/S2MM User Application Field 0. 358 * @app1: MM2S/S2MM User Application Field 1. 359 * @app2: MM2S/S2MM User Application Field 2. 360 * @app3: MM2S/S2MM User Application Field 3. 361 * @app4: MM2S/S2MM User Application Field 4. 362 */ 363struct axidma_bd { 364 u32 next; /* Physical address of next buffer descriptor */ 365 u32 next_msb; /* high 32 bits for IP >= v7.1, reserved on older IP */ 366 u32 phys; 367 u32 phys_msb; /* for IP >= v7.1, reserved for older IP */ 368 u32 reserved3; 369 u32 reserved4; 370 u32 cntrl; 371 u32 status; 372 u32 app0; 373 u32 app1; /* TX start << 16 | insert */ 374 u32 app2; /* TX csum seed */ 375 u32 app3; 376 u32 app4; /* Last field used by HW */ 377 struct sk_buff *skb; 378} __aligned(XAXIDMA_BD_MINIMUM_ALIGNMENT); 379 380#define XAE_NUM_MISC_CLOCKS 3 381 382/** 383 * struct skbuf_dma_descriptor - skb for each dma descriptor 384 * @sgl: Pointer for sglist. 385 * @desc: Pointer to dma descriptor. 386 * @dma_address: dma address of sglist. 387 * @skb: Pointer to SKB transferred using DMA 388 * @sg_len: number of entries in the sglist. 389 */ 390struct skbuf_dma_descriptor { 391 struct scatterlist sgl[MAX_SKB_FRAGS + 1]; 392 struct dma_async_tx_descriptor *desc; 393 dma_addr_t dma_address; 394 struct sk_buff *skb; 395 int sg_len; 396}; 397 398/** 399 * struct axienet_local - axienet private per device data 400 * @ndev: Pointer for net_device to which it will be attached. 401 * @dev: Pointer to device structure 402 * @phy_node: Pointer to device node structure 403 * @phylink: Pointer to phylink instance 404 * @phylink_config: phylink configuration settings 405 * @pcs_phy: Reference to PCS/PMA PHY if used 406 * @pcs: phylink pcs structure for PCS PHY 407 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core 408 * @axi_clk: AXI4-Lite bus clock 409 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks) 410 * @mii_bus: Pointer to MII bus structure 411 * @mii_clk_div: MII bus clock divider value 412 * @regs_start: Resource start for axienet device addresses 413 * @regs: Base address for the axienet_local device address space 414 * @dma_regs: Base address for the axidma device address space 415 * @napi_rx: NAPI RX control structure 416 * @rx_dma_cr: Nominal content of RX DMA control register 417 * @rx_bd_v: Virtual address of the RX buffer descriptor ring 418 * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring 419 * @rx_bd_num: Size of RX buffer descriptor ring 420 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being 421 * accessed currently. 422 * @rx_packets: RX packet count for statistics 423 * @rx_bytes: RX byte count for statistics 424 * @rx_stat_sync: Synchronization object for RX stats 425 * @napi_tx: NAPI TX control structure 426 * @tx_dma_cr: Nominal content of TX DMA control register 427 * @tx_bd_v: Virtual address of the TX buffer descriptor ring 428 * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring 429 * @tx_bd_num: Size of TX buffer descriptor ring 430 * @tx_bd_ci: Stores the next Tx buffer descriptor in the ring that may be 431 * complete. Only updated at runtime by TX NAPI poll. 432 * @tx_bd_tail: Stores the index of the next Tx buffer descriptor in the ring 433 * to be populated. 434 * @tx_packets: TX packet count for statistics 435 * @tx_bytes: TX byte count for statistics 436 * @tx_stat_sync: Synchronization object for TX stats 437 * @dma_err_task: Work structure to process Axi DMA errors 438 * @tx_irq: Axidma TX IRQ number 439 * @rx_irq: Axidma RX IRQ number 440 * @eth_irq: Ethernet core IRQ number 441 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X 442 * @options: AxiEthernet option word 443 * @features: Stores the extended features supported by the axienet hw 444 * @max_frm_size: Stores the maximum size of the frame that can be that 445 * Txed/Rxed in the existing hardware. If jumbo option is 446 * supported, the maximum frame size would be 9k. Else it is 447 * 1522 bytes (assuming support for basic VLAN) 448 * @rxmem: Stores rx memory size for jumbo frame handling. 449 * @csum_offload_on_tx_path: Stores the checksum selection on TX side. 450 * @csum_offload_on_rx_path: Stores the checksum selection on RX side. 451 * @coalesce_count_rx: Store the irq coalesce on RX side. 452 * @coalesce_usec_rx: IRQ coalesce delay for RX 453 * @coalesce_count_tx: Store the irq coalesce on TX side. 454 * @coalesce_usec_tx: IRQ coalesce delay for TX 455 * @use_dmaengine: flag to check dmaengine framework usage. 456 * @tx_chan: TX DMA channel. 457 * @rx_chan: RX DMA channel. 458 * @tx_skb_ring: Pointer to TX skb ring buffer array. 459 * @rx_skb_ring: Pointer to RX skb ring buffer array. 460 * @tx_ring_head: TX skb ring buffer head index. 461 * @tx_ring_tail: TX skb ring buffer tail index. 462 * @rx_ring_head: RX skb ring buffer head index. 463 * @rx_ring_tail: RX skb ring buffer tail index. 464 */ 465struct axienet_local { 466 struct net_device *ndev; 467 struct device *dev; 468 469 struct phylink *phylink; 470 struct phylink_config phylink_config; 471 472 struct mdio_device *pcs_phy; 473 struct phylink_pcs pcs; 474 475 bool switch_x_sgmii; 476 477 struct clk *axi_clk; 478 struct clk_bulk_data misc_clks[XAE_NUM_MISC_CLOCKS]; 479 480 struct mii_bus *mii_bus; 481 u8 mii_clk_div; 482 483 resource_size_t regs_start; 484 void __iomem *regs; 485 void __iomem *dma_regs; 486 487 struct napi_struct napi_rx; 488 u32 rx_dma_cr; 489 struct axidma_bd *rx_bd_v; 490 dma_addr_t rx_bd_p; 491 u32 rx_bd_num; 492 u32 rx_bd_ci; 493 u64_stats_t rx_packets; 494 u64_stats_t rx_bytes; 495 struct u64_stats_sync rx_stat_sync; 496 497 struct napi_struct napi_tx; 498 u32 tx_dma_cr; 499 struct axidma_bd *tx_bd_v; 500 dma_addr_t tx_bd_p; 501 u32 tx_bd_num; 502 u32 tx_bd_ci; 503 u32 tx_bd_tail; 504 u64_stats_t tx_packets; 505 u64_stats_t tx_bytes; 506 struct u64_stats_sync tx_stat_sync; 507 508 struct work_struct dma_err_task; 509 510 int tx_irq; 511 int rx_irq; 512 int eth_irq; 513 phy_interface_t phy_mode; 514 515 u32 options; 516 u32 features; 517 518 u32 max_frm_size; 519 u32 rxmem; 520 521 int csum_offload_on_tx_path; 522 int csum_offload_on_rx_path; 523 524 u32 coalesce_count_rx; 525 u32 coalesce_usec_rx; 526 u32 coalesce_count_tx; 527 u32 coalesce_usec_tx; 528 u8 use_dmaengine; 529 struct dma_chan *tx_chan; 530 struct dma_chan *rx_chan; 531 struct skbuf_dma_descriptor **tx_skb_ring; 532 struct skbuf_dma_descriptor **rx_skb_ring; 533 int tx_ring_head; 534 int tx_ring_tail; 535 int rx_ring_head; 536 int rx_ring_tail; 537}; 538 539/** 540 * struct axiethernet_option - Used to set axi ethernet hardware options 541 * @opt: Option to be set. 542 * @reg: Register offset to be written for setting the option 543 * @m_or: Mask to be ORed for setting the option in the register 544 */ 545struct axienet_option { 546 u32 opt; 547 u32 reg; 548 u32 m_or; 549}; 550 551/** 552 * axienet_ior - Memory mapped Axi Ethernet register read 553 * @lp: Pointer to axienet local structure 554 * @offset: Address offset from the base address of Axi Ethernet core 555 * 556 * Return: The contents of the Axi Ethernet register 557 * 558 * This function returns the contents of the corresponding register. 559 */ 560static inline u32 axienet_ior(struct axienet_local *lp, off_t offset) 561{ 562 return ioread32(lp->regs + offset); 563} 564 565static inline u32 axinet_ior_read_mcr(struct axienet_local *lp) 566{ 567 return axienet_ior(lp, XAE_MDIO_MCR_OFFSET); 568} 569 570static inline void axienet_lock_mii(struct axienet_local *lp) 571{ 572 if (lp->mii_bus) 573 mutex_lock(&lp->mii_bus->mdio_lock); 574} 575 576static inline void axienet_unlock_mii(struct axienet_local *lp) 577{ 578 if (lp->mii_bus) 579 mutex_unlock(&lp->mii_bus->mdio_lock); 580} 581 582/** 583 * axienet_iow - Memory mapped Axi Ethernet register write 584 * @lp: Pointer to axienet local structure 585 * @offset: Address offset from the base address of Axi Ethernet core 586 * @value: Value to be written into the Axi Ethernet register 587 * 588 * This function writes the desired value into the corresponding Axi Ethernet 589 * register. 590 */ 591static inline void axienet_iow(struct axienet_local *lp, off_t offset, 592 u32 value) 593{ 594 iowrite32(value, lp->regs + offset); 595} 596 597/** 598 * axienet_dma_out32 - Memory mapped Axi DMA register write. 599 * @lp: Pointer to axienet local structure 600 * @reg: Address offset from the base address of the Axi DMA core 601 * @value: Value to be written into the Axi DMA register 602 * 603 * This function writes the desired value into the corresponding Axi DMA 604 * register. 605 */ 606 607static inline void axienet_dma_out32(struct axienet_local *lp, 608 off_t reg, u32 value) 609{ 610 iowrite32(value, lp->dma_regs + reg); 611} 612 613#if defined(CONFIG_64BIT) && defined(iowrite64) 614/** 615 * axienet_dma_out64 - Memory mapped Axi DMA register write. 616 * @lp: Pointer to axienet local structure 617 * @reg: Address offset from the base address of the Axi DMA core 618 * @value: Value to be written into the Axi DMA register 619 * 620 * This function writes the desired value into the corresponding Axi DMA 621 * register. 622 */ 623static inline void axienet_dma_out64(struct axienet_local *lp, 624 off_t reg, u64 value) 625{ 626 iowrite64(value, lp->dma_regs + reg); 627} 628 629static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg, 630 dma_addr_t addr) 631{ 632 if (lp->features & XAE_FEATURE_DMA_64BIT) 633 axienet_dma_out64(lp, reg, addr); 634 else 635 axienet_dma_out32(lp, reg, lower_32_bits(addr)); 636} 637 638#else /* CONFIG_64BIT */ 639 640static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg, 641 dma_addr_t addr) 642{ 643 axienet_dma_out32(lp, reg, lower_32_bits(addr)); 644} 645 646#endif /* CONFIG_64BIT */ 647 648/* Function prototypes visible in xilinx_axienet_mdio.c for other files */ 649int axienet_mdio_setup(struct axienet_local *lp); 650void axienet_mdio_teardown(struct axienet_local *lp); 651 652#endif /* XILINX_AXI_ENET_H */ 653