1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3  Header File to describe the DMA descriptors and related definitions.
4  This is for DWMAC100 and 1000 cores.
5
6
7  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
8*******************************************************************************/
9
10#ifndef __DESCS_H__
11#define __DESCS_H__
12
13#include <linux/bitops.h>
14
15/* Normal receive descriptor defines */
16
17/* RDES0 */
18#define	RDES0_PAYLOAD_CSUM_ERR	BIT(0)
19#define	RDES0_CRC_ERROR		BIT(1)
20#define	RDES0_DRIBBLING		BIT(2)
21#define	RDES0_MII_ERROR		BIT(3)
22#define	RDES0_RECEIVE_WATCHDOG	BIT(4)
23#define	RDES0_FRAME_TYPE	BIT(5)
24#define	RDES0_COLLISION		BIT(6)
25#define	RDES0_IPC_CSUM_ERROR	BIT(7)
26#define	RDES0_LAST_DESCRIPTOR	BIT(8)
27#define	RDES0_FIRST_DESCRIPTOR	BIT(9)
28#define	RDES0_VLAN_TAG		BIT(10)
29#define	RDES0_OVERFLOW_ERROR	BIT(11)
30#define	RDES0_LENGTH_ERROR	BIT(12)
31#define	RDES0_SA_FILTER_FAIL	BIT(13)
32#define	RDES0_DESCRIPTOR_ERROR	BIT(14)
33#define	RDES0_ERROR_SUMMARY	BIT(15)
34#define	RDES0_FRAME_LEN_MASK	GENMASK(29, 16)
35#define RDES0_FRAME_LEN_SHIFT	16
36#define	RDES0_DA_FILTER_FAIL	BIT(30)
37#define	RDES0_OWN		BIT(31)
38			/* RDES1 */
39#define	RDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)
40#define	RDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)
41#define	RDES1_BUFFER2_SIZE_SHIFT	11
42#define	RDES1_SECOND_ADDRESS_CHAINED	BIT(24)
43#define	RDES1_END_RING			BIT(25)
44#define	RDES1_DISABLE_IC		BIT(31)
45
46/* Enhanced receive descriptor defines */
47
48/* RDES0 (similar to normal RDES) */
49#define	 ERDES0_RX_MAC_ADDR	BIT(0)
50
51/* RDES1: completely differ from normal desc definitions */
52#define	ERDES1_BUFFER1_SIZE_MASK	GENMASK(12, 0)
53#define	ERDES1_SECOND_ADDRESS_CHAINED	BIT(14)
54#define	ERDES1_END_RING			BIT(15)
55#define	ERDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)
56#define ERDES1_BUFFER2_SIZE_SHIFT	16
57#define	ERDES1_DISABLE_IC		BIT(31)
58
59/* Normal transmit descriptor defines */
60/* TDES0 */
61#define	TDES0_DEFERRED			BIT(0)
62#define	TDES0_UNDERFLOW_ERROR		BIT(1)
63#define	TDES0_EXCESSIVE_DEFERRAL	BIT(2)
64#define	TDES0_COLLISION_COUNT_MASK	GENMASK(6, 3)
65#define	TDES0_VLAN_FRAME		BIT(7)
66#define	TDES0_EXCESSIVE_COLLISIONS	BIT(8)
67#define	TDES0_LATE_COLLISION		BIT(9)
68#define	TDES0_NO_CARRIER		BIT(10)
69#define	TDES0_LOSS_CARRIER		BIT(11)
70#define	TDES0_PAYLOAD_ERROR		BIT(12)
71#define	TDES0_FRAME_FLUSHED		BIT(13)
72#define	TDES0_JABBER_TIMEOUT		BIT(14)
73#define	TDES0_ERROR_SUMMARY		BIT(15)
74#define	TDES0_IP_HEADER_ERROR		BIT(16)
75#define	TDES0_TIME_STAMP_STATUS		BIT(17)
76#define	TDES0_OWN			((u32)BIT(31))	/* silence sparse */
77/* TDES1 */
78#define	TDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)
79#define	TDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)
80#define	TDES1_BUFFER2_SIZE_SHIFT	11
81#define	TDES1_TIME_STAMP_ENABLE		BIT(22)
82#define	TDES1_DISABLE_PADDING		BIT(23)
83#define	TDES1_SECOND_ADDRESS_CHAINED	BIT(24)
84#define	TDES1_END_RING			BIT(25)
85#define	TDES1_CRC_DISABLE		BIT(26)
86#define	TDES1_CHECKSUM_INSERTION_MASK	GENMASK(28, 27)
87#define	TDES1_CHECKSUM_INSERTION_SHIFT	27
88#define	TDES1_FIRST_SEGMENT		BIT(29)
89#define	TDES1_LAST_SEGMENT		BIT(30)
90#define	TDES1_INTERRUPT			BIT(31)
91
92/* Enhanced transmit descriptor defines */
93/* TDES0 */
94#define	ETDES0_DEFERRED			BIT(0)
95#define	ETDES0_UNDERFLOW_ERROR		BIT(1)
96#define	ETDES0_EXCESSIVE_DEFERRAL	BIT(2)
97#define	ETDES0_COLLISION_COUNT_MASK	GENMASK(6, 3)
98#define	ETDES0_VLAN_FRAME		BIT(7)
99#define	ETDES0_EXCESSIVE_COLLISIONS	BIT(8)
100#define	ETDES0_LATE_COLLISION		BIT(9)
101#define	ETDES0_NO_CARRIER		BIT(10)
102#define	ETDES0_LOSS_CARRIER		BIT(11)
103#define	ETDES0_PAYLOAD_ERROR		BIT(12)
104#define	ETDES0_FRAME_FLUSHED		BIT(13)
105#define	ETDES0_JABBER_TIMEOUT		BIT(14)
106#define	ETDES0_ERROR_SUMMARY		BIT(15)
107#define	ETDES0_IP_HEADER_ERROR		BIT(16)
108#define	ETDES0_TIME_STAMP_STATUS	BIT(17)
109#define	ETDES0_SECOND_ADDRESS_CHAINED	BIT(20)
110#define	ETDES0_END_RING			BIT(21)
111#define	ETDES0_CHECKSUM_INSERTION_MASK	GENMASK(23, 22)
112#define	ETDES0_CHECKSUM_INSERTION_SHIFT	22
113#define	ETDES0_TIME_STAMP_ENABLE	BIT(25)
114#define	ETDES0_DISABLE_PADDING		BIT(26)
115#define	ETDES0_CRC_DISABLE		BIT(27)
116#define	ETDES0_FIRST_SEGMENT		BIT(28)
117#define	ETDES0_LAST_SEGMENT		BIT(29)
118#define	ETDES0_INTERRUPT		BIT(30)
119#define	ETDES0_OWN			((u32)BIT(31))	/* silence sparse */
120/* TDES1 */
121#define	ETDES1_BUFFER1_SIZE_MASK	GENMASK(12, 0)
122#define	ETDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)
123#define	ETDES1_BUFFER2_SIZE_SHIFT	16
124
125/* Extended Receive descriptor definitions */
126#define	ERDES4_IP_PAYLOAD_TYPE_MASK	GENMASK(6, 2)
127#define	ERDES4_IP_HDR_ERR		BIT(3)
128#define	ERDES4_IP_PAYLOAD_ERR		BIT(4)
129#define	ERDES4_IP_CSUM_BYPASSED		BIT(5)
130#define	ERDES4_IPV4_PKT_RCVD		BIT(6)
131#define	ERDES4_IPV6_PKT_RCVD		BIT(7)
132#define	ERDES4_MSG_TYPE_MASK		GENMASK(11, 8)
133#define	ERDES4_PTP_FRAME_TYPE		BIT(12)
134#define	ERDES4_PTP_VER			BIT(13)
135#define	ERDES4_TIMESTAMP_DROPPED	BIT(14)
136#define	ERDES4_AV_PKT_RCVD		BIT(16)
137#define	ERDES4_AV_TAGGED_PKT_RCVD	BIT(17)
138#define	ERDES4_VLAN_TAG_PRI_VAL_MASK	GENMASK(20, 18)
139#define	ERDES4_L3_FILTER_MATCH		BIT(24)
140#define	ERDES4_L4_FILTER_MATCH		BIT(25)
141#define	ERDES4_L3_L4_FILT_NO_MATCH_MASK	GENMASK(27, 26)
142
143/* Extended RDES4 message type definitions */
144#define RDES_EXT_NO_PTP			0x0
145#define RDES_EXT_SYNC			0x1
146#define RDES_EXT_FOLLOW_UP		0x2
147#define RDES_EXT_DELAY_REQ		0x3
148#define RDES_EXT_DELAY_RESP		0x4
149#define RDES_EXT_PDELAY_REQ		0x5
150#define RDES_EXT_PDELAY_RESP		0x6
151#define RDES_EXT_PDELAY_FOLLOW_UP	0x7
152#define RDES_PTP_ANNOUNCE		0x8
153#define RDES_PTP_MANAGEMENT		0x9
154#define RDES_PTP_SIGNALING		0xa
155#define RDES_PTP_PKT_RESERVED_TYPE	0xf
156
157/* Basic descriptor structure for normal and alternate descriptors */
158struct dma_desc {
159	__le32 des0;
160	__le32 des1;
161	__le32 des2;
162	__le32 des3;
163};
164
165/* Extended descriptor structure (e.g. >= databook 3.50a) */
166struct dma_extended_desc {
167	struct dma_desc basic;	/* Basic descriptors */
168	__le32 des4;	/* Extended Status */
169	__le32 des5;	/* Reserved */
170	__le32 des6;	/* Tx/Rx Timestamp Low */
171	__le32 des7;	/* Tx/Rx Timestamp High */
172};
173
174/* Enhanced descriptor for TBS */
175struct dma_edesc {
176	__le32 des4;
177	__le32 des5;
178	__le32 des6;
179	__le32 des7;
180	struct dma_desc basic;
181};
182
183/* Transmit checksum insertion control */
184#define	TX_CIC_FULL	3	/* Include IP header and pseudoheader */
185
186#endif /* __DESCS_H__ */
187