1139823Simp/* version dependencies have been confined to a separate file */ 26399Swollman 34074Swollman/* Tunable parameters */ 46399Swollman#define TX_RING_ENTRIES 64 /* 64-512?*/ 56399Swollman 66399Swollman#define RX_RING_ENTRIES 16 /* Do not change */ 76399Swollman/* Internal constants */ 86399Swollman#define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet)) 96399Swollman#define RX_BUFFER_SIZE 1546 /* ethenet packet size */ 106399Swollman#define METH_RX_BUFF_SIZE 4096 116399Swollman#define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */ 126399Swollman#define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */ 136399Swollman#define RX_BUCKET_SIZE 256 146399Swollman 158876Srgrimes/* For more detailed explanations of what each field menas, 166399Swollman see Nick's great comments to #defines below (or docs, if 176399Swollman you are lucky enough toget hold of them :)*/ 186399Swollman 196399Swollman/* tx status vector is written over tx command header upon 206399Swollman dma completion. */ 216399Swollman 226399Swollmantypedef struct tx_status_vector { 236399Swollman u64 sent:1; /* always set to 1...*/ 246399Swollman u64 pad0:34;/* always set to 0 */ 256399Swollman u64 flags:9; /*I'm too lazy to specify each one separately at the moment*/ 266399Swollman u64 col_retry_cnt:4; /*collision retry count*/ 276399Swollman u64 len:16; /*Transmit length in bytes*/ 284074Swollman} tx_status_vector; 294074Swollman 304074Swollman/* 314074Swollman * Each packet is 128 bytes long. 324074Swollman * It consists of header, 0-3 concatination 334074Swollman * buffer pointers and up to 120 data bytes. 344074Swollman */ 354074Swollmantypedef struct tx_packet_hdr { 364074Swollman u64 pad1:36; /*should be filled with 0 */ 374074Swollman u64 cat_ptr3_valid:1, /*Concatination pointer valid flags*/ 384074Swollman cat_ptr2_valid:1, 394074Swollman cat_ptr1_valid:1; 404074Swollman u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/ 414074Swollman u64 term_dma_flag:1; /*Terminate transmit DMA on transmit abort conditions*/ 424074Swollman u64 data_offset:7; /*Starting byte offset in ring data block*/ 43172467Ssilby u64 data_len:16; /*Length of valid data in bytes-1*/ 44172467Ssilby} tx_packet_hdr; 45172467Ssilbytypedef union tx_cat_ptr { 46189106Sbz struct { 47189106Sbz u64 pad2:16; /* should be 0 */ 484074Swollman u64 len:16; /*length of buffer data - 1*/ 494074Swollman u64 start_addr:29; /*Physical starting address*/ 504074Swollman u64 pad1:3; /* should be zero */ 5112172Sphk } form; 524074Swollman u64 raw; 534074Swollman} tx_cat_ptr; 544893Swollman 55120727Ssamtypedef struct tx_packet { 56181803Sbz union { 574074Swollman tx_packet_hdr header; 584074Swollman tx_status_vector res; 594074Swollman u64 raw; 60185571Sbz }header; 61185571Sbz union { 624074Swollman tx_cat_ptr cat_buf[3]; 634074Swollman char dt[120]; 6474454Sru } data; 65185571Sbz} tx_packet; 664074Swollman 6792723Salfredtypedef union rx_status_vector { 6812579Sbde volatile struct { 695101Swollman u64 pad1:1;/*fill it with ones*/ 704074Swollman u64 pad2:15;/*fill with 0*/ 714074Swollman u64 ip_chk_sum:16; 724074Swollman u64 seq_num:5; 734074Swollman u64 mac_addr_match:1; 744074Swollman u64 mcast_addr_match:1; 754074Swollman u64 carrier_event_seen:1; 76169454Srwatson u64 bad_packet:1; 774074Swollman u64 long_event_seen:1; 784074Swollman u64 invalid_preamble:1; 799470Swollman u64 broadcast:1; 804074Swollman u64 multicast:1; 81186119Sqingli u64 crc_error:1; 824074Swollman u64 huh:1;/*???*/ 8315652Swollman u64 rx_code_violation:1; 8415652Swollman u64 rx_len:16; 8515652Swollman } parsed; 8615652Swollman volatile u64 raw; 8715652Swollman} rx_status_vector; 8815652Swollman 8915652Swollmantypedef struct rx_packet { 9015652Swollman rx_status_vector status; 9115652Swollman u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */ 9215652Swollman u16 pad2; 9315652Swollman char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */ 9415652Swollman} rx_packet; 95122921Sandre 9615652Swollman#define TX_INFO_RPTR 0x00FF0000 9715652Swollman#define TX_INFO_WPTR 0x000000FF 9815652Swollman 9915652Swollman /* Bits in METH_MAC */ 100110656Shsu 101110656Shsu#define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */ 102110656Shsu#define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */ 1035792Swollman#define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */ 1045792Swollman /* selects ignored */ 105122921Sandre#define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */ 106122921Sandre#define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */ 1074074Swollman /* Note: when loopback is set this bit becomes collision control. Setting this bit will */ 108122922Sandre /* cause a collision to be reported. */ 10910881Swollman 1109470Swollman /* Bits 5 and 6 are used to determine the Destination address filter mode */ 111186119Sqingli#define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */ 1124074Swollman#define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */ 1134074Swollman#define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */ 1144074Swollman#define METH_PROMISC 0x60 /* 11: Promiscious mode */ 1154105Swollman 1164105Swollman#define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */ 1174105Swollman 1184074Swollman#define METH_MAC_IPG 0x1ffff00 1194074Swollman 1204074Swollman#define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8)) 1214074Swollman /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/ 1224074Swollman /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */ 1234074Swollman /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns */ 1244074Swollman /* per increment for 10BaseT */ 125120727Ssam 126110656Shsu /* Bits 15 through 21 are used to determine IPGR1 */ 127110656Shsu 1285101Swollman /* Bits 22 through 28 are used to determine IPGR2 */ 1294105Swollman 1304074Swollman#define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */ 1314074Swollman /* 000: Initial revision */ 1324074Swollman /* 001: First revision, Improved TX concatenation */ 1334074Swollman 1344074Swollman 135185088Szec/* DMA control bits */ 136185088Szec#define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */ 137185088Szec#define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */ 138185088Szec 139185088Szec#define METH_DMA_TX_EN BIT(1) /* enable TX DMA */ 140185088Szec#define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */ 141183550Szec#define METH_DMA_RX_EN BIT(15) /* Enable RX */ 142183550Szec#define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */ 143183550Szec 144110656Shsu/* RX FIFO MCL Info bits */ 145183550Szec#define METH_RX_FIFO_WPTR(x) (((x)>>16)&0xf) 146183550Szec#define METH_RX_FIFO_RPTR(x) (((x)>>8)&0xf) 14746381Sbillf#define METH_RX_FIFO_DEPTH(x) ((x)&0x1f) 1484105Swollman 149183550Szec/* RX status bits */ 150183550Szec 151183550Szec#define METH_RX_ST_VALID BIT(63) 152110656Shsu#define METH_RX_ST_RCV_CODE_VIOLATION BIT(16) 1534074Swollman#define METH_RX_ST_DRBL_NBL BIT(17) 1545792Swollman#define METH_RX_ST_CRC_ERR BIT(18) 1554074Swollman#define METH_RX_ST_MCAST_PKT BIT(19) 1564074Swollman#define METH_RX_ST_BCAST_PKT BIT(20) 1574074Swollman#define METH_RX_ST_INV_PREAMBLE_CTX BIT(21) 1584074Swollman#define METH_RX_ST_LONG_EVT_SEEN BIT(22) 1594074Swollman#define METH_RX_ST_BAD_PACKET BIT(23) 160183550Szec#define METH_RX_ST_CARRIER_EVT_SEEN BIT(24) 1614074Swollman#define METH_RX_ST_MCAST_FILTER_MATCH BIT(25) 1628876Srgrimes#define METH_RX_ST_PHYS_ADDR_MATCH BIT(26) 163120727Ssam 164120727Ssam#define METH_RX_STATUS_ERRORS \ 165110656Shsu ( \ 166110656Shsu METH_RX_ST_RCV_CODE_VIOLATION| \ 1675792Swollman METH_RX_ST_CRC_ERR| \ 168138499Sru METH_RX_ST_INV_PREAMBLE_CTX| \ 1694105Swollman METH_RX_ST_LONG_EVT_SEEN| \ 1704074Swollman METH_RX_ST_BAD_PACKET| \ 171186119Sqingli METH_RX_ST_CARRIER_EVT_SEEN \ 172138499Sru ) 173138499Sru /* Bits in METH_INT */ 1746399Swollman /* Write _1_ to corresponding bit to clear */ 1756399Swollman#define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */ 1766399Swollman#define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */ 1776399Swollman /* 1: A TX message had the INT request bit set, the packet has been sent. */ 178181803Sbz#define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ 1796399Swollman#define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ 180181803Sbz /* 1: A memory error occurred during DMA, DMA stopped, Fatal */ 1816399Swollman#define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ 182121770Ssam#define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ 1836399Swollman#define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ 1844074Swollman#define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */ 1854074Swollman 1864893Swollman/*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */ 1874893Swollman#define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/ 1885101Swollman 1894893Swollman /* Bits 13 through 15 are always 0. */ 1904893Swollman 1916400Swollman#define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */ 1924893Swollman 1934893Swollman#define METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */ 1944893Swollman 1954074Swollman /* top of the queue */ 1965101Swollman 1976400Swollman#define METH_INT_ERROR (METH_INT_TX_LINK_FAIL| \ 1986400Swollman METH_INT_MEM_ERROR| \ 1994074Swollman METH_INT_TX_ABORT| \ 2004893Swollman METH_INT_RX_OVERFLOW| \ 2014893Swollman METH_INT_RX_UNDERFLOW) 2024074Swollman 203183550Szec#define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */ 2044893Swollman 2054893Swollman/* TX status bits */ 2064893Swollman#define METH_TX_ST_DONE BIT(63) /* TX complete */ 2074893Swollman#define METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */ 208188962Srwatson#define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */ 209188962Srwatson#define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */ 210110656Shsu#define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */ 2114893Swollman#define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */ 2124893Swollman#define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */ 213150351Sandre 214110656Shsu 2157170Sdg/* Tx command header bits */ 2164893Swollman#define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */ 217178888Sjulian 2184893Swollman/* Phy MDIO interface busy flag */ 2194893Swollman#define MDIO_BUSY BIT(16) 220188962Srwatson#define MDIO_DATA_MASK 0xFFFF 221188962Srwatson/* PHY defines */ 222110656Shsu#define PHY_QS6612X 0x0181441 /* Quality TX */ 2236568Sdg#define PHY_ICS1889 0x0015F41 /* ICS FX */ 2244893Swollman#define PHY_ICS1890 0x0015F42 /* ICS TX */ 2254893Swollman#define PHY_DP83840 0x20005C0 /* National TX */ 2264893Swollman 2274893Swollman#define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1) 228110656Shsu