1/* SPDX-License-Identifier: GPL-2.0-only */ 2/**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2005-2006 Fen Systems Ltd. 5 * Copyright 2006-2013 Solarflare Communications Inc. 6 * Copyright 2019-2020 Xilinx Inc. 7 */ 8 9#ifndef EFX_NIC_COMMON_H 10#define EFX_NIC_COMMON_H 11 12#include "net_driver.h" 13#include "efx_common.h" 14#include "mcdi.h" 15#include "ptp.h" 16 17enum { 18 /* Revisions 0-3 were Falcon A0, A1, B0 and Siena respectively. 19 * They are not supported by this driver but these revision numbers 20 * form part of the ethtool API for register dumping. 21 */ 22 EFX_REV_HUNT_A0 = 4, 23 EFX_REV_EF100 = 5, 24}; 25 26static inline int efx_nic_rev(struct efx_nic *efx) 27{ 28 return efx->type->revision; 29} 30 31/* Read the current event from the event queue */ 32static inline efx_qword_t *efx_event(struct efx_channel *channel, 33 unsigned int index) 34{ 35 return ((efx_qword_t *)(channel->eventq.addr)) + 36 (index & channel->eventq_mask); 37} 38 39/* See if an event is present 40 * 41 * We check both the high and low dword of the event for all ones. We 42 * wrote all ones when we cleared the event, and no valid event can 43 * have all ones in either its high or low dwords. This approach is 44 * robust against reordering. 45 * 46 * Note that using a single 64-bit comparison is incorrect; even 47 * though the CPU read will be atomic, the DMA write may not be. 48 */ 49static inline int efx_event_present(efx_qword_t *event) 50{ 51 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 52 EFX_DWORD_IS_ALL_ONES(event->dword[1])); 53} 54 55/* Returns a pointer to the specified transmit descriptor in the TX 56 * descriptor queue belonging to the specified channel. 57 */ 58static inline efx_qword_t * 59efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 60{ 61 return ((efx_qword_t *)(tx_queue->txd.addr)) + index; 62} 63 64/* Report whether this TX queue would be empty for the given write_count. 65 * May return false negative. 66 */ 67static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, unsigned int write_count) 68{ 69 unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count); 70 71 if (empty_read_count == 0) 72 return false; 73 74 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 75} 76 77int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 78 bool *data_mapped); 79 80/* Decide whether to push a TX descriptor to the NIC vs merely writing 81 * the doorbell. This can reduce latency when we are adding a single 82 * descriptor to an empty queue, but is otherwise pointless. 83 * We use the write_count used for the last doorbell push, to get the 84 * NIC's view of the tx queue. 85 */ 86static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, 87 unsigned int write_count) 88{ 89 bool was_empty = efx_nic_tx_is_empty(tx_queue, write_count); 90 91 tx_queue->empty_read_count = 0; 92 return was_empty && tx_queue->write_count - write_count == 1; 93} 94 95/* Returns a pointer to the specified descriptor in the RX descriptor queue */ 96static inline efx_qword_t * 97efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 98{ 99 return ((efx_qword_t *)(rx_queue->rxd.addr)) + index; 100} 101 102/* Alignment of PCIe DMA boundaries (4KB) */ 103#define EFX_PAGE_SIZE 4096 104/* Size and alignment of buffer table entries (same) */ 105#define EFX_BUF_SIZE EFX_PAGE_SIZE 106 107/* NIC-generic software stats */ 108enum { 109 GENERIC_STAT_rx_noskb_drops, 110 GENERIC_STAT_rx_nodesc_trunc, 111 GENERIC_STAT_COUNT 112}; 113 114#define EFX_GENERIC_SW_STAT(ext_name) \ 115 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 116 117/* TX data path */ 118static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 119{ 120 return tx_queue->efx->type->tx_probe(tx_queue); 121} 122static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 123{ 124 tx_queue->efx->type->tx_init(tx_queue); 125} 126static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 127{ 128 if (tx_queue->efx->type->tx_remove) 129 tx_queue->efx->type->tx_remove(tx_queue); 130} 131static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 132{ 133 tx_queue->efx->type->tx_write(tx_queue); 134} 135 136/* RX data path */ 137static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 138{ 139 return rx_queue->efx->type->rx_probe(rx_queue); 140} 141static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 142{ 143 rx_queue->efx->type->rx_init(rx_queue); 144} 145static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 146{ 147 rx_queue->efx->type->rx_remove(rx_queue); 148} 149static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 150{ 151 rx_queue->efx->type->rx_write(rx_queue); 152} 153static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) 154{ 155 rx_queue->efx->type->rx_defer_refill(rx_queue); 156} 157 158/* Event data path */ 159static inline int efx_nic_probe_eventq(struct efx_channel *channel) 160{ 161 return channel->efx->type->ev_probe(channel); 162} 163static inline int efx_nic_init_eventq(struct efx_channel *channel) 164{ 165 return channel->efx->type->ev_init(channel); 166} 167static inline void efx_nic_fini_eventq(struct efx_channel *channel) 168{ 169 channel->efx->type->ev_fini(channel); 170} 171static inline void efx_nic_remove_eventq(struct efx_channel *channel) 172{ 173 channel->efx->type->ev_remove(channel); 174} 175static inline int 176efx_nic_process_eventq(struct efx_channel *channel, int quota) 177{ 178 return channel->efx->type->ev_process(channel, quota); 179} 180static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) 181{ 182 channel->efx->type->ev_read_ack(channel); 183} 184 185void efx_nic_event_test_start(struct efx_channel *channel); 186 187bool efx_nic_event_present(struct efx_channel *channel); 188 189static inline void efx_sensor_event(struct efx_nic *efx, efx_qword_t *ev) 190{ 191 if (efx->type->sensor_event) 192 efx->type->sensor_event(efx, ev); 193} 194 195static inline unsigned int efx_rx_recycle_ring_size(const struct efx_nic *efx) 196{ 197 return efx->type->rx_recycle_ring_size(efx); 198} 199 200/* Some statistics are computed as A - B where A and B each increase 201 * linearly with some hardware counter(s) and the counters are read 202 * asynchronously. If the counters contributing to B are always read 203 * after those contributing to A, the computed value may be lower than 204 * the true value by some variable amount, and may decrease between 205 * subsequent computations. 206 * 207 * We should never allow statistics to decrease or to exceed the true 208 * value. Since the computed value will never be greater than the 209 * true value, we can achieve this by only storing the computed value 210 * when it increases. 211 */ 212static inline void efx_update_diff_stat(u64 *stat, u64 diff) 213{ 214 if ((s64)(diff - *stat) > 0) 215 *stat = diff; 216} 217 218/* Interrupts */ 219int efx_nic_init_interrupt(struct efx_nic *efx); 220int efx_nic_irq_test_start(struct efx_nic *efx); 221void efx_nic_fini_interrupt(struct efx_nic *efx); 222 223static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) 224{ 225 return READ_ONCE(channel->event_test_cpu); 226} 227static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) 228{ 229 return READ_ONCE(efx->last_irq_cpu); 230} 231 232/* Global Resources */ 233int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 234 unsigned int len, gfp_t gfp_flags); 235void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); 236 237size_t efx_nic_get_regs_len(struct efx_nic *efx); 238void efx_nic_get_regs(struct efx_nic *efx, void *buf); 239 240#define EFX_MC_STATS_GENERATION_INVALID ((__force __le64)(-1)) 241 242size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 243 const unsigned long *mask, u8 *names); 244int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest); 245void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 246 const unsigned long *mask, u64 *stats, 247 const void *dma_buf, bool accumulate); 248void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); 249static inline size_t efx_nic_update_stats_atomic(struct efx_nic *efx, u64 *full_stats, 250 struct rtnl_link_stats64 *core_stats) 251{ 252 if (efx->type->update_stats_atomic) 253 return efx->type->update_stats_atomic(efx, full_stats, core_stats); 254 return efx->type->update_stats(efx, full_stats, core_stats); 255} 256 257#define EFX_MAX_FLUSH_TIME 5000 258 259#endif /* EFX_NIC_COMMON_H */ 260