1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2/*
3 *   Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
4 *   Copyright (c) 2014, I2SE GmbH
5 */
6
7/*   Qualcomm Atheros SPI register definition.
8 *
9 *   This module is designed to define the Qualcomm Atheros SPI register
10 *   placeholders;
11 */
12
13#ifndef _QCA_SPI_H
14#define _QCA_SPI_H
15
16#include <linux/netdevice.h>
17#include <linux/sched.h>
18#include <linux/skbuff.h>
19#include <linux/spi/spi.h>
20#include <linux/types.h>
21
22#include "qca_7k_common.h"
23
24#define QCASPI_DRV_VERSION "0.2.7-i"
25#define QCASPI_DRV_NAME    "qcaspi"
26
27#define QCASPI_GOOD_SIGNATURE 0xAA55
28
29#define QCASPI_TX_RING_MAX_LEN 10
30#define QCASPI_TX_RING_MIN_LEN 2
31#define QCASPI_RX_MAX_FRAMES 4
32
33/* sync related constants */
34#define QCASPI_SYNC_UNKNOWN 0
35#define QCASPI_SYNC_RESET   1
36#define QCASPI_SYNC_READY   2
37
38#define QCASPI_RESET_TIMEOUT 10
39
40/* sync events */
41#define QCASPI_EVENT_UPDATE 0
42#define QCASPI_EVENT_CPUON  1
43
44struct tx_ring {
45	struct sk_buff *skb[QCASPI_TX_RING_MAX_LEN];
46	u16 head;
47	u16 tail;
48	u16 size;
49	u16 count;
50};
51
52struct qcaspi_stats {
53	u64 trig_reset;
54	u64 device_reset;
55	u64 reset_timeout;
56	u64 read_err;
57	u64 write_err;
58	u64 read_buf_err;
59	u64 write_buf_err;
60	u64 out_of_mem;
61	u64 write_buf_miss;
62	u64 ring_full;
63	u64 spi_err;
64	u64 write_verify_failed;
65	u64 buf_avail_err;
66	u64 bad_signature;
67};
68
69struct qcaspi {
70	struct net_device *net_dev;
71	struct spi_device *spi_dev;
72	struct task_struct *spi_thread;
73
74	struct tx_ring txr;
75	struct qcaspi_stats stats;
76
77	u8 *rx_buffer;
78	u32 buffer_size;
79	u8 sync;
80
81	struct qcafrm_handle frm_handle;
82	struct sk_buff *rx_skb;
83
84	unsigned int intr_req;
85	unsigned int intr_svc;
86	u16 reset_count;
87
88#ifdef CONFIG_DEBUG_FS
89	struct dentry *device_root;
90#endif
91
92	/* user configurable options */
93	u32 clkspeed;
94	u8 legacy_mode;
95	u16 burst_len;
96};
97
98#endif /* _QCA_SPI_H */
99