11573Srgrimes/* SPDX-License-Identifier: GPL-2.0 */ 21573Srgrimes/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 31573Srgrimes 41573Srgrimes#ifndef _IONIC_DEV_H_ 51573Srgrimes#define _IONIC_DEV_H_ 61573Srgrimes 71573Srgrimes#include <linux/atomic.h> 81573Srgrimes#include <linux/mutex.h> 91573Srgrimes#include <linux/workqueue.h> 101573Srgrimes#include <linux/skbuff.h> 111573Srgrimes#include <linux/bpf_trace.h> 121573Srgrimes 131573Srgrimes#include "ionic_if.h" 141573Srgrimes#include "ionic_regs.h" 151573Srgrimes 161573Srgrimes#define IONIC_MAX_TX_DESC 8192 171573Srgrimes#define IONIC_MAX_RX_DESC 16384 181573Srgrimes#define IONIC_MIN_TXRX_DESC 64 191573Srgrimes#define IONIC_DEF_TXRX_DESC 1024 201573Srgrimes#define IONIC_RX_FILL_THRESHOLD 16 211573Srgrimes#define IONIC_RX_FILL_DIV 8 221573Srgrimes#define IONIC_TSO_DESCS_NEEDED 44 /* 64K TSO @1500B */ 231573Srgrimes#define IONIC_LIFS_MAX 1024 241573Srgrimes#define IONIC_WATCHDOG_SECS 5 251573Srgrimes#define IONIC_ITR_COAL_USEC_DEFAULT 64 261573Srgrimes 271573Srgrimes#define IONIC_DEV_CMD_REG_VERSION 1 281573Srgrimes#define IONIC_DEV_INFO_REG_COUNT 32 291573Srgrimes#define IONIC_DEV_CMD_REG_COUNT 32 301573Srgrimes 311573Srgrimes#define IONIC_NAPI_DEADLINE (HZ / 200) /* 5ms */ 321573Srgrimes#define IONIC_ADMIN_DOORBELL_DEADLINE (HZ / 2) /* 500ms */ 331573Srgrimes#define IONIC_TX_DOORBELL_DEADLINE (HZ / 100) /* 10ms */ 341573Srgrimes#define IONIC_RX_MIN_DOORBELL_DEADLINE (HZ / 100) /* 10ms */ 351573Srgrimes#define IONIC_RX_MAX_DOORBELL_DEADLINE (HZ * 5) /* 5s */ 361573Srgrimes 371573Srgrimesstruct ionic_dev_bar { 3851549Sru void __iomem *vaddr; 391573Srgrimes phys_addr_t bus_addr; 4051549Sru unsigned long len; 4151549Sru int res_index; 4251549Sru}; 431573Srgrimes 441573Srgrimes#ifndef __CHECKER__ 451573Srgrimes/* Registers */ 461573Srgrimesstatic_assert(sizeof(struct ionic_intr) == 32); 471573Srgrimes 481573Srgrimesstatic_assert(sizeof(struct ionic_doorbell) == 8); 491573Srgrimesstatic_assert(sizeof(struct ionic_intr_status) == 8); 501573Srgrimesstatic_assert(sizeof(union ionic_dev_regs) == 4096); 511573Srgrimesstatic_assert(sizeof(union ionic_dev_info_regs) == 2048); 521573Srgrimesstatic_assert(sizeof(union ionic_dev_cmd_regs) == 2048); 531573Srgrimesstatic_assert(sizeof(struct ionic_lif_stats) == 1024); 541573Srgrimes 551573Srgrimesstatic_assert(sizeof(struct ionic_admin_cmd) == 64); 561573Srgrimesstatic_assert(sizeof(struct ionic_admin_comp) == 16); 571573Srgrimesstatic_assert(sizeof(struct ionic_nop_cmd) == 64); 581573Srgrimesstatic_assert(sizeof(struct ionic_nop_comp) == 16); 591573Srgrimes 601573Srgrimes/* Device commands */ 611573Srgrimesstatic_assert(sizeof(struct ionic_dev_identify_cmd) == 64); 621573Srgrimesstatic_assert(sizeof(struct ionic_dev_identify_comp) == 16); 631573Srgrimesstatic_assert(sizeof(struct ionic_dev_init_cmd) == 64); 641573Srgrimesstatic_assert(sizeof(struct ionic_dev_init_comp) == 16); 651573Srgrimesstatic_assert(sizeof(struct ionic_dev_reset_cmd) == 64); 661573Srgrimesstatic_assert(sizeof(struct ionic_dev_reset_comp) == 16); 671573Srgrimesstatic_assert(sizeof(struct ionic_dev_getattr_cmd) == 64); 681573Srgrimesstatic_assert(sizeof(struct ionic_dev_getattr_comp) == 16); 691573Srgrimesstatic_assert(sizeof(struct ionic_dev_setattr_cmd) == 64); 701573Srgrimesstatic_assert(sizeof(struct ionic_dev_setattr_comp) == 16); 711573Srgrimesstatic_assert(sizeof(struct ionic_lif_setphc_cmd) == 64); 721573Srgrimes 731573Srgrimes/* Port commands */ 7411659Sphkstatic_assert(sizeof(struct ionic_port_identify_cmd) == 64); 751573Srgrimesstatic_assert(sizeof(struct ionic_port_identify_comp) == 16); 761573Srgrimesstatic_assert(sizeof(struct ionic_port_init_cmd) == 64); 771573Srgrimesstatic_assert(sizeof(struct ionic_port_init_comp) == 16); 781573Srgrimesstatic_assert(sizeof(struct ionic_port_reset_cmd) == 64); 791573Srgrimesstatic_assert(sizeof(struct ionic_port_reset_comp) == 16); 801573Srgrimesstatic_assert(sizeof(struct ionic_port_getattr_cmd) == 64); 811573Srgrimesstatic_assert(sizeof(struct ionic_port_getattr_comp) == 16); 821573Srgrimesstatic_assert(sizeof(struct ionic_port_setattr_cmd) == 64); 831573Srgrimesstatic_assert(sizeof(struct ionic_port_setattr_comp) == 16); 841573Srgrimes 851573Srgrimes/* LIF commands */ 861573Srgrimesstatic_assert(sizeof(struct ionic_lif_init_cmd) == 64); 871573Srgrimesstatic_assert(sizeof(struct ionic_lif_init_comp) == 16); 881573Srgrimesstatic_assert(sizeof(struct ionic_lif_reset_cmd) == 64); 891573Srgrimesstatic_assert(sizeof(ionic_lif_reset_comp) == 16); 901573Srgrimesstatic_assert(sizeof(struct ionic_lif_getattr_cmd) == 64); 911573Srgrimesstatic_assert(sizeof(struct ionic_lif_getattr_comp) == 16); 921573Srgrimesstatic_assert(sizeof(struct ionic_lif_setattr_cmd) == 64); 931573Srgrimesstatic_assert(sizeof(struct ionic_lif_setattr_comp) == 16); 941573Srgrimes 951573Srgrimesstatic_assert(sizeof(struct ionic_q_init_cmd) == 64); 961573Srgrimesstatic_assert(sizeof(struct ionic_q_init_comp) == 16); 971573Srgrimesstatic_assert(sizeof(struct ionic_q_control_cmd) == 64); 981573Srgrimesstatic_assert(sizeof(ionic_q_control_comp) == 16); 991573Srgrimesstatic_assert(sizeof(struct ionic_q_identify_cmd) == 64); 1001573Srgrimesstatic_assert(sizeof(struct ionic_q_identify_comp) == 16); 1011573Srgrimes 1021573Srgrimesstatic_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64); 1031573Srgrimesstatic_assert(sizeof(ionic_rx_mode_set_comp) == 16); 1041573Srgrimesstatic_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64); 1051573Srgrimesstatic_assert(sizeof(struct ionic_rx_filter_add_comp) == 16); 1061573Srgrimesstatic_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64); 1071573Srgrimesstatic_assert(sizeof(ionic_rx_filter_del_comp) == 16); 1081573Srgrimes 1091573Srgrimes/* RDMA commands */ 1101573Srgrimesstatic_assert(sizeof(struct ionic_rdma_reset_cmd) == 64); 1111573Srgrimesstatic_assert(sizeof(struct ionic_rdma_queue_cmd) == 64); 1121573Srgrimes 1131573Srgrimes/* Events */ 1141573Srgrimesstatic_assert(sizeof(struct ionic_notifyq_cmd) == 4); 1151573Srgrimesstatic_assert(sizeof(union ionic_notifyq_comp) == 64); 1161573Srgrimesstatic_assert(sizeof(struct ionic_notifyq_event) == 64); 1171573Srgrimesstatic_assert(sizeof(struct ionic_link_change_event) == 64); 1181573Srgrimesstatic_assert(sizeof(struct ionic_reset_event) == 64); 1191573Srgrimesstatic_assert(sizeof(struct ionic_heartbeat_event) == 64); 1201573Srgrimesstatic_assert(sizeof(struct ionic_log_event) == 64); 1211573Srgrimes 1221573Srgrimes/* I/O */ 1231573Srgrimesstatic_assert(sizeof(struct ionic_txq_desc) == 16); 1241573Srgrimesstatic_assert(sizeof(struct ionic_txq_sg_desc) == 128); 1251573Srgrimesstatic_assert(sizeof(struct ionic_txq_sg_desc_v1) == 256); 1261573Srgrimesstatic_assert(sizeof(struct ionic_txq_comp) == 16); 1271573Srgrimes 1281573Srgrimesstatic_assert(sizeof(struct ionic_rxq_desc) == 16); 1291573Srgrimesstatic_assert(sizeof(struct ionic_rxq_sg_desc) == 128); 1301573Srgrimesstatic_assert(sizeof(struct ionic_rxq_comp) == 16); 1311573Srgrimesstatic_assert(sizeof(struct ionic_rxq_comp) == sizeof(struct ionic_txq_comp)); 1321573Srgrimes 1331573Srgrimes/* SR/IOV */ 1341573Srgrimesstatic_assert(sizeof(struct ionic_vf_setattr_cmd) == 64); 1351573Srgrimesstatic_assert(sizeof(struct ionic_vf_setattr_comp) == 16); 1361573Srgrimesstatic_assert(sizeof(struct ionic_vf_getattr_cmd) == 64); 1371573Srgrimesstatic_assert(sizeof(struct ionic_vf_getattr_comp) == 16); 1381573Srgrimesstatic_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64); 1391573Srgrimesstatic_assert(sizeof(struct ionic_vf_ctrl_comp) == 16); 1401573Srgrimes#endif /* __CHECKER__ */ 1411573Srgrimes 1421573Srgrimesstruct ionic_devinfo { 1431573Srgrimes u8 asic_type; 1441573Srgrimes u8 asic_rev; 1451573Srgrimes char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1]; 1461573Srgrimes char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1]; 1471573Srgrimes}; 1481573Srgrimes 1491573Srgrimesstruct ionic_dev { 1501573Srgrimes union ionic_dev_info_regs __iomem *dev_info_regs; 1511573Srgrimes union ionic_dev_cmd_regs __iomem *dev_cmd_regs; 1521573Srgrimes struct ionic_hwstamp_regs __iomem *hwstamp_regs; 1531573Srgrimes 1541573Srgrimes atomic_long_t last_check_time; 1551573Srgrimes unsigned long last_hb_time; 1561573Srgrimes u32 last_fw_hb; 1571573Srgrimes bool fw_hb_ready; 1581573Srgrimes bool fw_status_ready; 1591573Srgrimes u8 fw_generation; 1601573Srgrimes u8 opcode; 1611573Srgrimes 1621573Srgrimes u64 __iomem *db_pages; 1631573Srgrimes dma_addr_t phy_db_pages; 1641573Srgrimes 1651573Srgrimes struct ionic_intr __iomem *intr_ctrl; 1661573Srgrimes u64 __iomem *intr_status; 1671573Srgrimes 1681573Srgrimes struct mutex cmb_inuse_lock; /* for cmb_inuse */ 1691573Srgrimes unsigned long *cmb_inuse; 1701573Srgrimes dma_addr_t phy_cmb_pages; 1711573Srgrimes u32 cmb_npages; 1721573Srgrimes 1731573Srgrimes u32 port_info_sz; 1741573Srgrimes struct ionic_port_info *port_info; 1751573Srgrimes dma_addr_t port_info_pa; 1761573Srgrimes 1771573Srgrimes struct ionic_devinfo dev_info; 1781573Srgrimes}; 17911659Sphk 1801573Srgrimesstruct ionic_queue; 1811573Srgrimesstruct ionic_qcq; 1821573Srgrimes 1831573Srgrimes#define IONIC_MAX_BUF_LEN ((u16)-1) 1841573Srgrimes#define IONIC_PAGE_SIZE PAGE_SIZE 1851573Srgrimes#define IONIC_PAGE_SPLIT_SZ (PAGE_SIZE / 2) 1861573Srgrimes#define IONIC_PAGE_GFP_MASK (GFP_ATOMIC | __GFP_NOWARN |\ 1871573Srgrimes __GFP_COMP | __GFP_MEMALLOC) 1881573Srgrimes 1891573Srgrimes#define IONIC_XDP_MAX_LINEAR_MTU (IONIC_PAGE_SIZE - \ 1901573Srgrimes (VLAN_ETH_HLEN + \ 1911573Srgrimes XDP_PACKET_HEADROOM + \ 1921573Srgrimes SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))) 1931573Srgrimes 1941573Srgrimesstruct ionic_buf_info { 1951573Srgrimes struct page *page; 1961573Srgrimes dma_addr_t dma_addr; 1978870Srgrimes u32 page_offset; 1981573Srgrimes u32 len; 1991573Srgrimes}; 2001573Srgrimes 2011573Srgrimes#define IONIC_TX_MAX_FRAGS (1 + IONIC_TX_MAX_SG_ELEMS_V1) 2021573Srgrimes#define IONIC_RX_MAX_FRAGS (1 + IONIC_RX_MAX_SG_ELEMS) 2031573Srgrimes 2041573Srgrimesstruct ionic_tx_desc_info { 2051573Srgrimes unsigned int bytes; 2061573Srgrimes unsigned int nbufs; 2071573Srgrimes struct sk_buff *skb; 2081573Srgrimes struct xdp_frame *xdpf; 2091573Srgrimes enum xdp_action act; 2101573Srgrimes struct ionic_buf_info bufs[MAX_SKB_FRAGS + 1]; 2111573Srgrimes}; 2121573Srgrimes 2131573Srgrimesstruct ionic_rx_desc_info { 2141573Srgrimes unsigned int nbufs; 2151573Srgrimes struct ionic_buf_info bufs[IONIC_RX_MAX_FRAGS]; 2161573Srgrimes}; 2171573Srgrimes 2181573Srgrimesstruct ionic_admin_desc_info { 2191573Srgrimes void *ctx; 2201573Srgrimes}; 2211573Srgrimes 2221573Srgrimes#define IONIC_QUEUE_NAME_MAX_SZ 16 2231573Srgrimes 2241573Srgrimesstruct ionic_queue { 2251573Srgrimes struct device *dev; 2261573Srgrimes struct ionic_lif *lif; 2271573Srgrimes union { 2281573Srgrimes void *info; 2291573Srgrimes struct ionic_tx_desc_info *tx_info; 2301573Srgrimes struct ionic_rx_desc_info *rx_info; 2311573Srgrimes struct ionic_admin_desc_info *admin_info; 2321573Srgrimes }; 2331573Srgrimes u64 dbval; 2341573Srgrimes unsigned long dbell_deadline; 2351573Srgrimes unsigned long dbell_jiffies; 2361573Srgrimes u16 head_idx; 2371573Srgrimes u16 tail_idx; 2381573Srgrimes unsigned int index; 2391573Srgrimes unsigned int num_descs; 2401573Srgrimes unsigned int max_sg_elems; 2411573Srgrimes u64 features; 2421573Srgrimes unsigned int type; 2431573Srgrimes unsigned int hw_index; 2441573Srgrimes unsigned int hw_type; 2451573Srgrimes bool xdp_flush; 2461573Srgrimes union { 2471573Srgrimes void *base; 2481573Srgrimes struct ionic_txq_desc *txq; 2491573Srgrimes struct ionic_rxq_desc *rxq; 2501573Srgrimes struct ionic_admin_cmd *adminq; 2511573Srgrimes }; 2521573Srgrimes union { 2531573Srgrimes void __iomem *cmb_base; 2541573Srgrimes struct ionic_txq_desc __iomem *cmb_txq; 2551573Srgrimes struct ionic_rxq_desc __iomem *cmb_rxq; 2561573Srgrimes }; 2571573Srgrimes union { 2581573Srgrimes void *sg_base; 2591573Srgrimes struct ionic_txq_sg_desc *txq_sgl; 2601573Srgrimes struct ionic_txq_sg_desc_v1 *txq_sgl_v1; 2611573Srgrimes struct ionic_rxq_sg_desc *rxq_sgl; 26251549Sru }; 2631573Srgrimes struct xdp_rxq_info *xdp_rxq_info; 2641573Srgrimes struct ionic_queue *partner; 2651573Srgrimes dma_addr_t base_pa; 2661573Srgrimes dma_addr_t cmb_base_pa; 26751549Sru dma_addr_t sg_base_pa; 2681573Srgrimes u64 drop; 2691573Srgrimes unsigned int desc_size; 2701573Srgrimes unsigned int sg_desc_size; 2711573Srgrimes unsigned int pid; 2721573Srgrimes char name[IONIC_QUEUE_NAME_MAX_SZ]; 2731573Srgrimes} ____cacheline_aligned_in_smp; 2741573Srgrimes 2751573Srgrimes#define IONIC_INTR_INDEX_NOT_ASSIGNED -1 2761573Srgrimes#define IONIC_INTR_NAME_MAX_SZ 32 2771573Srgrimes 2781573Srgrimesstruct ionic_intr_info { 2791573Srgrimes char name[IONIC_INTR_NAME_MAX_SZ]; 2801573Srgrimes u64 rearm_count; 2811573Srgrimes unsigned int index; 2821573Srgrimes unsigned int vector; 2831573Srgrimes unsigned int cpu; 2841573Srgrimes u32 dim_coal_hw; 2851573Srgrimes cpumask_t affinity_mask; 2861573Srgrimes}; 2871573Srgrimes 2881573Srgrimesstruct ionic_cq { 2891573Srgrimes struct ionic_lif *lif; 2901573Srgrimes struct ionic_queue *bound_q; 2911573Srgrimes struct ionic_intr_info *bound_intr; 2921573Srgrimes u16 tail_idx; 2931573Srgrimes bool done_color; 2941573Srgrimes unsigned int num_descs; 2951573Srgrimes unsigned int desc_size; 2961573Srgrimes void *base; 2971573Srgrimes dma_addr_t base_pa; 2981573Srgrimes struct ionic_dev *idev; 2991573Srgrimes} ____cacheline_aligned_in_smp; 3001573Srgrimes 3011573Srgrimesstruct ionic; 3021573Srgrimes 3031573Srgrimesstatic inline void ionic_intr_init(struct ionic_dev *idev, 3041573Srgrimes struct ionic_intr_info *intr, 3051573Srgrimes unsigned long index) 3061573Srgrimes{ 3071573Srgrimes ionic_intr_clean(idev->intr_ctrl, index); 3081573Srgrimes intr->index = index; 3091573Srgrimes} 3101573Srgrimes 3111573Srgrimesstatic inline unsigned int ionic_q_space_avail(struct ionic_queue *q) 3121573Srgrimes{ 3131573Srgrimes unsigned int avail = q->tail_idx; 3141573Srgrimes 3151573Srgrimes if (q->head_idx >= avail) 3161573Srgrimes avail += q->num_descs - q->head_idx - 1; 3171573Srgrimes else 3181573Srgrimes avail -= q->head_idx + 1; 3191573Srgrimes 3201573Srgrimes return avail; 3211573Srgrimes} 3221573Srgrimes 3231573Srgrimesstatic inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want) 3241573Srgrimes{ 3251573Srgrimes return ionic_q_space_avail(q) >= want; 3261573Srgrimes} 3271573Srgrimes 3281573Srgrimesvoid ionic_init_devinfo(struct ionic *ionic); 3291573Srgrimesint ionic_dev_setup(struct ionic *ionic); 3301573Srgrimesvoid ionic_dev_teardown(struct ionic *ionic); 3311573Srgrimes 3321573Srgrimesvoid ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 3331573Srgrimesu8 ionic_dev_cmd_status(struct ionic_dev *idev); 3341573Srgrimesbool ionic_dev_cmd_done(struct ionic_dev *idev); 3351573Srgrimesvoid ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp); 3361573Srgrimes 3371573Srgrimesvoid ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver); 3381573Srgrimesvoid ionic_dev_cmd_init(struct ionic_dev *idev); 3391573Srgrimesvoid ionic_dev_cmd_reset(struct ionic_dev *idev); 3401573Srgrimes 3411573Srgrimesvoid ionic_dev_cmd_port_identify(struct ionic_dev *idev); 3421573Srgrimesvoid ionic_dev_cmd_port_init(struct ionic_dev *idev); 3431573Srgrimesvoid ionic_dev_cmd_port_reset(struct ionic_dev *idev); 3441573Srgrimesvoid ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state); 3451573Srgrimesvoid ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed); 3461573Srgrimesvoid ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable); 3471573Srgrimesvoid ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type); 3481573Srgrimesvoid ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type); 3491573Srgrimes 3501573Srgrimesint ionic_set_vf_config(struct ionic *ionic, int vf, 3511573Srgrimes struct ionic_vf_setattr_cmd *vfc); 3521573Srgrimes 3531573Srgrimesvoid ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 3541573Srgrimes u16 lif_type, u8 qtype, u8 qver); 3551573Srgrimesvoid ionic_vf_start(struct ionic *ionic); 3561573Srgrimesvoid ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver); 3571573Srgrimesvoid ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 3581573Srgrimes dma_addr_t addr); 3591573Srgrimesvoid ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index); 3601573Srgrimesvoid ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 3611573Srgrimes u16 lif_index, u16 intr_index); 3621573Srgrimes 3631573Srgrimesint ionic_db_page_num(struct ionic_lif *lif, int pid); 3641573Srgrimes 3651573Srgrimesint ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order); 3661573Srgrimesvoid ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order); 3671573Srgrimes 3681573Srgrimesint ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 3691573Srgrimes struct ionic_intr_info *intr, 3701573Srgrimes unsigned int num_descs, size_t desc_size); 3711573Srgrimesvoid ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa); 3721573Srgrimesvoid ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q); 3731573Srgrimestypedef bool (*ionic_cq_cb)(struct ionic_cq *cq); 3741573Srgrimestypedef void (*ionic_cq_done_cb)(void *done_arg); 3758870Srgrimesunsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 3761573Srgrimes ionic_cq_cb cb, ionic_cq_done_cb done_cb, 3771573Srgrimes void *done_arg); 3781573Srgrimesunsigned int ionic_tx_cq_service(struct ionic_cq *cq, unsigned int work_to_do); 3791573Srgrimes 3801573Srgrimesint ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 3811573Srgrimes struct ionic_queue *q, unsigned int index, const char *name, 3821573Srgrimes unsigned int num_descs, size_t desc_size, 3831573Srgrimes size_t sg_desc_size, unsigned int pid); 3841573Srgrimesvoid ionic_q_post(struct ionic_queue *q, bool ring_doorbell); 3851573Srgrimesbool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos); 3861573Srgrimes 3871573Srgrimesint ionic_heartbeat_check(struct ionic *ionic); 3881573Srgrimesbool ionic_is_fw_running(struct ionic_dev *idev); 3891573Srgrimes 3901573Srgrimesbool ionic_adminq_poke_doorbell(struct ionic_queue *q); 3911573Srgrimesbool ionic_txq_poke_doorbell(struct ionic_queue *q); 3921573Srgrimesbool ionic_rxq_poke_doorbell(struct ionic_queue *q); 3931573Srgrimes 3941573Srgrimes#endif /* _IONIC_DEV_H_ */ 3951573Srgrimes