1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell CN10K RPM driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8#ifndef LMAC_COMMON_H
9#define LMAC_COMMON_H
10
11#include "rvu.h"
12#include "cgx.h"
13/**
14 * struct lmac - per lmac locks and properties
15 * @wq_cmd_cmplt:	waitq to keep the process blocked until cmd completion
16 * @cmd_lock:		Lock to serialize the command interface
17 * @resp:		command response
18 * @link_info:		link related information
19 * @mac_to_index_bmap:	Mac address to CGX table index mapping
20 * @rx_fc_pfvf_bmap:    Receive flow control enabled netdev mapping
21 * @tx_fc_pfvf_bmap:    Transmit flow control enabled netdev mapping
22 * @event_cb:		callback for linkchange events
23 * @event_cb_lock:	lock for serializing callback with unregister
24 * @cgx:		parent cgx port
25 * @mcast_filters_count:  Number of multicast filters installed
26 * @lmac_id:		lmac port id
27 * @lmac_type:	        lmac type like SGMII/XAUI
28 * @cmd_pend:		flag set before new command is started
29 *			flag cleared after command response is received
30 * @name:		lmac port name
31 */
32struct lmac {
33	wait_queue_head_t wq_cmd_cmplt;
34	/* Lock to serialize the command interface */
35	struct mutex cmd_lock;
36	u64 resp;
37	struct cgx_link_user_info link_info;
38	struct rsrc_bmap mac_to_index_bmap;
39	struct rsrc_bmap rx_fc_pfvf_bmap;
40	struct rsrc_bmap tx_fc_pfvf_bmap;
41	struct cgx_event_cb event_cb;
42	/* lock for serializing callback with unregister */
43	spinlock_t event_cb_lock;
44	struct cgx *cgx;
45	u8 mcast_filters_count;
46	u8 lmac_id;
47	u8 lmac_type;
48	bool cmd_pend;
49	char *name;
50};
51
52/* CGX & RPM has different feature set
53 * update the structure fields with different one
54 */
55struct mac_ops {
56	char		       *name;
57	/* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed
58	 * bar offset for example
59	 * CGX DMAC_CTL0  0x1f8
60	 * RPM DMAC_CTL0  0x4ff8
61	 */
62	u64			csr_offset;
63	/* For ATF to send events to kernel, there is no dedicated interrupt
64	 * defined hence CGX uses OVERFLOW bit in CMR_INT. RPM block supports
65	 * SW_INT so that ATF triggers this interrupt after processing of
66	 * requested command
67	 */
68	u64			int_register;
69	u64			int_set_reg;
70	/* lmac offset is different is RPM */
71	u8			lmac_offset;
72	u8			irq_offset;
73	u8			int_ena_bit;
74	u8			lmac_fwi;
75	u32			fifo_len;
76	bool			non_contiguous_serdes_lane;
77	/* RPM & CGX differs in number of Receive/transmit stats */
78	u8			rx_stats_cnt;
79	u8			tx_stats_cnt;
80	/* Unlike CN10K which shares same CSR offset with CGX
81	 * CNF10KB has different csr offset
82	 */
83	u64			rxid_map_offset;
84	u8			dmac_filter_count;
85	/* Incase of RPM get number of lmacs from RPMX_CMR_RX_LMACS[LMAC_EXIST]
86	 * number of setbits in lmac_exist tells number of lmacs
87	 */
88	int			(*get_nr_lmacs)(void *cgx);
89	u8                      (*get_lmac_type)(void *cgx, int lmac_id);
90	u32                     (*lmac_fifo_len)(void *cgx, int lmac_id);
91	int                     (*mac_lmac_intl_lbk)(void *cgx, int lmac_id,
92						     bool enable);
93	/* Register Stats related functions */
94	int			(*mac_get_rx_stats)(void *cgx, int lmac_id,
95						    int idx, u64 *rx_stat);
96	int			(*mac_get_tx_stats)(void *cgx, int lmac_id,
97						    int idx, u64 *tx_stat);
98
99	/* Enable LMAC Pause Frame Configuration */
100	void			(*mac_enadis_rx_pause_fwding)(void *cgxd,
101							      int lmac_id,
102							      bool enable);
103
104	int			(*mac_get_pause_frm_status)(void *cgxd,
105							    int lmac_id,
106							    u8 *tx_pause,
107							    u8 *rx_pause);
108
109	int			(*mac_enadis_pause_frm)(void *cgxd,
110							int lmac_id,
111							u8 tx_pause,
112							u8 rx_pause);
113
114	void			(*mac_pause_frm_config)(void  *cgxd,
115							int lmac_id,
116							bool enable);
117
118	/* Enable/Disable Inbound PTP */
119	void			(*mac_enadis_ptp_config)(void  *cgxd,
120							 int lmac_id,
121							 bool enable);
122
123	int			(*mac_rx_tx_enable)(void *cgxd, int lmac_id, bool enable);
124	int			(*mac_tx_enable)(void *cgxd, int lmac_id, bool enable);
125	int                     (*pfc_config)(void *cgxd, int lmac_id,
126					      u8 tx_pause, u8 rx_pause, u16 pfc_en);
127
128	int                     (*mac_get_pfc_frm_cfg)(void *cgxd, int lmac_id,
129						       u8 *tx_pause, u8 *rx_pause);
130	int			(*mac_reset)(void *cgxd, int lmac_id, u8 pf_req_flr);
131
132	/* FEC stats */
133	int			(*get_fec_stats)(void *cgxd, int lmac_id,
134						 struct cgx_fec_stats_rsp *rsp);
135};
136
137struct cgx {
138	void __iomem		*reg_base;
139	struct pci_dev		*pdev;
140	u8			cgx_id;
141	u8			lmac_count;
142	/* number of LMACs per MAC could be 4 or 8 */
143	u8			max_lmac_per_mac;
144#define MAX_LMAC_COUNT		8
145	struct lmac             *lmac_idmap[MAX_LMAC_COUNT];
146	struct			work_struct cgx_cmd_work;
147	struct			workqueue_struct *cgx_cmd_workq;
148	struct list_head	cgx_list;
149	u64			hw_features;
150	struct mac_ops		*mac_ops;
151	unsigned long		lmac_bmap; /* bitmap of enabled lmacs */
152	/* Lock to serialize read/write of global csrs like
153	 * RPMX_MTI_STAT_DATA_HI_CDC etc
154	 */
155	struct mutex		lock;
156};
157
158typedef struct cgx rpm_t;
159
160/* Function Declarations */
161void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val);
162u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset);
163struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx);
164int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac);
165int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id);
166bool is_lmac_valid(struct cgx *cgx, int lmac_id);
167struct mac_ops *rpm_get_mac_ops(struct cgx *cgx);
168
169#endif /* LMAC_COMMON_H */
170