1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Fast Ethernet Controller (ENET) PTP driver for MX6x. 4 * 5 * Copyright (C) 2012 Freescale Semiconductor, Inc. 6 */ 7 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10#include <linux/module.h> 11#include <linux/kernel.h> 12#include <linux/string.h> 13#include <linux/ptrace.h> 14#include <linux/errno.h> 15#include <linux/ioport.h> 16#include <linux/slab.h> 17#include <linux/interrupt.h> 18#include <linux/pci.h> 19#include <linux/delay.h> 20#include <linux/netdevice.h> 21#include <linux/etherdevice.h> 22#include <linux/skbuff.h> 23#include <linux/spinlock.h> 24#include <linux/workqueue.h> 25#include <linux/bitops.h> 26#include <linux/io.h> 27#include <linux/irq.h> 28#include <linux/clk.h> 29#include <linux/platform_device.h> 30#include <linux/phy.h> 31#include <linux/fec.h> 32#include <linux/of.h> 33#include <linux/of_gpio.h> 34#include <linux/of_net.h> 35 36#include "fec.h" 37 38/* FEC 1588 register bits */ 39#define FEC_T_CTRL_SLAVE 0x00002000 40#define FEC_T_CTRL_CAPTURE 0x00000800 41#define FEC_T_CTRL_RESTART 0x00000200 42#define FEC_T_CTRL_PERIOD_RST 0x00000030 43#define FEC_T_CTRL_PERIOD_EN 0x00000010 44#define FEC_T_CTRL_ENABLE 0x00000001 45 46#define FEC_T_INC_MASK 0x0000007f 47#define FEC_T_INC_OFFSET 0 48#define FEC_T_INC_CORR_MASK 0x00007f00 49#define FEC_T_INC_CORR_OFFSET 8 50 51#define FEC_T_CTRL_PINPER 0x00000080 52#define FEC_T_TF0_MASK 0x00000001 53#define FEC_T_TF0_OFFSET 0 54#define FEC_T_TF1_MASK 0x00000002 55#define FEC_T_TF1_OFFSET 1 56#define FEC_T_TF2_MASK 0x00000004 57#define FEC_T_TF2_OFFSET 2 58#define FEC_T_TF3_MASK 0x00000008 59#define FEC_T_TF3_OFFSET 3 60#define FEC_T_TDRE_MASK 0x00000001 61#define FEC_T_TDRE_OFFSET 0 62#define FEC_T_TMODE_MASK 0x0000003C 63#define FEC_T_TMODE_OFFSET 2 64#define FEC_T_TIE_MASK 0x00000040 65#define FEC_T_TIE_OFFSET 6 66#define FEC_T_TF_MASK 0x00000080 67#define FEC_T_TF_OFFSET 7 68 69#define FEC_ATIME_CTRL 0x400 70#define FEC_ATIME 0x404 71#define FEC_ATIME_EVT_OFFSET 0x408 72#define FEC_ATIME_EVT_PERIOD 0x40c 73#define FEC_ATIME_CORR 0x410 74#define FEC_ATIME_INC 0x414 75#define FEC_TS_TIMESTAMP 0x418 76 77#define FEC_TGSR 0x604 78#define FEC_TCSR(n) (0x608 + n * 0x08) 79#define FEC_TCCR(n) (0x60C + n * 0x08) 80#define MAX_TIMER_CHANNEL 3 81#define FEC_TMODE_TOGGLE 0x05 82#define FEC_HIGH_PULSE 0x0F 83 84#define FEC_CC_MULT (1 << 31) 85#define FEC_COUNTER_PERIOD (1 << 31) 86#define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC 87#define FEC_CHANNLE_0 0 88#define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0 89 90#define FEC_PTP_MAX_NSEC_PERIOD 4000000000ULL 91#define FEC_PTP_MAX_NSEC_COUNTER 0x80000000ULL 92 93/** 94 * fec_ptp_enable_pps 95 * @fep: the fec_enet_private structure handle 96 * @enable: enable the channel pps output 97 * 98 * This function enble the PPS ouput on the timer channel. 99 */ 100static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable) 101{ 102 unsigned long flags; 103 u32 val, tempval; 104 struct timespec64 ts; 105 u64 ns; 106 107 if (fep->pps_enable == enable) 108 return 0; 109 110 fep->pps_channel = DEFAULT_PPS_CHANNEL; 111 fep->reload_period = PPS_OUPUT_RELOAD_PERIOD; 112 113 spin_lock_irqsave(&fep->tmreg_lock, flags); 114 115 if (enable) { 116 /* clear capture or output compare interrupt status if have. 117 */ 118 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); 119 120 /* It is recommended to double check the TMODE field in the 121 * TCSR register to be cleared before the first compare counter 122 * is written into TCCR register. Just add a double check. 123 */ 124 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 125 do { 126 val &= ~(FEC_T_TMODE_MASK); 127 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); 128 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 129 } while (val & FEC_T_TMODE_MASK); 130 131 /* Dummy read counter to update the counter */ 132 timecounter_read(&fep->tc); 133 /* We want to find the first compare event in the next 134 * second point. So we need to know what the ptp time 135 * is now and how many nanoseconds is ahead to get next second. 136 * The remaining nanosecond ahead before the next second would be 137 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds 138 * to current timer would be next second. 139 */ 140 tempval = fep->cc.read(&fep->cc); 141 /* Convert the ptp local counter to 1588 timestamp */ 142 ns = timecounter_cyc2time(&fep->tc, tempval); 143 ts = ns_to_timespec64(ns); 144 145 /* The tempval is less than 3 seconds, and so val is less than 146 * 4 seconds. No overflow for 32bit calculation. 147 */ 148 val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval; 149 150 /* Need to consider the situation that the current time is 151 * very close to the second point, which means NSEC_PER_SEC 152 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer 153 * is still running when we calculate the first compare event, it is 154 * possible that the remaining nanoseonds run out before the compare 155 * counter is calculated and written into TCCR register. To avoid 156 * this possibility, we will set the compare event to be the next 157 * of next second. The current setting is 31-bit timer and wrap 158 * around over 2 seconds. So it is okay to set the next of next 159 * seond for the timer. 160 */ 161 val += NSEC_PER_SEC; 162 163 /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current 164 * ptp counter, which maybe cause 32-bit wrap. Since the 165 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second. 166 * We can ensure the wrap will not cause issue. If the offset 167 * is bigger than fep->cc.mask would be a error. 168 */ 169 val &= fep->cc.mask; 170 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); 171 172 /* Calculate the second the compare event timestamp */ 173 fep->next_counter = (val + fep->reload_period) & fep->cc.mask; 174 175 /* * Enable compare event when overflow */ 176 val = readl(fep->hwp + FEC_ATIME_CTRL); 177 val |= FEC_T_CTRL_PINPER; 178 writel(val, fep->hwp + FEC_ATIME_CTRL); 179 180 /* Compare channel setting. */ 181 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 182 val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); 183 val &= ~(1 << FEC_T_TDRE_OFFSET); 184 val &= ~(FEC_T_TMODE_MASK); 185 val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET); 186 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); 187 188 /* Write the second compare event timestamp and calculate 189 * the third timestamp. Refer the TCCR register detail in the spec. 190 */ 191 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); 192 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; 193 } else { 194 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); 195 } 196 197 fep->pps_enable = enable; 198 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 199 200 return 0; 201} 202 203static int fec_ptp_pps_perout(struct fec_enet_private *fep) 204{ 205 u32 compare_val, ptp_hc, temp_val; 206 u64 curr_time; 207 unsigned long flags; 208 209 spin_lock_irqsave(&fep->tmreg_lock, flags); 210 211 /* Update time counter */ 212 timecounter_read(&fep->tc); 213 214 /* Get the current ptp hardware time counter */ 215 temp_val = readl(fep->hwp + FEC_ATIME_CTRL); 216 temp_val |= FEC_T_CTRL_CAPTURE; 217 writel(temp_val, fep->hwp + FEC_ATIME_CTRL); 218 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) 219 udelay(1); 220 221 ptp_hc = readl(fep->hwp + FEC_ATIME); 222 223 /* Convert the ptp local counter to 1588 timestamp */ 224 curr_time = timecounter_cyc2time(&fep->tc, ptp_hc); 225 226 /* If the pps start time less than current time add 100ms, just return. 227 * Because the software might not able to set the comparison time into 228 * the FEC_TCCR register in time and missed the start time. 229 */ 230 if (fep->perout_stime < curr_time + 100 * NSEC_PER_MSEC) { 231 dev_err(&fep->pdev->dev, "Current time is too close to the start time!\n"); 232 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 233 return -1; 234 } 235 236 compare_val = fep->perout_stime - curr_time + ptp_hc; 237 compare_val &= fep->cc.mask; 238 239 writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel)); 240 fep->next_counter = (compare_val + fep->reload_period) & fep->cc.mask; 241 242 /* Enable compare event when overflow */ 243 temp_val = readl(fep->hwp + FEC_ATIME_CTRL); 244 temp_val |= FEC_T_CTRL_PINPER; 245 writel(temp_val, fep->hwp + FEC_ATIME_CTRL); 246 247 /* Compare channel setting. */ 248 temp_val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 249 temp_val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); 250 temp_val &= ~(1 << FEC_T_TDRE_OFFSET); 251 temp_val &= ~(FEC_T_TMODE_MASK); 252 temp_val |= (FEC_TMODE_TOGGLE << FEC_T_TMODE_OFFSET); 253 writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel)); 254 255 /* Write the second compare event timestamp and calculate 256 * the third timestamp. Refer the TCCR register detail in the spec. 257 */ 258 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); 259 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; 260 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 261 262 return 0; 263} 264 265static enum hrtimer_restart fec_ptp_pps_perout_handler(struct hrtimer *timer) 266{ 267 struct fec_enet_private *fep = container_of(timer, 268 struct fec_enet_private, perout_timer); 269 270 fec_ptp_pps_perout(fep); 271 272 return HRTIMER_NORESTART; 273} 274 275/** 276 * fec_ptp_read - read raw cycle counter (to be used by time counter) 277 * @cc: the cyclecounter structure 278 * 279 * this function reads the cyclecounter registers and is called by the 280 * cyclecounter structure used to construct a ns counter from the 281 * arbitrary fixed point registers 282 */ 283static u64 fec_ptp_read(const struct cyclecounter *cc) 284{ 285 struct fec_enet_private *fep = 286 container_of(cc, struct fec_enet_private, cc); 287 u32 tempval; 288 289 tempval = readl(fep->hwp + FEC_ATIME_CTRL); 290 tempval |= FEC_T_CTRL_CAPTURE; 291 writel(tempval, fep->hwp + FEC_ATIME_CTRL); 292 293 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) 294 udelay(1); 295 296 return readl(fep->hwp + FEC_ATIME); 297} 298 299/** 300 * fec_ptp_start_cyclecounter - create the cycle counter from hw 301 * @ndev: network device 302 * 303 * this function initializes the timecounter and cyclecounter 304 * structures for use in generated a ns counter from the arbitrary 305 * fixed point cycles registers in the hardware. 306 */ 307void fec_ptp_start_cyclecounter(struct net_device *ndev) 308{ 309 struct fec_enet_private *fep = netdev_priv(ndev); 310 unsigned long flags; 311 int inc; 312 313 inc = 1000000000 / fep->cycle_speed; 314 315 /* grab the ptp lock */ 316 spin_lock_irqsave(&fep->tmreg_lock, flags); 317 318 /* 1ns counter */ 319 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); 320 321 /* use 31-bit timer counter */ 322 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD); 323 324 writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST, 325 fep->hwp + FEC_ATIME_CTRL); 326 327 memset(&fep->cc, 0, sizeof(fep->cc)); 328 fep->cc.read = fec_ptp_read; 329 fep->cc.mask = CLOCKSOURCE_MASK(31); 330 fep->cc.shift = 31; 331 fep->cc.mult = FEC_CC_MULT; 332 333 /* reset the ns time counter */ 334 timecounter_init(&fep->tc, &fep->cc, 0); 335 336 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 337} 338 339/** 340 * fec_ptp_adjfine - adjust ptp cycle frequency 341 * @ptp: the ptp clock structure 342 * @scaled_ppm: scaled parts per million adjustment from base 343 * 344 * Adjust the frequency of the ptp cycle counter by the 345 * indicated amount from the base frequency. 346 * 347 * Scaled parts per million is ppm with a 16-bit binary fractional field. 348 * 349 * Because ENET hardware frequency adjust is complex, 350 * using software method to do that. 351 */ 352static int fec_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 353{ 354 s32 ppb = scaled_ppm_to_ppb(scaled_ppm); 355 unsigned long flags; 356 int neg_adj = 0; 357 u32 i, tmp; 358 u32 corr_inc, corr_period; 359 u32 corr_ns; 360 u64 lhs, rhs; 361 362 struct fec_enet_private *fep = 363 container_of(ptp, struct fec_enet_private, ptp_caps); 364 365 if (ppb == 0) 366 return 0; 367 368 if (ppb < 0) { 369 ppb = -ppb; 370 neg_adj = 1; 371 } 372 373 /* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC; 374 * Try to find the corr_inc between 1 to fep->ptp_inc to 375 * meet adjustment requirement. 376 */ 377 lhs = NSEC_PER_SEC; 378 rhs = (u64)ppb * (u64)fep->ptp_inc; 379 for (i = 1; i <= fep->ptp_inc; i++) { 380 if (lhs >= rhs) { 381 corr_inc = i; 382 corr_period = div_u64(lhs, rhs); 383 break; 384 } 385 lhs += NSEC_PER_SEC; 386 } 387 /* Not found? Set it to high value - double speed 388 * correct in every clock step. 389 */ 390 if (i > fep->ptp_inc) { 391 corr_inc = fep->ptp_inc; 392 corr_period = 1; 393 } 394 395 if (neg_adj) 396 corr_ns = fep->ptp_inc - corr_inc; 397 else 398 corr_ns = fep->ptp_inc + corr_inc; 399 400 spin_lock_irqsave(&fep->tmreg_lock, flags); 401 402 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; 403 tmp |= corr_ns << FEC_T_INC_CORR_OFFSET; 404 writel(tmp, fep->hwp + FEC_ATIME_INC); 405 corr_period = corr_period > 1 ? corr_period - 1 : corr_period; 406 writel(corr_period, fep->hwp + FEC_ATIME_CORR); 407 /* dummy read to update the timer. */ 408 timecounter_read(&fep->tc); 409 410 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 411 412 return 0; 413} 414 415/** 416 * fec_ptp_adjtime 417 * @ptp: the ptp clock structure 418 * @delta: offset to adjust the cycle counter by 419 * 420 * adjust the timer by resetting the timecounter structure. 421 */ 422static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 423{ 424 struct fec_enet_private *fep = 425 container_of(ptp, struct fec_enet_private, ptp_caps); 426 unsigned long flags; 427 428 spin_lock_irqsave(&fep->tmreg_lock, flags); 429 timecounter_adjtime(&fep->tc, delta); 430 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 431 432 return 0; 433} 434 435/** 436 * fec_ptp_gettime 437 * @ptp: the ptp clock structure 438 * @ts: timespec structure to hold the current time value 439 * 440 * read the timecounter and return the correct value on ns, 441 * after converting it into a struct timespec. 442 */ 443static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 444{ 445 struct fec_enet_private *fep = 446 container_of(ptp, struct fec_enet_private, ptp_caps); 447 u64 ns; 448 unsigned long flags; 449 450 mutex_lock(&fep->ptp_clk_mutex); 451 /* Check the ptp clock */ 452 if (!fep->ptp_clk_on) { 453 mutex_unlock(&fep->ptp_clk_mutex); 454 return -EINVAL; 455 } 456 spin_lock_irqsave(&fep->tmreg_lock, flags); 457 ns = timecounter_read(&fep->tc); 458 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 459 mutex_unlock(&fep->ptp_clk_mutex); 460 461 *ts = ns_to_timespec64(ns); 462 463 return 0; 464} 465 466/** 467 * fec_ptp_settime 468 * @ptp: the ptp clock structure 469 * @ts: the timespec containing the new time for the cycle counter 470 * 471 * reset the timecounter to use a new base value instead of the kernel 472 * wall timer value. 473 */ 474static int fec_ptp_settime(struct ptp_clock_info *ptp, 475 const struct timespec64 *ts) 476{ 477 struct fec_enet_private *fep = 478 container_of(ptp, struct fec_enet_private, ptp_caps); 479 480 u64 ns; 481 unsigned long flags; 482 u32 counter; 483 484 mutex_lock(&fep->ptp_clk_mutex); 485 /* Check the ptp clock */ 486 if (!fep->ptp_clk_on) { 487 mutex_unlock(&fep->ptp_clk_mutex); 488 return -EINVAL; 489 } 490 491 ns = timespec64_to_ns(ts); 492 /* Get the timer value based on timestamp. 493 * Update the counter with the masked value. 494 */ 495 counter = ns & fep->cc.mask; 496 497 spin_lock_irqsave(&fep->tmreg_lock, flags); 498 writel(counter, fep->hwp + FEC_ATIME); 499 timecounter_init(&fep->tc, &fep->cc, ns); 500 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 501 mutex_unlock(&fep->ptp_clk_mutex); 502 return 0; 503} 504 505static int fec_ptp_pps_disable(struct fec_enet_private *fep, uint channel) 506{ 507 unsigned long flags; 508 509 spin_lock_irqsave(&fep->tmreg_lock, flags); 510 writel(0, fep->hwp + FEC_TCSR(channel)); 511 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 512 513 return 0; 514} 515 516/** 517 * fec_ptp_enable 518 * @ptp: the ptp clock structure 519 * @rq: the requested feature to change 520 * @on: whether to enable or disable the feature 521 * 522 */ 523static int fec_ptp_enable(struct ptp_clock_info *ptp, 524 struct ptp_clock_request *rq, int on) 525{ 526 struct fec_enet_private *fep = 527 container_of(ptp, struct fec_enet_private, ptp_caps); 528 ktime_t timeout; 529 struct timespec64 start_time, period; 530 u64 curr_time, delta, period_ns; 531 unsigned long flags; 532 int ret = 0; 533 534 if (rq->type == PTP_CLK_REQ_PPS) { 535 ret = fec_ptp_enable_pps(fep, on); 536 537 return ret; 538 } else if (rq->type == PTP_CLK_REQ_PEROUT) { 539 /* Reject requests with unsupported flags */ 540 if (rq->perout.flags) 541 return -EOPNOTSUPP; 542 543 if (rq->perout.index != DEFAULT_PPS_CHANNEL) 544 return -EOPNOTSUPP; 545 546 fep->pps_channel = DEFAULT_PPS_CHANNEL; 547 period.tv_sec = rq->perout.period.sec; 548 period.tv_nsec = rq->perout.period.nsec; 549 period_ns = timespec64_to_ns(&period); 550 551 /* FEC PTP timer only has 31 bits, so if the period exceed 552 * 4s is not supported. 553 */ 554 if (period_ns > FEC_PTP_MAX_NSEC_PERIOD) { 555 dev_err(&fep->pdev->dev, "The period must equal to or less than 4s!\n"); 556 return -EOPNOTSUPP; 557 } 558 559 fep->reload_period = div_u64(period_ns, 2); 560 if (on && fep->reload_period) { 561 /* Convert 1588 timestamp to ns*/ 562 start_time.tv_sec = rq->perout.start.sec; 563 start_time.tv_nsec = rq->perout.start.nsec; 564 fep->perout_stime = timespec64_to_ns(&start_time); 565 566 mutex_lock(&fep->ptp_clk_mutex); 567 if (!fep->ptp_clk_on) { 568 dev_err(&fep->pdev->dev, "Error: PTP clock is closed!\n"); 569 mutex_unlock(&fep->ptp_clk_mutex); 570 return -EOPNOTSUPP; 571 } 572 spin_lock_irqsave(&fep->tmreg_lock, flags); 573 /* Read current timestamp */ 574 curr_time = timecounter_read(&fep->tc); 575 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 576 mutex_unlock(&fep->ptp_clk_mutex); 577 578 /* Calculate time difference */ 579 delta = fep->perout_stime - curr_time; 580 581 if (fep->perout_stime <= curr_time) { 582 dev_err(&fep->pdev->dev, "Start time must larger than current time!\n"); 583 return -EINVAL; 584 } 585 586 /* Because the timer counter of FEC only has 31-bits, correspondingly, 587 * the time comparison register FEC_TCCR also only low 31 bits can be 588 * set. If the start time of pps signal exceeds current time more than 589 * 0x80000000 ns, a software timer is used and the timer expires about 590 * 1 second before the start time to be able to set FEC_TCCR. 591 */ 592 if (delta > FEC_PTP_MAX_NSEC_COUNTER) { 593 timeout = ns_to_ktime(delta - NSEC_PER_SEC); 594 hrtimer_start(&fep->perout_timer, timeout, HRTIMER_MODE_REL); 595 } else { 596 return fec_ptp_pps_perout(fep); 597 } 598 } else { 599 fec_ptp_pps_disable(fep, fep->pps_channel); 600 } 601 602 return 0; 603 } else { 604 return -EOPNOTSUPP; 605 } 606} 607 608int fec_ptp_set(struct net_device *ndev, struct kernel_hwtstamp_config *config, 609 struct netlink_ext_ack *extack) 610{ 611 struct fec_enet_private *fep = netdev_priv(ndev); 612 613 switch (config->tx_type) { 614 case HWTSTAMP_TX_OFF: 615 fep->hwts_tx_en = 0; 616 break; 617 case HWTSTAMP_TX_ON: 618 fep->hwts_tx_en = 1; 619 break; 620 default: 621 return -ERANGE; 622 } 623 624 switch (config->rx_filter) { 625 case HWTSTAMP_FILTER_NONE: 626 fep->hwts_rx_en = 0; 627 break; 628 629 default: 630 fep->hwts_rx_en = 1; 631 config->rx_filter = HWTSTAMP_FILTER_ALL; 632 break; 633 } 634 635 return 0; 636} 637 638void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *config) 639{ 640 struct fec_enet_private *fep = netdev_priv(ndev); 641 642 config->flags = 0; 643 config->tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 644 config->rx_filter = (fep->hwts_rx_en ? 645 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 646} 647 648/* 649 * fec_time_keep - call timecounter_read every second to avoid timer overrun 650 * because ENET just support 32bit counter, will timeout in 4s 651 */ 652static void fec_time_keep(struct work_struct *work) 653{ 654 struct delayed_work *dwork = to_delayed_work(work); 655 struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep); 656 unsigned long flags; 657 658 mutex_lock(&fep->ptp_clk_mutex); 659 if (fep->ptp_clk_on) { 660 spin_lock_irqsave(&fep->tmreg_lock, flags); 661 timecounter_read(&fep->tc); 662 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 663 } 664 mutex_unlock(&fep->ptp_clk_mutex); 665 666 schedule_delayed_work(&fep->time_keep, HZ); 667} 668 669/* This function checks the pps event and reloads the timer compare counter. */ 670static irqreturn_t fec_pps_interrupt(int irq, void *dev_id) 671{ 672 struct net_device *ndev = dev_id; 673 struct fec_enet_private *fep = netdev_priv(ndev); 674 u32 val; 675 u8 channel = fep->pps_channel; 676 struct ptp_clock_event event; 677 678 val = readl(fep->hwp + FEC_TCSR(channel)); 679 if (val & FEC_T_TF_MASK) { 680 /* Write the next next compare(not the next according the spec) 681 * value to the register 682 */ 683 writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); 684 do { 685 writel(val, fep->hwp + FEC_TCSR(channel)); 686 } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); 687 688 /* Update the counter; */ 689 fep->next_counter = (fep->next_counter + fep->reload_period) & 690 fep->cc.mask; 691 692 event.type = PTP_CLOCK_PPS; 693 ptp_clock_event(fep->ptp_clock, &event); 694 return IRQ_HANDLED; 695 } 696 697 return IRQ_NONE; 698} 699 700/** 701 * fec_ptp_init 702 * @pdev: The FEC network adapter 703 * @irq_idx: the interrupt index 704 * 705 * This function performs the required steps for enabling ptp 706 * support. If ptp support has already been loaded it simply calls the 707 * cyclecounter init routine and exits. 708 */ 709 710void fec_ptp_init(struct platform_device *pdev, int irq_idx) 711{ 712 struct net_device *ndev = platform_get_drvdata(pdev); 713 struct fec_enet_private *fep = netdev_priv(ndev); 714 int irq; 715 int ret; 716 717 fep->ptp_caps.owner = THIS_MODULE; 718 strscpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name)); 719 720 fep->ptp_caps.max_adj = 250000000; 721 fep->ptp_caps.n_alarm = 0; 722 fep->ptp_caps.n_ext_ts = 0; 723 fep->ptp_caps.n_per_out = 1; 724 fep->ptp_caps.n_pins = 0; 725 fep->ptp_caps.pps = 1; 726 fep->ptp_caps.adjfine = fec_ptp_adjfine; 727 fep->ptp_caps.adjtime = fec_ptp_adjtime; 728 fep->ptp_caps.gettime64 = fec_ptp_gettime; 729 fep->ptp_caps.settime64 = fec_ptp_settime; 730 fep->ptp_caps.enable = fec_ptp_enable; 731 732 fep->cycle_speed = clk_get_rate(fep->clk_ptp); 733 if (!fep->cycle_speed) { 734 fep->cycle_speed = NSEC_PER_SEC; 735 dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n"); 736 } 737 fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed; 738 739 spin_lock_init(&fep->tmreg_lock); 740 741 fec_ptp_start_cyclecounter(ndev); 742 743 INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep); 744 745 hrtimer_init(&fep->perout_timer, CLOCK_REALTIME, HRTIMER_MODE_REL); 746 fep->perout_timer.function = fec_ptp_pps_perout_handler; 747 748 irq = platform_get_irq_byname_optional(pdev, "pps"); 749 if (irq < 0) 750 irq = platform_get_irq_optional(pdev, irq_idx); 751 /* Failure to get an irq is not fatal, 752 * only the PTP_CLOCK_PPS clock events should stop 753 */ 754 if (irq >= 0) { 755 ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt, 756 0, pdev->name, ndev); 757 if (ret < 0) 758 dev_warn(&pdev->dev, "request for pps irq failed(%d)\n", 759 ret); 760 } 761 762 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev); 763 if (IS_ERR(fep->ptp_clock)) { 764 fep->ptp_clock = NULL; 765 dev_err(&pdev->dev, "ptp_clock_register failed\n"); 766 } 767 768 schedule_delayed_work(&fep->time_keep, HZ); 769} 770 771void fec_ptp_stop(struct platform_device *pdev) 772{ 773 struct net_device *ndev = platform_get_drvdata(pdev); 774 struct fec_enet_private *fep = netdev_priv(ndev); 775 776 cancel_delayed_work_sync(&fep->time_keep); 777 hrtimer_cancel(&fep->perout_timer); 778 if (fep->ptp_clock) 779 ptp_clock_unregister(fep->ptp_clock); 780} 781