1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (C) 2021 Gerhard Engleder <gerhard@engleder-embedded.com> */ 3 4/* Hardware definition of TSNEP and EtherCAT MAC device */ 5 6#ifndef _TSNEP_HW_H 7#define _TSNEP_HW_H 8 9#include <linux/types.h> 10 11/* type */ 12#define ECM_TYPE 0x0000 13#define ECM_REVISION_MASK 0x000000FF 14#define ECM_REVISION_SHIFT 0 15#define ECM_VERSION_MASK 0x0000FF00 16#define ECM_VERSION_SHIFT 8 17#define ECM_QUEUE_COUNT_MASK 0x00070000 18#define ECM_QUEUE_COUNT_SHIFT 16 19#define ECM_GATE_CONTROL 0x02000000 20 21/* system time */ 22#define ECM_SYSTEM_TIME_LOW 0x0008 23#define ECM_SYSTEM_TIME_HIGH 0x000C 24 25/* clock */ 26#define ECM_CLOCK_RATE 0x0010 27#define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF 28#define ECM_CLOCK_RATE_OFFSET_SIGN 0x80000000 29 30/* interrupt */ 31#define ECM_INT_ENABLE 0x0018 32#define ECM_INT_ACTIVE 0x001C 33#define ECM_INT_ACKNOWLEDGE 0x001C 34#define ECM_INT_LINK 0x00000020 35#define ECM_INT_TX_0 0x00000100 36#define ECM_INT_RX_0 0x00000200 37#define ECM_INT_TXRX_SHIFT 2 38#define ECM_INT_ALL 0x7FFFFFFF 39#define ECM_INT_DISABLE 0x80000000 40 41/* reset */ 42#define ECM_RESET 0x0020 43#define ECM_RESET_COMMON 0x00000001 44#define ECM_RESET_CHANNEL 0x00000100 45#define ECM_RESET_TXRX 0x00010000 46 47/* counter */ 48#define ECM_COUNTER_LOW 0x0028 49#define ECM_COUNTER_HIGH 0x002C 50 51/* interrupt delay */ 52#define ECM_INT_DELAY 0x0030 53#define ECM_INT_DELAY_MASK 0xF0 54#define ECM_INT_DELAY_SHIFT 4 55#define ECM_INT_DELAY_BASE_US 16 56#define ECM_INT_DELAY_OFFSET 1 57 58/* control and status */ 59#define ECM_STATUS 0x0080 60#define ECM_LINK_MODE_OFF 0x01000000 61#define ECM_LINK_MODE_100 0x02000000 62#define ECM_LINK_MODE_1000 0x04000000 63#define ECM_NO_LINK 0x01000000 64#define ECM_LINK_MODE_MASK 0x06000000 65 66/* management data */ 67#define ECM_MD_CONTROL 0x0084 68#define ECM_MD_STATUS 0x0084 69#define ECM_MD_PREAMBLE 0x00000001 70#define ECM_MD_READ 0x00000004 71#define ECM_MD_WRITE 0x00000002 72#define ECM_MD_ADDR_MASK 0x000000F8 73#define ECM_MD_ADDR_SHIFT 3 74#define ECM_MD_PHY_ADDR_MASK 0x00001F00 75#define ECM_MD_PHY_ADDR_SHIFT 8 76#define ECM_MD_BUSY 0x00000001 77#define ECM_MD_DATA_MASK 0xFFFF0000 78#define ECM_MD_DATA_SHIFT 16 79 80/* statistic */ 81#define ECM_STAT 0x00B0 82#define ECM_STAT_RX_ERR_MASK 0x000000FF 83#define ECM_STAT_RX_ERR_SHIFT 0 84#define ECM_STAT_INV_FRM_MASK 0x0000FF00 85#define ECM_STAT_INV_FRM_SHIFT 8 86#define ECM_STAT_FWD_RX_ERR_MASK 0x00FF0000 87#define ECM_STAT_FWD_RX_ERR_SHIFT 16 88 89/* tsnep */ 90#define TSNEP_MAC_SIZE 0x4000 91#define TSNEP_QUEUE_SIZE 0x1000 92#define TSNEP_QUEUE(n) ({ typeof(n) __n = (n); \ 93 (__n) == 0 ? \ 94 0 : \ 95 TSNEP_MAC_SIZE + TSNEP_QUEUE_SIZE * ((__n) - 1); }) 96#define TSNEP_MAX_QUEUES 8 97#define TSNEP_MAX_FRAME_SIZE (2 * 1024) /* hardware supports actually 16k */ 98#define TSNEP_DESC_SIZE 256 99#define TSNEP_DESC_OFFSET 128 100 101/* tsnep register */ 102#define TSNEP_INFO 0x0100 103#define TSNEP_INFO_TX_TIME 0x00010000 104#define TSNEP_CONTROL 0x0108 105#define TSNEP_CONTROL_TX_RESET 0x00000001 106#define TSNEP_CONTROL_TX_ENABLE 0x00000002 107#define TSNEP_CONTROL_TX_DMA_ERROR 0x00000010 108#define TSNEP_CONTROL_TX_DESC_ERROR 0x00000020 109#define TSNEP_CONTROL_RX_RESET 0x00000100 110#define TSNEP_CONTROL_RX_ENABLE 0x00000200 111#define TSNEP_CONTROL_RX_DISABLE 0x00000400 112#define TSNEP_CONTROL_RX_DMA_ERROR 0x00001000 113#define TSNEP_CONTROL_RX_DESC_ERROR 0x00002000 114#define TSNEP_TX_DESC_ADDR_LOW 0x0140 115#define TSNEP_TX_DESC_ADDR_HIGH 0x0144 116#define TSNEP_RX_DESC_ADDR_LOW 0x0180 117#define TSNEP_RX_DESC_ADDR_HIGH 0x0184 118#define TSNEP_RESET_OWNER_COUNTER 0x01 119#define TSNEP_RX_STATISTIC 0x0190 120#define TSNEP_RX_STATISTIC_NO_DESC_MASK 0x000000FF 121#define TSNEP_RX_STATISTIC_NO_DESC_SHIFT 0 122#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_MASK 0x0000FF00 123#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_SHIFT 8 124#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_MASK 0x00FF0000 125#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_SHIFT 16 126#define TSNEP_RX_STATISTIC_INVALID_FRAME_MASK 0xFF000000 127#define TSNEP_RX_STATISTIC_INVALID_FRAME_SHIFT 24 128#define TSNEP_RX_STATISTIC_NO_DESC 0x0190 129#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL 0x0191 130#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW 0x0192 131#define TSNEP_RX_STATISTIC_INVALID_FRAME 0x0193 132#define TSNEP_MAC_ADDRESS_LOW 0x0800 133#define TSNEP_MAC_ADDRESS_HIGH 0x0804 134#define TSNEP_RX_FILTER 0x0806 135#define TSNEP_RX_FILTER_ACCEPT_ALL_MULTICASTS 0x0001 136#define TSNEP_RX_FILTER_ACCEPT_ALL_UNICASTS 0x0002 137#define TSNEP_GC 0x0808 138#define TSNEP_GC_ENABLE_A 0x00000002 139#define TSNEP_GC_ENABLE_B 0x00000004 140#define TSNEP_GC_DISABLE 0x00000008 141#define TSNEP_GC_ENABLE_TIMEOUT 0x00000010 142#define TSNEP_GC_ACTIVE_A 0x00000002 143#define TSNEP_GC_ACTIVE_B 0x00000004 144#define TSNEP_GC_CHANGE_AB 0x00000008 145#define TSNEP_GC_TIMEOUT_ACTIVE 0x00000010 146#define TSNEP_GC_TIMEOUT_SIGNAL 0x00000020 147#define TSNEP_GC_LIST_ERROR 0x00000080 148#define TSNEP_GC_OPEN 0x00FF0000 149#define TSNEP_GC_OPEN_SHIFT 16 150#define TSNEP_GC_NEXT_OPEN 0xFF000000 151#define TSNEP_GC_NEXT_OPEN_SHIFT 24 152#define TSNEP_GC_TIMEOUT 131072 153#define TSNEP_GC_TIME 0x080C 154#define TSNEP_GC_CHANGE 0x0810 155#define TSNEP_GCL_A 0x2000 156#define TSNEP_GCL_B 0x2800 157#define TSNEP_GCL_SIZE SZ_2K 158#define TSNEP_RX_ASSIGN 0x0840 159#define TSNEP_RX_ASSIGN_ACTIVE 0x00000001 160#define TSNEP_RX_ASSIGN_QUEUE_MASK 0x00000006 161#define TSNEP_RX_ASSIGN_QUEUE_SHIFT 1 162#define TSNEP_RX_ASSIGN_OFFSET 1 163#define TSNEP_RX_ASSIGN_ETHER_TYPE 0x0880 164#define TSNEP_RX_ASSIGN_ETHER_TYPE_OFFSET 2 165#define TSNEP_RX_ASSIGN_ETHER_TYPE_COUNT 2 166 167/* tsnep gate control list operation */ 168struct tsnep_gcl_operation { 169 u32 properties; 170 u32 interval; 171}; 172 173#define TSNEP_GCL_COUNT (TSNEP_GCL_SIZE / sizeof(struct tsnep_gcl_operation)) 174#define TSNEP_GCL_MASK 0x000000FF 175#define TSNEP_GCL_INSERT 0x20000000 176#define TSNEP_GCL_CHANGE 0x40000000 177#define TSNEP_GCL_LAST 0x80000000 178#define TSNEP_GCL_MIN_INTERVAL 32 179 180/* tsnep TX/RX descriptor */ 181#define TSNEP_DESC_SIZE 256 182#define TSNEP_DESC_SIZE_DATA_AFTER 2048 183#define TSNEP_DESC_OFFSET 128 184#define TSNEP_DESC_SIZE_DATA_AFTER_INLINE (64 - sizeof(struct tsnep_tx_desc) + \ 185 sizeof_field(struct tsnep_tx_desc, tx)) 186#define TSNEP_DESC_OWNER_COUNTER_MASK 0xC0000000 187#define TSNEP_DESC_OWNER_COUNTER_SHIFT 30 188#define TSNEP_DESC_LENGTH_MASK 0x00003FFF 189#define TSNEP_DESC_INTERRUPT_FLAG 0x00040000 190#define TSNEP_DESC_EXTENDED_WRITEBACK_FLAG 0x00080000 191#define TSNEP_DESC_NO_LINK_FLAG 0x01000000 192 193/* tsnep TX descriptor */ 194struct tsnep_tx_desc { 195 __le32 properties; 196 __le32 more_properties; 197 __le32 reserved[2]; 198 __le64 next; 199 __le64 tx; 200}; 201 202#define TSNEP_TX_DESC_OWNER_MASK 0xE0000000 203#define TSNEP_TX_DESC_OWNER_USER_FLAG 0x20000000 204#define TSNEP_TX_DESC_LAST_FRAGMENT_FLAG 0x00010000 205#define TSNEP_TX_DESC_DATA_AFTER_DESC_FLAG 0x00020000 206 207/* tsnep TX descriptor writeback */ 208struct tsnep_tx_desc_wb { 209 __le32 properties; 210 __le32 reserved1; 211 __le64 counter; 212 __le64 timestamp; 213 __le32 dma_delay; 214 __le32 reserved2; 215}; 216 217#define TSNEP_TX_DESC_UNDERRUN_ERROR_FLAG 0x00010000 218#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_MASK 0x0000FFFC 219#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_SHIFT 2 220#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_MASK 0xFFFC0000 221#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_SHIFT 18 222#define TSNEP_TX_DESC_DMA_DELAY_NS 64 223 224/* tsnep RX descriptor */ 225struct tsnep_rx_desc { 226 __le32 properties; 227 __le32 reserved[3]; 228 __le64 next; 229 __le64 rx; 230}; 231 232#define TSNEP_RX_DESC_BUFFER_SIZE_MASK 0x00003FFC 233 234/* tsnep RX descriptor writeback */ 235struct tsnep_rx_desc_wb { 236 __le32 properties; 237 __le32 reserved[7]; 238}; 239 240/* tsnep RX inline meta */ 241struct tsnep_rx_inline { 242 __le64 counter; 243 __le64 timestamp; 244}; 245 246#define TSNEP_RX_INLINE_METADATA_SIZE (sizeof(struct tsnep_rx_inline)) 247 248#endif /* _TSNEP_HW_H */ 249