1/**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 *          Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT.  See the GNU General Public License for more details.
17 ***********************************************************************/
18/*!  \file  octeon_iq.h
19 *   \brief Host Driver: Implementation of Octeon input queues. "Input" is
20 *   with respect to the Octeon device on the NIC. From this driver's
21 *   point of view they are egress queues.
22 */
23
24#ifndef __OCTEON_IQ_H__
25#define  __OCTEON_IQ_H__
26
27#define IQ_STATUS_RUNNING   1
28
29#define IQ_SEND_OK          0
30#define IQ_SEND_STOP        1
31#define IQ_SEND_FAILED     -1
32
33/*-------------------------  INSTRUCTION QUEUE --------------------------*/
34
35/* \cond */
36
37#define REQTYPE_NONE                 0
38#define REQTYPE_NORESP_NET           1
39#define REQTYPE_NORESP_NET_SG        2
40#define REQTYPE_RESP_NET             3
41#define REQTYPE_RESP_NET_SG          4
42#define REQTYPE_SOFT_COMMAND         5
43#define REQTYPE_LAST                 5
44
45struct octeon_request_list {
46	u32 reqtype;
47	void *buf;
48};
49
50/* \endcond */
51
52/** Input Queue statistics. Each input queue has four stats fields. */
53struct oct_iq_stats {
54	u64 instr_posted; /**< Instructions posted to this queue. */
55	u64 instr_processed; /**< Instructions processed in this queue. */
56	u64 instr_dropped; /**< Instructions that could not be processed */
57	u64 bytes_sent;  /**< Bytes sent through this queue. */
58	u64 sgentry_sent;/**< Gather entries sent through this queue. */
59	u64 tx_done;/**< Num of packets sent to network. */
60	u64 tx_iq_busy;/**< Numof times this iq was found to be full. */
61	u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */
62	u64 tx_tot_bytes;/**< Total count of bytes sento to network. */
63	u64 tx_gso;  /* count of tso */
64	u64 tx_vxlan; /* tunnel */
65	u64 tx_dmamap_fail; /* Number of times dma mapping failed */
66	u64 tx_restart; /* Number of times this queue restarted */
67};
68
69#define OCT_IQ_STATS_SIZE   (sizeof(struct oct_iq_stats))
70
71/** The instruction (input) queue.
72 *  The input queue is used to post raw (instruction) mode data or packet
73 *  data to Octeon device from the host. Each input queue (upto 4) for
74 *  a Octeon device has one such structure to represent it.
75 */
76struct octeon_instr_queue {
77	struct octeon_device *oct_dev;
78
79	/** A spinlock to protect access to the input ring.  */
80	spinlock_t lock;
81
82	/** A spinlock to protect while posting on the ring.  */
83	spinlock_t post_lock;
84
85	/** This flag indicates if the queue can be used for soft commands.
86	 *  If this flag is set, post_lock must be acquired before posting
87	 *  a command to the queue.
88	 *  If this flag is clear, post_lock is invalid for the queue.
89	 *  All control commands (soft commands) will go through only Queue 0
90	 *  (control and data queue). So only queue-0 needs post_lock,
91	 *  other queues are only data queues and does not need post_lock
92	 */
93	bool allow_soft_cmds;
94
95	u32 pkt_in_done;
96
97	u32 pkts_processed;
98
99	/** A spinlock to protect access to the input ring.*/
100	spinlock_t iq_flush_running_lock;
101
102	/** Flag that indicates if the queue uses 64 byte commands. */
103	u32 iqcmd_64B:1;
104
105	/** Queue info. */
106	union oct_txpciq txpciq;
107
108	u32 rsvd:17;
109
110	/* Controls whether extra flushing of IQ is done on Tx */
111	u32 do_auto_flush:1;
112
113	u32 status:8;
114
115	/** Maximum no. of instructions in this queue. */
116	u32 max_count;
117
118	/** Index in input ring where the driver should write the next packet */
119	u32 host_write_index;
120
121	/** Index in input ring where Octeon is expected to read the next
122	 * packet.
123	 */
124	u32 octeon_read_index;
125
126	/** This index aids in finding the window in the queue where Octeon
127	 *  has read the commands.
128	 */
129	u32 flush_index;
130
131	/** This field keeps track of the instructions pending in this queue. */
132	atomic_t instr_pending;
133
134	u32 reset_instr_cnt;
135
136	/** Pointer to the Virtual Base addr of the input ring. */
137	u8 *base_addr;
138
139	struct octeon_request_list *request_list;
140
141	/** Octeon doorbell register for the ring. */
142	void __iomem *doorbell_reg;
143
144	/** Octeon instruction count register for this ring. */
145	void __iomem *inst_cnt_reg;
146
147	/** Number of instructions pending to be posted to Octeon. */
148	u32 fill_cnt;
149
150	/** The max. number of instructions that can be held pending by the
151	 * driver.
152	 */
153	u32 fill_threshold;
154
155	/** The last time that the doorbell was rung. */
156	u64 last_db_time;
157
158	/** The doorbell timeout. If the doorbell was not rung for this time and
159	 * fill_cnt is non-zero, ring the doorbell again.
160	 */
161	u32 db_timeout;
162
163	/** Statistics for this input queue. */
164	struct oct_iq_stats stats;
165
166	/** DMA mapped base address of the input descriptor ring. */
167	dma_addr_t base_addr_dma;
168
169	/** Application context */
170	void *app_ctx;
171
172	/* network stack queue index */
173	int q_index;
174
175	/*os ifidx associated with this queue */
176	int ifidx;
177
178};
179
180/*----------------------  INSTRUCTION FORMAT ----------------------------*/
181
182/** 32-byte instruction format.
183 *  Format of instruction for a 32-byte mode input queue.
184 */
185struct octeon_instr_32B {
186	/** Pointer where the input data is available. */
187	u64 dptr;
188
189	/** Instruction Header.  */
190	u64 ih;
191
192	/** Pointer where the response for a RAW mode packet will be written
193	 * by Octeon.
194	 */
195	u64 rptr;
196
197	/** Input Request Header. Additional info about the input. */
198	u64 irh;
199
200};
201
202#define OCT_32B_INSTR_SIZE     (sizeof(struct octeon_instr_32B))
203
204/** 64-byte instruction format.
205 *  Format of instruction for a 64-byte mode input queue.
206 */
207struct octeon_instr2_64B {
208	/** Pointer where the input data is available. */
209	u64 dptr;
210
211	/** Instruction Header. */
212	u64 ih2;
213
214	/** Input Request Header. */
215	u64 irh;
216
217	/** opcode/subcode specific parameters */
218	u64 ossp[2];
219
220	/** Return Data Parameters */
221	u64 rdp;
222
223	/** Pointer where the response for a RAW mode packet will be written
224	 * by Octeon.
225	 */
226	u64 rptr;
227
228	u64 reserved;
229};
230
231struct octeon_instr3_64B {
232	/** Pointer where the input data is available. */
233	u64 dptr;
234
235	/** Instruction Header. */
236	u64 ih3;
237
238	/** Instruction Header. */
239	u64 pki_ih3;
240
241	/** Input Request Header. */
242	u64 irh;
243
244	/** opcode/subcode specific parameters */
245	u64 ossp[2];
246
247	/** Return Data Parameters */
248	u64 rdp;
249
250	/** Pointer where the response for a RAW mode packet will be written
251	 * by Octeon.
252	 */
253	u64 rptr;
254
255};
256
257union octeon_instr_64B {
258	struct octeon_instr2_64B cmd2;
259	struct octeon_instr3_64B cmd3;
260};
261
262#define OCT_64B_INSTR_SIZE     (sizeof(union octeon_instr_64B))
263
264/** The size of each buffer in soft command buffer pool
265 */
266#define  SOFT_COMMAND_BUFFER_SIZE	2048
267
268struct octeon_soft_command {
269	/** Soft command buffer info. */
270	struct list_head node;
271	u64 dma_addr;
272	u32 size;
273
274	/** Command and return status */
275	union octeon_instr_64B cmd;
276
277#define COMPLETION_WORD_INIT    0xffffffffffffffffULL
278	u64 *status_word;
279
280	/** Data buffer info */
281	void *virtdptr;
282	u64 dmadptr;
283	u32 datasize;
284
285	/** Return buffer info */
286	void *virtrptr;
287	u64 dmarptr;
288	u32 rdatasize;
289
290	/** Context buffer info */
291	void *ctxptr;
292	u32  ctxsize;
293
294	/** Time out and callback */
295	size_t expiry_time;
296	u32 iq_no;
297	void (*callback)(struct octeon_device *, u32, void *);
298	void *callback_arg;
299
300	int caller_is_done;
301	u32 sc_status;
302	struct completion complete;
303};
304
305/* max timeout (in milli sec) for soft request */
306#define LIO_SC_MAX_TMO_MS       60000
307
308/** Maximum number of buffers to allocate into soft command buffer pool
309 */
310#define  MAX_SOFT_COMMAND_BUFFERS	256
311
312/** Head of a soft command buffer pool.
313 */
314struct octeon_sc_buffer_pool {
315	/** List structure to add delete pending entries to */
316	struct list_head head;
317
318	/** A lock for this response list */
319	spinlock_t lock;
320
321	atomic_t alloc_buf_count;
322};
323
324#define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count)  \
325		(((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count)
326
327int octeon_setup_sc_buffer_pool(struct octeon_device *oct);
328int octeon_free_sc_done_list(struct octeon_device *oct);
329int octeon_free_sc_zombie_list(struct octeon_device *oct);
330int octeon_free_sc_buffer_pool(struct octeon_device *oct);
331struct octeon_soft_command *
332	octeon_alloc_soft_command(struct octeon_device *oct,
333				  u32 datasize, u32 rdatasize,
334				  u32 ctxsize);
335void octeon_free_soft_command(struct octeon_device *oct,
336			      struct octeon_soft_command *sc);
337
338/**
339 *  octeon_init_instr_queue()
340 *  @param octeon_dev      - pointer to the octeon device structure.
341 *  @param txpciq          - queue to be initialized (0 <= q_no <= 3).
342 *
343 *  Called at driver init time for each input queue. iq_conf has the
344 *  configuration parameters for the queue.
345 *
346 *  @return  Success: 0   Failure: 1
347 */
348int octeon_init_instr_queue(struct octeon_device *octeon_dev,
349			    union oct_txpciq txpciq,
350			    u32 num_descs);
351
352/**
353 *  octeon_delete_instr_queue()
354 *  @param octeon_dev      - pointer to the octeon device structure.
355 *  @param iq_no           - queue to be deleted (0 <= q_no <= 3).
356 *
357 *  Called at driver unload time for each input queue. Deletes all
358 *  allocated resources for the input queue.
359 *
360 *  @return  Success: 0   Failure: 1
361 */
362int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);
363
364int lio_wait_for_instr_fetch(struct octeon_device *oct);
365
366void
367octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no);
368
369int
370octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
371				void (*fn)(void *));
372
373int
374lio_process_iq_request_list(struct octeon_device *oct,
375			    struct octeon_instr_queue *iq, u32 napi_budget);
376
377int octeon_send_command(struct octeon_device *oct, u32 iq_no,
378			u32 force_db, void *cmd, void *buf,
379			u32 datasize, u32 reqtype);
380
381void octeon_dump_soft_command(struct octeon_device *oct,
382			      struct octeon_soft_command *sc);
383
384void octeon_prepare_soft_command(struct octeon_device *oct,
385				 struct octeon_soft_command *sc,
386				 u8 opcode, u8 subcode,
387				 u32 irh_ossp, u64 ossp0,
388				 u64 ossp1);
389
390int octeon_send_soft_command(struct octeon_device *oct,
391			     struct octeon_soft_command *sc);
392
393int octeon_setup_iq(struct octeon_device *oct, int ifidx,
394		    int q_index, union oct_txpciq iq_no, u32 num_descs,
395		    void *app_ctx);
396int
397octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
398		u32 napi_budget);
399#endif				/* __OCTEON_IQ_H__ */
400