1/* bnx2x_sp.h: Qlogic Everest network driver. 2 * 3 * Copyright 2011-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * Unless you and Qlogic execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2, available 10 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). 11 * 12 * Notwithstanding the above, under no circumstances may you combine this 13 * software in any way with any other Qlogic software provided under a 14 * license other than the GPL, without Qlogic's express prior written 15 * consent. 16 * 17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 18 * Written by: Vladislav Zolotarov 19 * 20 */ 21#ifndef BNX2X_SP_VERBS 22#define BNX2X_SP_VERBS 23 24struct bnx2x; 25struct eth_context; 26 27/* Bits representing general command's configuration */ 28enum { 29 RAMROD_TX, 30 RAMROD_RX, 31 /* Wait until all pending commands complete */ 32 RAMROD_COMP_WAIT, 33 /* Don't send a ramrod, only update a registry */ 34 RAMROD_DRV_CLR_ONLY, 35 /* Configure HW according to the current object state */ 36 RAMROD_RESTORE, 37 /* Execute the next command now */ 38 RAMROD_EXEC, 39 /* Don't add a new command and continue execution of postponed 40 * commands. If not set a new command will be added to the 41 * pending commands list. 42 */ 43 RAMROD_CONT, 44 /* If there is another pending ramrod, wait until it finishes and 45 * re-try to submit this one. This flag can be set only in sleepable 46 * context, and should not be set from the context that completes the 47 * ramrods as deadlock will occur. 48 */ 49 RAMROD_RETRY, 50}; 51 52typedef enum { 53 BNX2X_OBJ_TYPE_RX, 54 BNX2X_OBJ_TYPE_TX, 55 BNX2X_OBJ_TYPE_RX_TX, 56} bnx2x_obj_type; 57 58/* Public slow path states */ 59enum { 60 BNX2X_FILTER_MAC_PENDING, 61 BNX2X_FILTER_VLAN_PENDING, 62 BNX2X_FILTER_VLAN_MAC_PENDING, 63 BNX2X_FILTER_RX_MODE_PENDING, 64 BNX2X_FILTER_RX_MODE_SCHED, 65 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 66 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 67 BNX2X_FILTER_FCOE_ETH_START_SCHED, 68 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 69 BNX2X_FILTER_MCAST_PENDING, 70 BNX2X_FILTER_MCAST_SCHED, 71 BNX2X_FILTER_RSS_CONF_PENDING, 72 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 73 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 74}; 75 76struct bnx2x_raw_obj { 77 u8 func_id; 78 79 /* Queue params */ 80 u8 cl_id; 81 u32 cid; 82 83 /* Ramrod data buffer params */ 84 void *rdata; 85 dma_addr_t rdata_mapping; 86 87 /* Ramrod state params */ 88 int state; /* "ramrod is pending" state bit */ 89 unsigned long *pstate; /* pointer to state buffer */ 90 91 bnx2x_obj_type obj_type; 92 93 int (*wait_comp)(struct bnx2x *bp, 94 struct bnx2x_raw_obj *o); 95 96 bool (*check_pending)(struct bnx2x_raw_obj *o); 97 void (*clear_pending)(struct bnx2x_raw_obj *o); 98 void (*set_pending)(struct bnx2x_raw_obj *o); 99}; 100 101/************************* VLAN-MAC commands related parameters ***************/ 102struct bnx2x_mac_ramrod_data { 103 u8 mac[ETH_ALEN]; 104 u8 is_inner_mac; 105}; 106 107struct bnx2x_vlan_ramrod_data { 108 u16 vlan; 109}; 110 111struct bnx2x_vlan_mac_ramrod_data { 112 u8 mac[ETH_ALEN]; 113 u8 is_inner_mac; 114 u16 vlan; 115}; 116 117union bnx2x_classification_ramrod_data { 118 struct bnx2x_mac_ramrod_data mac; 119 struct bnx2x_vlan_ramrod_data vlan; 120 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 121}; 122 123/* VLAN_MAC commands */ 124enum bnx2x_vlan_mac_cmd { 125 BNX2X_VLAN_MAC_ADD, 126 BNX2X_VLAN_MAC_DEL, 127 BNX2X_VLAN_MAC_MOVE, 128}; 129 130struct bnx2x_vlan_mac_data { 131 /* Requested command: BNX2X_VLAN_MAC_XX */ 132 enum bnx2x_vlan_mac_cmd cmd; 133 /* used to contain the data related vlan_mac_flags bits from 134 * ramrod parameters. 135 */ 136 unsigned long vlan_mac_flags; 137 138 /* Needed for MOVE command */ 139 struct bnx2x_vlan_mac_obj *target_obj; 140 141 union bnx2x_classification_ramrod_data u; 142}; 143 144/*************************** Exe Queue obj ************************************/ 145union bnx2x_exe_queue_cmd_data { 146 struct bnx2x_vlan_mac_data vlan_mac; 147 148 struct { 149 /* TODO */ 150 } mcast; 151}; 152 153struct bnx2x_exeq_elem { 154 struct list_head link; 155 156 /* Length of this element in the exe_chunk. */ 157 int cmd_len; 158 159 union bnx2x_exe_queue_cmd_data cmd_data; 160}; 161 162union bnx2x_qable_obj; 163 164union bnx2x_exeq_comp_elem { 165 union event_ring_elem *elem; 166}; 167 168struct bnx2x_exe_queue_obj; 169 170typedef int (*exe_q_validate)(struct bnx2x *bp, 171 union bnx2x_qable_obj *o, 172 struct bnx2x_exeq_elem *elem); 173 174typedef int (*exe_q_remove)(struct bnx2x *bp, 175 union bnx2x_qable_obj *o, 176 struct bnx2x_exeq_elem *elem); 177 178/* Return positive if entry was optimized, 0 - if not, negative 179 * in case of an error. 180 */ 181typedef int (*exe_q_optimize)(struct bnx2x *bp, 182 union bnx2x_qable_obj *o, 183 struct bnx2x_exeq_elem *elem); 184typedef int (*exe_q_execute)(struct bnx2x *bp, 185 union bnx2x_qable_obj *o, 186 struct list_head *exe_chunk, 187 unsigned long *ramrod_flags); 188typedef struct bnx2x_exeq_elem * 189 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 190 struct bnx2x_exeq_elem *elem); 191 192struct bnx2x_exe_queue_obj { 193 /* Commands pending for an execution. */ 194 struct list_head exe_queue; 195 196 /* Commands pending for an completion. */ 197 struct list_head pending_comp; 198 199 spinlock_t lock; 200 201 /* Maximum length of commands' list for one execution */ 202 int exe_chunk_len; 203 204 union bnx2x_qable_obj *owner; 205 206 /****** Virtual functions ******/ 207 /** 208 * Called before commands execution for commands that are really 209 * going to be executed (after 'optimize'). 210 * 211 * Must run under exe_queue->lock 212 */ 213 exe_q_validate validate; 214 215 /** 216 * Called before removing pending commands, cleaning allocated 217 * resources (e.g., credits from validate) 218 */ 219 exe_q_remove remove; 220 221 /** 222 * This will try to cancel the current pending commands list 223 * considering the new command. 224 * 225 * Returns the number of optimized commands or a negative error code 226 * 227 * Must run under exe_queue->lock 228 */ 229 exe_q_optimize optimize; 230 231 /** 232 * Run the next commands chunk (owner specific). 233 */ 234 exe_q_execute execute; 235 236 /** 237 * Return the exe_queue element containing the specific command 238 * if any. Otherwise return NULL. 239 */ 240 exe_q_get get; 241}; 242/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 243/* 244 * Element in the VLAN_MAC registry list having all currently configured 245 * rules. 246 */ 247struct bnx2x_vlan_mac_registry_elem { 248 struct list_head link; 249 250 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 251 * Relevant for 57710 and 57711 only. VLANs and MACs share the 252 * same CAM for these chips. 253 */ 254 int cam_offset; 255 256 /* Needed for DEL and RESTORE flows */ 257 unsigned long vlan_mac_flags; 258 259 union bnx2x_classification_ramrod_data u; 260}; 261 262/* Bits representing VLAN_MAC commands specific flags */ 263enum { 264 BNX2X_UC_LIST_MAC, 265 BNX2X_ETH_MAC, 266 BNX2X_ISCSI_ETH_MAC, 267 BNX2X_NETQ_ETH_MAC, 268 BNX2X_VLAN, 269 BNX2X_DONT_CONSUME_CAM_CREDIT, 270 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 271}; 272/* When looking for matching filters, some flags are not interesting */ 273#define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \ 274 1 << BNX2X_ETH_MAC | \ 275 1 << BNX2X_ISCSI_ETH_MAC | \ 276 1 << BNX2X_NETQ_ETH_MAC | \ 277 1 << BNX2X_VLAN) 278#define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \ 279 ((flags) & BNX2X_VLAN_MAC_CMP_MASK) 280 281struct bnx2x_vlan_mac_ramrod_params { 282 /* Object to run the command from */ 283 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 284 285 /* General command flags: COMP_WAIT, etc. */ 286 unsigned long ramrod_flags; 287 288 /* Command specific configuration request */ 289 struct bnx2x_vlan_mac_data user_req; 290}; 291 292struct bnx2x_vlan_mac_obj { 293 struct bnx2x_raw_obj raw; 294 295 /* Bookkeeping list: will prevent the addition of already existing 296 * entries. 297 */ 298 struct list_head head; 299 /* Implement a simple reader/writer lock on the head list. 300 * all these fields should only be accessed under the exe_queue lock 301 */ 302 u8 head_reader; /* Num. of readers accessing head list */ 303 bool head_exe_request; /* Pending execution request. */ 304 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 305 306 /* TODO: Add it's initialization in the init functions */ 307 struct bnx2x_exe_queue_obj exe_queue; 308 309 /* MACs credit pool */ 310 struct bnx2x_credit_pool_obj *macs_pool; 311 312 /* VLANs credit pool */ 313 struct bnx2x_credit_pool_obj *vlans_pool; 314 315 /* RAMROD command to be used */ 316 int ramrod_cmd; 317 318 /* copy first n elements onto preallocated buffer 319 * 320 * @param n number of elements to get 321 * @param buf buffer preallocated by caller into which elements 322 * will be copied. Note elements are 4-byte aligned 323 * so buffer size must be able to accommodate the 324 * aligned elements. 325 * 326 * @return number of copied bytes 327 */ 328 int (*get_n_elements)(struct bnx2x *bp, 329 struct bnx2x_vlan_mac_obj *o, int n, u8 *base, 330 u8 stride, u8 size); 331 332 /** 333 * Checks if ADD-ramrod with the given params may be performed. 334 * 335 * @return zero if the element may be added 336 */ 337 338 int (*check_add)(struct bnx2x *bp, 339 struct bnx2x_vlan_mac_obj *o, 340 union bnx2x_classification_ramrod_data *data); 341 342 /** 343 * Checks if DEL-ramrod with the given params may be performed. 344 * 345 * @return true if the element may be deleted 346 */ 347 struct bnx2x_vlan_mac_registry_elem * 348 (*check_del)(struct bnx2x *bp, 349 struct bnx2x_vlan_mac_obj *o, 350 union bnx2x_classification_ramrod_data *data); 351 352 /** 353 * Checks if DEL-ramrod with the given params may be performed. 354 * 355 * @return true if the element may be deleted 356 */ 357 bool (*check_move)(struct bnx2x *bp, 358 struct bnx2x_vlan_mac_obj *src_o, 359 struct bnx2x_vlan_mac_obj *dst_o, 360 union bnx2x_classification_ramrod_data *data); 361 362 /** 363 * Update the relevant credit object(s) (consume/return 364 * correspondingly). 365 */ 366 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 367 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 368 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 369 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 370 371 /** 372 * Configures one rule in the ramrod data buffer. 373 */ 374 void (*set_one_rule)(struct bnx2x *bp, 375 struct bnx2x_vlan_mac_obj *o, 376 struct bnx2x_exeq_elem *elem, int rule_idx, 377 int cam_offset); 378 379 /** 380 * Delete all configured elements having the given 381 * vlan_mac_flags specification. Assumes no pending for 382 * execution commands. Will schedule all all currently 383 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 384 * specification for deletion and will use the given 385 * ramrod_flags for the last DEL operation. 386 * 387 * @param bp 388 * @param o 389 * @param ramrod_flags RAMROD_XX flags 390 * 391 * @return 0 if the last operation has completed successfully 392 * and there are no more elements left, positive value 393 * if there are pending for completion commands, 394 * negative value in case of failure. 395 */ 396 int (*delete_all)(struct bnx2x *bp, 397 struct bnx2x_vlan_mac_obj *o, 398 unsigned long *vlan_mac_flags, 399 unsigned long *ramrod_flags); 400 401 /** 402 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 403 * configured elements list. 404 * 405 * @param bp 406 * @param p Command parameters (RAMROD_COMP_WAIT bit in 407 * ramrod_flags is only taken into an account) 408 * @param ppos a pointer to the cookie that should be given back in the 409 * next call to make function handle the next element. If 410 * *ppos is set to NULL it will restart the iterator. 411 * If returned *ppos == NULL this means that the last 412 * element has been handled. 413 * 414 * @return int 415 */ 416 int (*restore)(struct bnx2x *bp, 417 struct bnx2x_vlan_mac_ramrod_params *p, 418 struct bnx2x_vlan_mac_registry_elem **ppos); 419 420 /** 421 * Should be called on a completion arrival. 422 * 423 * @param bp 424 * @param o 425 * @param cqe Completion element we are handling 426 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 427 * pending commands will be executed. 428 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 429 * may also be set if needed. 430 * 431 * @return 0 if there are neither pending nor waiting for 432 * completion commands. Positive value if there are 433 * pending for execution or for completion commands. 434 * Negative value in case of an error (including an 435 * error in the cqe). 436 */ 437 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 438 union event_ring_elem *cqe, 439 unsigned long *ramrod_flags); 440 441 /** 442 * Wait for completion of all commands. Don't schedule new ones, 443 * just wait. It assumes that the completion code will schedule 444 * for new commands. 445 */ 446 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 447}; 448 449enum { 450 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 451 BNX2X_LLH_CAM_ETH_LINE, 452 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 453}; 454 455/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 456 457/* RX_MODE ramrod special flags: set in rx_mode_flags field in 458 * a bnx2x_rx_mode_ramrod_params. 459 */ 460enum { 461 BNX2X_RX_MODE_FCOE_ETH, 462 BNX2X_RX_MODE_ISCSI_ETH, 463}; 464 465enum { 466 BNX2X_ACCEPT_UNICAST, 467 BNX2X_ACCEPT_MULTICAST, 468 BNX2X_ACCEPT_ALL_UNICAST, 469 BNX2X_ACCEPT_ALL_MULTICAST, 470 BNX2X_ACCEPT_BROADCAST, 471 BNX2X_ACCEPT_UNMATCHED, 472 BNX2X_ACCEPT_ANY_VLAN 473}; 474 475struct bnx2x_rx_mode_ramrod_params { 476 struct bnx2x_rx_mode_obj *rx_mode_obj; 477 unsigned long *pstate; 478 int state; 479 u8 cl_id; 480 u32 cid; 481 u8 func_id; 482 unsigned long ramrod_flags; 483 unsigned long rx_mode_flags; 484 485 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 486 * a tstorm_eth_mac_filter_config (e1x). 487 */ 488 void *rdata; 489 dma_addr_t rdata_mapping; 490 491 /* Rx mode settings */ 492 unsigned long rx_accept_flags; 493 494 /* internal switching settings */ 495 unsigned long tx_accept_flags; 496}; 497 498struct bnx2x_rx_mode_obj { 499 int (*config_rx_mode)(struct bnx2x *bp, 500 struct bnx2x_rx_mode_ramrod_params *p); 501 502 int (*wait_comp)(struct bnx2x *bp, 503 struct bnx2x_rx_mode_ramrod_params *p); 504}; 505 506/********************** Set multicast group ***********************************/ 507 508struct bnx2x_mcast_list_elem { 509 struct list_head link; 510 u8 *mac; 511}; 512 513union bnx2x_mcast_config_data { 514 u8 *mac; 515 u8 bin; /* used in a RESTORE flow */ 516}; 517 518struct bnx2x_mcast_ramrod_params { 519 struct bnx2x_mcast_obj *mcast_obj; 520 521 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 522 unsigned long ramrod_flags; 523 524 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 525 /** TODO: 526 * - rename it to macs_num. 527 * - Add a new command type for handling pending commands 528 * (remove "zero semantics"). 529 * 530 * Length of mcast_list. If zero and ADD_CONT command - post 531 * pending commands. 532 */ 533 int mcast_list_len; 534}; 535 536enum bnx2x_mcast_cmd { 537 BNX2X_MCAST_CMD_ADD, 538 BNX2X_MCAST_CMD_CONT, 539 BNX2X_MCAST_CMD_DEL, 540 BNX2X_MCAST_CMD_RESTORE, 541 542 /* Following this, multicast configuration should equal to approx 543 * the set of MACs provided [i.e., remove all else]. 544 * The two sub-commands are used internally to decide whether a given 545 * bin is to be added or removed 546 */ 547 BNX2X_MCAST_CMD_SET, 548 BNX2X_MCAST_CMD_SET_ADD, 549 BNX2X_MCAST_CMD_SET_DEL, 550}; 551 552struct bnx2x_mcast_obj { 553 struct bnx2x_raw_obj raw; 554 555 union { 556 struct { 557 #define BNX2X_MCAST_BINS_NUM 256 558 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 559 u64 vec[BNX2X_MCAST_VEC_SZ]; 560 561 /** Number of BINs to clear. Should be updated 562 * immediately when a command arrives in order to 563 * properly create DEL commands. 564 */ 565 int num_bins_set; 566 } aprox_match; 567 568 struct { 569 struct list_head macs; 570 int num_macs_set; 571 } exact_match; 572 } registry; 573 574 /* Pending commands */ 575 struct list_head pending_cmds_head; 576 577 /* A state that is set in raw.pstate, when there are pending commands */ 578 int sched_state; 579 580 /* Maximal number of mcast MACs configured in one command */ 581 int max_cmd_len; 582 583 /* Total number of currently pending MACs to configure: both 584 * in the pending commands list and in the current command. 585 */ 586 int total_pending_num; 587 588 u8 engine_id; 589 590 /** 591 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 592 */ 593 int (*config_mcast)(struct bnx2x *bp, 594 struct bnx2x_mcast_ramrod_params *p, 595 enum bnx2x_mcast_cmd cmd); 596 597 /** 598 * Fills the ramrod data during the RESTORE flow. 599 * 600 * @param bp 601 * @param o 602 * @param start_idx Registry index to start from 603 * @param rdata_idx Index in the ramrod data to start from 604 * 605 * @return -1 if we handled the whole registry or index of the last 606 * handled registry element. 607 */ 608 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 609 int start_bin, int *rdata_idx); 610 611 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 612 struct bnx2x_mcast_ramrod_params *p, 613 enum bnx2x_mcast_cmd cmd); 614 615 void (*set_one_rule)(struct bnx2x *bp, 616 struct bnx2x_mcast_obj *o, int idx, 617 union bnx2x_mcast_config_data *cfg_data, 618 enum bnx2x_mcast_cmd cmd); 619 620 /** Checks if there are more mcast MACs to be set or a previous 621 * command is still pending. 622 */ 623 bool (*check_pending)(struct bnx2x_mcast_obj *o); 624 625 /** 626 * Set/Clear/Check SCHEDULED state of the object 627 */ 628 void (*set_sched)(struct bnx2x_mcast_obj *o); 629 void (*clear_sched)(struct bnx2x_mcast_obj *o); 630 bool (*check_sched)(struct bnx2x_mcast_obj *o); 631 632 /* Wait until all pending commands complete */ 633 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 634 635 /** 636 * Handle the internal object counters needed for proper 637 * commands handling. Checks that the provided parameters are 638 * feasible. 639 */ 640 int (*validate)(struct bnx2x *bp, 641 struct bnx2x_mcast_ramrod_params *p, 642 enum bnx2x_mcast_cmd cmd); 643 644 /** 645 * Restore the values of internal counters in case of a failure. 646 */ 647 void (*revert)(struct bnx2x *bp, 648 struct bnx2x_mcast_ramrod_params *p, 649 int old_num_bins, 650 enum bnx2x_mcast_cmd cmd); 651 652 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 653 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 654}; 655 656/*************************** Credit handling **********************************/ 657struct bnx2x_credit_pool_obj { 658 659 /* Current amount of credit in the pool */ 660 atomic_t credit; 661 662 /* Maximum allowed credit. put() will check against it. */ 663 int pool_sz; 664 665 /* Allocate a pool table statically. 666 * 667 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 668 * 669 * The set bit in the table will mean that the entry is available. 670 */ 671#define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 672 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 673 674 /* Base pool offset (initialized differently */ 675 int base_pool_offset; 676 677 /** 678 * Get the next free pool entry. 679 * 680 * @return true if there was a free entry in the pool 681 */ 682 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 683 684 /** 685 * Return the entry back to the pool. 686 * 687 * @return true if entry is legal and has been successfully 688 * returned to the pool. 689 */ 690 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 691 692 /** 693 * Get the requested amount of credit from the pool. 694 * 695 * @param cnt Amount of requested credit 696 * @return true if the operation is successful 697 */ 698 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 699 700 /** 701 * Returns the credit to the pool. 702 * 703 * @param cnt Amount of credit to return 704 * @return true if the operation is successful 705 */ 706 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 707 708 /** 709 * Reads the current amount of credit. 710 */ 711 int (*check)(struct bnx2x_credit_pool_obj *o); 712}; 713 714/*************************** RSS configuration ********************************/ 715enum { 716 /* RSS_MODE bits are mutually exclusive */ 717 BNX2X_RSS_MODE_DISABLED, 718 BNX2X_RSS_MODE_REGULAR, 719 720 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 721 722 BNX2X_RSS_IPV4, 723 BNX2X_RSS_IPV4_TCP, 724 BNX2X_RSS_IPV4_UDP, 725 BNX2X_RSS_IPV6, 726 BNX2X_RSS_IPV6_TCP, 727 BNX2X_RSS_IPV6_UDP, 728 729 BNX2X_RSS_IPV4_VXLAN, 730 BNX2X_RSS_IPV6_VXLAN, 731 BNX2X_RSS_TUNN_INNER_HDRS, 732}; 733 734struct bnx2x_config_rss_params { 735 struct bnx2x_rss_config_obj *rss_obj; 736 737 /* may have RAMROD_COMP_WAIT set only */ 738 unsigned long ramrod_flags; 739 740 /* BNX2X_RSS_X bits */ 741 unsigned long rss_flags; 742 743 /* Number hash bits to take into an account */ 744 u8 rss_result_mask; 745 746 /* Indirection table */ 747 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 748 749 /* RSS hash values */ 750 u32 rss_key[10]; 751 752 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 753 u16 toe_rss_bitmap; 754}; 755 756struct bnx2x_rss_config_obj { 757 struct bnx2x_raw_obj raw; 758 759 /* RSS engine to use */ 760 u8 engine_id; 761 762 /* Last configured indirection table */ 763 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 764 765 /* flags for enabling 4-tupple hash on UDP */ 766 u8 udp_rss_v4; 767 u8 udp_rss_v6; 768 769 int (*config_rss)(struct bnx2x *bp, 770 struct bnx2x_config_rss_params *p); 771}; 772 773/*********************** Queue state update ***********************************/ 774 775/* UPDATE command options */ 776enum { 777 BNX2X_Q_UPDATE_IN_VLAN_REM, 778 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 779 BNX2X_Q_UPDATE_OUT_VLAN_REM, 780 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 781 BNX2X_Q_UPDATE_ANTI_SPOOF, 782 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 783 BNX2X_Q_UPDATE_ACTIVATE, 784 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 785 BNX2X_Q_UPDATE_DEF_VLAN_EN, 786 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 787 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 788 BNX2X_Q_UPDATE_SILENT_VLAN_REM, 789 BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 790 BNX2X_Q_UPDATE_TX_SWITCHING, 791 BNX2X_Q_UPDATE_PTP_PKTS_CHNG, 792 BNX2X_Q_UPDATE_PTP_PKTS, 793}; 794 795/* Allowed Queue states */ 796enum bnx2x_q_state { 797 BNX2X_Q_STATE_RESET, 798 BNX2X_Q_STATE_INITIALIZED, 799 BNX2X_Q_STATE_ACTIVE, 800 BNX2X_Q_STATE_MULTI_COS, 801 BNX2X_Q_STATE_MCOS_TERMINATED, 802 BNX2X_Q_STATE_INACTIVE, 803 BNX2X_Q_STATE_STOPPED, 804 BNX2X_Q_STATE_TERMINATED, 805 BNX2X_Q_STATE_FLRED, 806 BNX2X_Q_STATE_MAX, 807}; 808 809/* Allowed Queue states */ 810enum bnx2x_q_logical_state { 811 BNX2X_Q_LOGICAL_STATE_ACTIVE, 812 BNX2X_Q_LOGICAL_STATE_STOPPED, 813}; 814 815/* Allowed commands */ 816enum bnx2x_queue_cmd { 817 BNX2X_Q_CMD_INIT, 818 BNX2X_Q_CMD_SETUP, 819 BNX2X_Q_CMD_SETUP_TX_ONLY, 820 BNX2X_Q_CMD_DEACTIVATE, 821 BNX2X_Q_CMD_ACTIVATE, 822 BNX2X_Q_CMD_UPDATE, 823 BNX2X_Q_CMD_UPDATE_TPA, 824 BNX2X_Q_CMD_HALT, 825 BNX2X_Q_CMD_CFC_DEL, 826 BNX2X_Q_CMD_TERMINATE, 827 BNX2X_Q_CMD_EMPTY, 828 BNX2X_Q_CMD_MAX, 829}; 830 831/* queue SETUP + INIT flags */ 832enum { 833 BNX2X_Q_FLG_TPA, 834 BNX2X_Q_FLG_TPA_IPV6, 835 BNX2X_Q_FLG_TPA_GRO, 836 BNX2X_Q_FLG_STATS, 837 BNX2X_Q_FLG_ZERO_STATS, 838 BNX2X_Q_FLG_ACTIVE, 839 BNX2X_Q_FLG_OV, 840 BNX2X_Q_FLG_VLAN, 841 BNX2X_Q_FLG_COS, 842 BNX2X_Q_FLG_HC, 843 BNX2X_Q_FLG_HC_EN, 844 BNX2X_Q_FLG_DHC, 845 BNX2X_Q_FLG_FCOE, 846 BNX2X_Q_FLG_LEADING_RSS, 847 BNX2X_Q_FLG_MCAST, 848 BNX2X_Q_FLG_DEF_VLAN, 849 BNX2X_Q_FLG_TX_SWITCH, 850 BNX2X_Q_FLG_TX_SEC, 851 BNX2X_Q_FLG_ANTI_SPOOF, 852 BNX2X_Q_FLG_SILENT_VLAN_REM, 853 BNX2X_Q_FLG_FORCE_DEFAULT_PRI, 854 BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, 855 BNX2X_Q_FLG_PCSUM_ON_PKT, 856 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID 857}; 858 859/* Queue type options: queue type may be a combination of below. */ 860enum bnx2x_q_type { 861 /** TODO: Consider moving both these flags into the init() 862 * ramrod params. 863 */ 864 BNX2X_Q_TYPE_HAS_RX, 865 BNX2X_Q_TYPE_HAS_TX, 866}; 867 868#define BNX2X_PRIMARY_CID_INDEX 0 869#define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 870#define BNX2X_MULTI_TX_COS_E2_E3A0 2 871#define BNX2X_MULTI_TX_COS_E3B0 3 872#define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 873 874#define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 875/* DMAE channel to be used by FW for timesync workaroun. A driver that sends 876 * timesync-related ramrods must not use this DMAE command ID. 877 */ 878#define FW_DMAE_CMD_ID 6 879 880struct bnx2x_queue_init_params { 881 struct { 882 unsigned long flags; 883 u16 hc_rate; 884 u8 fw_sb_id; 885 u8 sb_cq_index; 886 } tx; 887 888 struct { 889 unsigned long flags; 890 u16 hc_rate; 891 u8 fw_sb_id; 892 u8 sb_cq_index; 893 } rx; 894 895 /* CID context in the host memory */ 896 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 897 898 /* maximum number of cos supported by hardware */ 899 u8 max_cos; 900}; 901 902struct bnx2x_queue_terminate_params { 903 /* index within the tx_only cids of this queue object */ 904 u8 cid_index; 905}; 906 907struct bnx2x_queue_cfc_del_params { 908 /* index within the tx_only cids of this queue object */ 909 u8 cid_index; 910}; 911 912struct bnx2x_queue_update_params { 913 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 914 u16 def_vlan; 915 u16 silent_removal_value; 916 u16 silent_removal_mask; 917/* index within the tx_only cids of this queue object */ 918 u8 cid_index; 919}; 920 921struct bnx2x_queue_update_tpa_params { 922 dma_addr_t sge_map; 923 u8 update_ipv4; 924 u8 update_ipv6; 925 u8 max_tpa_queues; 926 u8 max_sges_pkt; 927 u8 complete_on_both_clients; 928 u8 dont_verify_thr; 929 u8 tpa_mode; 930 u8 _pad; 931 932 u16 sge_buff_sz; 933 u16 max_agg_sz; 934 935 u16 sge_pause_thr_low; 936 u16 sge_pause_thr_high; 937}; 938 939struct rxq_pause_params { 940 u16 bd_th_lo; 941 u16 bd_th_hi; 942 u16 rcq_th_lo; 943 u16 rcq_th_hi; 944 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 945 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 946 u16 pri_map; 947}; 948 949/* general */ 950struct bnx2x_general_setup_params { 951 /* valid iff BNX2X_Q_FLG_STATS */ 952 u8 stat_id; 953 954 u8 spcl_id; 955 u16 mtu; 956 u8 cos; 957 958 u8 fp_hsi; 959}; 960 961struct bnx2x_rxq_setup_params { 962 /* dma */ 963 dma_addr_t dscr_map; 964 dma_addr_t sge_map; 965 dma_addr_t rcq_map; 966 dma_addr_t rcq_np_map; 967 968 u16 drop_flags; 969 u16 buf_sz; 970 u8 fw_sb_id; 971 u8 cl_qzone_id; 972 973 /* valid iff BNX2X_Q_FLG_TPA */ 974 u16 tpa_agg_sz; 975 u16 sge_buf_sz; 976 u8 max_sges_pkt; 977 u8 max_tpa_queues; 978 u8 rss_engine_id; 979 980 /* valid iff BNX2X_Q_FLG_MCAST */ 981 u8 mcast_engine_id; 982 983 u8 cache_line_log; 984 985 u8 sb_cq_index; 986 987 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 988 u16 silent_removal_value; 989 u16 silent_removal_mask; 990}; 991 992struct bnx2x_txq_setup_params { 993 /* dma */ 994 dma_addr_t dscr_map; 995 996 u8 fw_sb_id; 997 u8 sb_cq_index; 998 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 999 u16 traffic_type; 1000 /* equals to the leading rss client id, used for TX classification*/ 1001 u8 tss_leading_cl_id; 1002 1003 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 1004 u16 default_vlan; 1005}; 1006 1007struct bnx2x_queue_setup_params { 1008 struct bnx2x_general_setup_params gen_params; 1009 struct bnx2x_txq_setup_params txq_params; 1010 struct bnx2x_rxq_setup_params rxq_params; 1011 struct rxq_pause_params pause_params; 1012 unsigned long flags; 1013}; 1014 1015struct bnx2x_queue_setup_tx_only_params { 1016 struct bnx2x_general_setup_params gen_params; 1017 struct bnx2x_txq_setup_params txq_params; 1018 unsigned long flags; 1019 /* index within the tx_only cids of this queue object */ 1020 u8 cid_index; 1021}; 1022 1023struct bnx2x_queue_state_params { 1024 struct bnx2x_queue_sp_obj *q_obj; 1025 1026 /* Current command */ 1027 enum bnx2x_queue_cmd cmd; 1028 1029 /* may have RAMROD_COMP_WAIT set only */ 1030 unsigned long ramrod_flags; 1031 1032 /* Params according to the current command */ 1033 union { 1034 struct bnx2x_queue_update_params update; 1035 struct bnx2x_queue_update_tpa_params update_tpa; 1036 struct bnx2x_queue_setup_params setup; 1037 struct bnx2x_queue_init_params init; 1038 struct bnx2x_queue_setup_tx_only_params tx_only; 1039 struct bnx2x_queue_terminate_params terminate; 1040 struct bnx2x_queue_cfc_del_params cfc_del; 1041 } params; 1042}; 1043 1044struct bnx2x_viflist_params { 1045 u8 echo_res; 1046 u8 func_bit_map_res; 1047}; 1048 1049struct bnx2x_queue_sp_obj { 1050 u32 cids[BNX2X_MULTI_TX_COS]; 1051 u8 cl_id; 1052 u8 func_id; 1053 1054 /* number of traffic classes supported by queue. 1055 * The primary connection of the queue supports the first traffic 1056 * class. Any further traffic class is supported by a tx-only 1057 * connection. 1058 * 1059 * Therefore max_cos is also a number of valid entries in the cids 1060 * array. 1061 */ 1062 u8 max_cos; 1063 u8 num_tx_only, next_tx_only; 1064 1065 enum bnx2x_q_state state, next_state; 1066 1067 /* bits from enum bnx2x_q_type */ 1068 unsigned long type; 1069 1070 /* BNX2X_Q_CMD_XX bits. This object implements "one 1071 * pending" paradigm but for debug and tracing purposes it's 1072 * more convenient to have different bits for different 1073 * commands. 1074 */ 1075 unsigned long pending; 1076 1077 /* Buffer to use as a ramrod data and its mapping */ 1078 void *rdata; 1079 dma_addr_t rdata_mapping; 1080 1081 /** 1082 * Performs one state change according to the given parameters. 1083 * 1084 * @return 0 in case of success and negative value otherwise. 1085 */ 1086 int (*send_cmd)(struct bnx2x *bp, 1087 struct bnx2x_queue_state_params *params); 1088 1089 /** 1090 * Sets the pending bit according to the requested transition. 1091 */ 1092 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1093 struct bnx2x_queue_state_params *params); 1094 1095 /** 1096 * Checks that the requested state transition is legal. 1097 */ 1098 int (*check_transition)(struct bnx2x *bp, 1099 struct bnx2x_queue_sp_obj *o, 1100 struct bnx2x_queue_state_params *params); 1101 1102 /** 1103 * Completes the pending command. 1104 */ 1105 int (*complete_cmd)(struct bnx2x *bp, 1106 struct bnx2x_queue_sp_obj *o, 1107 enum bnx2x_queue_cmd); 1108 1109 int (*wait_comp)(struct bnx2x *bp, 1110 struct bnx2x_queue_sp_obj *o, 1111 enum bnx2x_queue_cmd cmd); 1112}; 1113 1114/********************** Function state update *********************************/ 1115 1116/* UPDATE command options */ 1117enum { 1118 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 1119 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, 1120 BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, 1121 BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG, 1122 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG, 1123 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG, 1124 BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, 1125 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE, 1126 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN, 1127 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE, 1128 BNX2X_F_UPDATE_TUNNEL_INNER_RSS, 1129}; 1130 1131/* Allowed Function states */ 1132enum bnx2x_func_state { 1133 BNX2X_F_STATE_RESET, 1134 BNX2X_F_STATE_INITIALIZED, 1135 BNX2X_F_STATE_STARTED, 1136 BNX2X_F_STATE_TX_STOPPED, 1137 BNX2X_F_STATE_MAX, 1138}; 1139 1140/* Allowed Function commands */ 1141enum bnx2x_func_cmd { 1142 BNX2X_F_CMD_HW_INIT, 1143 BNX2X_F_CMD_START, 1144 BNX2X_F_CMD_STOP, 1145 BNX2X_F_CMD_HW_RESET, 1146 BNX2X_F_CMD_AFEX_UPDATE, 1147 BNX2X_F_CMD_AFEX_VIFLISTS, 1148 BNX2X_F_CMD_TX_STOP, 1149 BNX2X_F_CMD_TX_START, 1150 BNX2X_F_CMD_SWITCH_UPDATE, 1151 BNX2X_F_CMD_SET_TIMESYNC, 1152 BNX2X_F_CMD_MAX, 1153}; 1154 1155struct bnx2x_func_hw_init_params { 1156 /* A load phase returned by MCP. 1157 * 1158 * May be: 1159 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1160 * FW_MSG_CODE_DRV_LOAD_COMMON 1161 * FW_MSG_CODE_DRV_LOAD_PORT 1162 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1163 */ 1164 u32 load_phase; 1165}; 1166 1167struct bnx2x_func_hw_reset_params { 1168 /* A load phase returned by MCP. 1169 * 1170 * May be: 1171 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1172 * FW_MSG_CODE_DRV_LOAD_COMMON 1173 * FW_MSG_CODE_DRV_LOAD_PORT 1174 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1175 */ 1176 u32 reset_phase; 1177}; 1178 1179struct bnx2x_func_start_params { 1180 /* Multi Function mode: 1181 * - Single Function 1182 * - Switch Dependent 1183 * - Switch Independent 1184 */ 1185 u16 mf_mode; 1186 1187 /* Switch Dependent mode outer VLAN tag */ 1188 u16 sd_vlan_tag; 1189 1190 /* Function cos mode */ 1191 u8 network_cos_mode; 1192 1193 /* UDP dest port for VXLAN */ 1194 u16 vxlan_dst_port; 1195 1196 /* UDP dest port for Geneve */ 1197 u16 geneve_dst_port; 1198 1199 /* Enable inner Rx classifications for L2GRE packets */ 1200 u8 inner_clss_l2gre; 1201 1202 /* Enable inner Rx classifications for L2-Geneve packets */ 1203 u8 inner_clss_l2geneve; 1204 1205 /* Enable inner Rx classification for vxlan packets */ 1206 u8 inner_clss_vxlan; 1207 1208 /* Enable RSS according to inner header */ 1209 u8 inner_rss; 1210 1211 /* Allows accepting of packets failing MF classification, possibly 1212 * only matching a given ethertype 1213 */ 1214 u8 class_fail; 1215 u16 class_fail_ethtype; 1216 1217 /* Override priority of output packets */ 1218 u8 sd_vlan_force_pri; 1219 u8 sd_vlan_force_pri_val; 1220 1221 /* Replace vlan's ethertype */ 1222 u16 sd_vlan_eth_type; 1223 1224 /* Prevent inner vlans from being added by FW */ 1225 u8 no_added_tags; 1226 1227 /* Inner-to-Outer vlan priority mapping */ 1228 u8 c2s_pri[MAX_VLAN_PRIORITIES]; 1229 u8 c2s_pri_default; 1230 u8 c2s_pri_valid; 1231}; 1232 1233struct bnx2x_func_switch_update_params { 1234 unsigned long changes; /* BNX2X_F_UPDATE_XX bits */ 1235 u16 vlan; 1236 u16 vlan_eth_type; 1237 u8 vlan_force_prio; 1238 u16 vxlan_dst_port; 1239 u16 geneve_dst_port; 1240}; 1241 1242struct bnx2x_func_afex_update_params { 1243 u16 vif_id; 1244 u16 afex_default_vlan; 1245 u8 allowed_priorities; 1246}; 1247 1248struct bnx2x_func_afex_viflists_params { 1249 u16 vif_list_index; 1250 u8 func_bit_map; 1251 u8 afex_vif_list_command; 1252 u8 func_to_clear; 1253}; 1254 1255struct bnx2x_func_tx_start_params { 1256 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1257 u8 dcb_enabled; 1258 u8 dcb_version; 1259 u8 dont_add_pri_0_en; 1260 u8 dcb_outer_pri[MAX_TRAFFIC_TYPES]; 1261}; 1262 1263struct bnx2x_func_set_timesync_params { 1264 /* Reset, set or keep the current drift value */ 1265 u8 drift_adjust_cmd; 1266 1267 /* Dec, inc or keep the current offset */ 1268 u8 offset_cmd; 1269 1270 /* Drift value direction */ 1271 u8 add_sub_drift_adjust_value; 1272 1273 /* Drift, period and offset values to be used according to the commands 1274 * above. 1275 */ 1276 u8 drift_adjust_value; 1277 u32 drift_adjust_period; 1278 u64 offset_delta; 1279}; 1280 1281struct bnx2x_func_state_params { 1282 struct bnx2x_func_sp_obj *f_obj; 1283 1284 /* Current command */ 1285 enum bnx2x_func_cmd cmd; 1286 1287 /* may have RAMROD_COMP_WAIT set only */ 1288 unsigned long ramrod_flags; 1289 1290 /* Params according to the current command */ 1291 union { 1292 struct bnx2x_func_hw_init_params hw_init; 1293 struct bnx2x_func_hw_reset_params hw_reset; 1294 struct bnx2x_func_start_params start; 1295 struct bnx2x_func_switch_update_params switch_update; 1296 struct bnx2x_func_afex_update_params afex_update; 1297 struct bnx2x_func_afex_viflists_params afex_viflists; 1298 struct bnx2x_func_tx_start_params tx_start; 1299 struct bnx2x_func_set_timesync_params set_timesync; 1300 } params; 1301}; 1302 1303struct bnx2x_func_sp_drv_ops { 1304 /* Init tool + runtime initialization: 1305 * - Common Chip 1306 * - Common (per Path) 1307 * - Port 1308 * - Function phases 1309 */ 1310 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1311 int (*init_hw_cmn)(struct bnx2x *bp); 1312 int (*init_hw_port)(struct bnx2x *bp); 1313 int (*init_hw_func)(struct bnx2x *bp); 1314 1315 /* Reset Function HW: Common, Port, Function phases. */ 1316 void (*reset_hw_cmn)(struct bnx2x *bp); 1317 void (*reset_hw_port)(struct bnx2x *bp); 1318 void (*reset_hw_func)(struct bnx2x *bp); 1319 1320 /* Init/Free GUNZIP resources */ 1321 int (*gunzip_init)(struct bnx2x *bp); 1322 void (*gunzip_end)(struct bnx2x *bp); 1323 1324 /* Prepare/Release FW resources */ 1325 int (*init_fw)(struct bnx2x *bp); 1326 void (*release_fw)(struct bnx2x *bp); 1327}; 1328 1329struct bnx2x_func_sp_obj { 1330 enum bnx2x_func_state state, next_state; 1331 1332 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1333 * pending" paradigm but for debug and tracing purposes it's 1334 * more convenient to have different bits for different 1335 * commands. 1336 */ 1337 unsigned long pending; 1338 1339 /* Buffer to use as a ramrod data and its mapping */ 1340 void *rdata; 1341 dma_addr_t rdata_mapping; 1342 1343 /* Buffer to use as a afex ramrod data and its mapping. 1344 * This can't be same rdata as above because afex ramrod requests 1345 * can arrive to the object in parallel to other ramrod requests. 1346 */ 1347 void *afex_rdata; 1348 dma_addr_t afex_rdata_mapping; 1349 1350 /* this mutex validates that when pending flag is taken, the next 1351 * ramrod to be sent will be the one set the pending bit 1352 */ 1353 struct mutex one_pending_mutex; 1354 1355 /* Driver interface */ 1356 struct bnx2x_func_sp_drv_ops *drv; 1357 1358 /** 1359 * Performs one state change according to the given parameters. 1360 * 1361 * @return 0 in case of success and negative value otherwise. 1362 */ 1363 int (*send_cmd)(struct bnx2x *bp, 1364 struct bnx2x_func_state_params *params); 1365 1366 /** 1367 * Checks that the requested state transition is legal. 1368 */ 1369 int (*check_transition)(struct bnx2x *bp, 1370 struct bnx2x_func_sp_obj *o, 1371 struct bnx2x_func_state_params *params); 1372 1373 /** 1374 * Completes the pending command. 1375 */ 1376 int (*complete_cmd)(struct bnx2x *bp, 1377 struct bnx2x_func_sp_obj *o, 1378 enum bnx2x_func_cmd cmd); 1379 1380 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1381 enum bnx2x_func_cmd cmd); 1382}; 1383 1384/********************** Interfaces ********************************************/ 1385/* Queueable objects set */ 1386union bnx2x_qable_obj { 1387 struct bnx2x_vlan_mac_obj vlan_mac; 1388}; 1389/************** Function state update *********/ 1390void bnx2x_init_func_obj(struct bnx2x *bp, 1391 struct bnx2x_func_sp_obj *obj, 1392 void *rdata, dma_addr_t rdata_mapping, 1393 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1394 struct bnx2x_func_sp_drv_ops *drv_iface); 1395 1396int bnx2x_func_state_change(struct bnx2x *bp, 1397 struct bnx2x_func_state_params *params); 1398 1399enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1400 struct bnx2x_func_sp_obj *o); 1401/******************* Queue State **************/ 1402void bnx2x_init_queue_obj(struct bnx2x *bp, 1403 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1404 u8 cid_cnt, u8 func_id, void *rdata, 1405 dma_addr_t rdata_mapping, unsigned long type); 1406 1407int bnx2x_queue_state_change(struct bnx2x *bp, 1408 struct bnx2x_queue_state_params *params); 1409 1410int bnx2x_get_q_logical_state(struct bnx2x *bp, 1411 struct bnx2x_queue_sp_obj *obj); 1412 1413/********************* VLAN-MAC ****************/ 1414void bnx2x_init_mac_obj(struct bnx2x *bp, 1415 struct bnx2x_vlan_mac_obj *mac_obj, 1416 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1417 dma_addr_t rdata_mapping, int state, 1418 unsigned long *pstate, bnx2x_obj_type type, 1419 struct bnx2x_credit_pool_obj *macs_pool); 1420 1421void bnx2x_init_vlan_obj(struct bnx2x *bp, 1422 struct bnx2x_vlan_mac_obj *vlan_obj, 1423 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1424 dma_addr_t rdata_mapping, int state, 1425 unsigned long *pstate, bnx2x_obj_type type, 1426 struct bnx2x_credit_pool_obj *vlans_pool); 1427 1428void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1429 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1430 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1431 dma_addr_t rdata_mapping, int state, 1432 unsigned long *pstate, bnx2x_obj_type type, 1433 struct bnx2x_credit_pool_obj *macs_pool, 1434 struct bnx2x_credit_pool_obj *vlans_pool); 1435 1436int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp, 1437 struct bnx2x_vlan_mac_obj *o); 1438void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp, 1439 struct bnx2x_vlan_mac_obj *o); 1440int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp, 1441 struct bnx2x_vlan_mac_obj *o); 1442int bnx2x_config_vlan_mac(struct bnx2x *bp, 1443 struct bnx2x_vlan_mac_ramrod_params *p); 1444 1445int bnx2x_vlan_mac_move(struct bnx2x *bp, 1446 struct bnx2x_vlan_mac_ramrod_params *p, 1447 struct bnx2x_vlan_mac_obj *dest_o); 1448 1449/********************* RX MODE ****************/ 1450 1451void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1452 struct bnx2x_rx_mode_obj *o); 1453 1454/** 1455 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1456 * 1457 * @p: Command parameters 1458 * 1459 * Return: 0 - if operation was successful and there is no pending completions, 1460 * positive number - if there are pending completions, 1461 * negative - if there were errors 1462 */ 1463int bnx2x_config_rx_mode(struct bnx2x *bp, 1464 struct bnx2x_rx_mode_ramrod_params *p); 1465 1466/****************** MULTICASTS ****************/ 1467 1468void bnx2x_init_mcast_obj(struct bnx2x *bp, 1469 struct bnx2x_mcast_obj *mcast_obj, 1470 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1471 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1472 int state, unsigned long *pstate, 1473 bnx2x_obj_type type); 1474 1475/** 1476 * bnx2x_config_mcast - Configure multicast MACs list. 1477 * 1478 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1479 * 1480 * May configure a new list 1481 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1482 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1483 * configuration, continue to execute the pending commands 1484 * (BNX2X_MCAST_CMD_CONT). 1485 * 1486 * If previous command is still pending or if number of MACs to 1487 * configure is more that maximum number of MACs in one command, 1488 * the current command will be enqueued to the tail of the 1489 * pending commands list. 1490 * 1491 * Return: 0 is operation was successful and there are no pending completions, 1492 * negative if there were errors, positive if there are pending 1493 * completions. 1494 */ 1495int bnx2x_config_mcast(struct bnx2x *bp, 1496 struct bnx2x_mcast_ramrod_params *p, 1497 enum bnx2x_mcast_cmd cmd); 1498 1499/****************** CREDIT POOL ****************/ 1500void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1501 struct bnx2x_credit_pool_obj *p, u8 func_id, 1502 u8 func_num); 1503void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1504 struct bnx2x_credit_pool_obj *p, u8 func_id, 1505 u8 func_num); 1506void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p, 1507 int base, int credit); 1508 1509/****************** RSS CONFIGURATION ****************/ 1510void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1511 struct bnx2x_rss_config_obj *rss_obj, 1512 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1513 void *rdata, dma_addr_t rdata_mapping, 1514 int state, unsigned long *pstate, 1515 bnx2x_obj_type type); 1516 1517/** 1518 * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1519 * 1520 * Return: 0 in case of success 1521 */ 1522int bnx2x_config_rss(struct bnx2x *bp, 1523 struct bnx2x_config_rss_params *p); 1524 1525/** 1526 * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1527 * 1528 * @ind_table: buffer to fill with the current indirection 1529 * table content. Should be at least 1530 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1531 */ 1532void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1533 u8 *ind_table); 1534 1535#define PF_MAC_CREDIT_E2(bp, func_num) \ 1536 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_MAC_CREDIT_CNT) / \ 1537 func_num + GET_NUM_VFS_PER_PF(bp) * VF_MAC_CREDIT_CNT) 1538 1539#define BNX2X_VFS_VLAN_CREDIT(bp) \ 1540 (GET_NUM_VFS_PER_PATH(bp) * VF_VLAN_CREDIT_CNT) 1541 1542#define PF_VLAN_CREDIT_E2(bp, func_num) \ 1543 ((MAX_VLAN_CREDIT_E2 - 1 - BNX2X_VFS_VLAN_CREDIT(bp)) / \ 1544 func_num + GET_NUM_VFS_PER_PF(bp) * VF_VLAN_CREDIT_CNT) 1545 1546#endif /* BNX2X_SP_VERBS */ 1547