1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _BGMAC_H 3#define _BGMAC_H 4 5#include <linux/netdevice.h> 6 7#include "unimac.h" 8 9#define BGMAC_DEV_CTL 0x000 10#define BGMAC_DC_TSM 0x00000002 11#define BGMAC_DC_CFCO 0x00000004 12#define BGMAC_DC_RLSS 0x00000008 13#define BGMAC_DC_MROR 0x00000010 14#define BGMAC_DC_FCM_MASK 0x00000060 15#define BGMAC_DC_FCM_SHIFT 5 16#define BGMAC_DC_NAE 0x00000080 17#define BGMAC_DC_TF 0x00000100 18#define BGMAC_DC_RDS_MASK 0x00030000 19#define BGMAC_DC_RDS_SHIFT 16 20#define BGMAC_DC_TDS_MASK 0x000c0000 21#define BGMAC_DC_TDS_SHIFT 18 22#define BGMAC_DEV_STATUS 0x004 /* Configuration of the interface */ 23#define BGMAC_DS_RBF 0x00000001 24#define BGMAC_DS_RDF 0x00000002 25#define BGMAC_DS_RIF 0x00000004 26#define BGMAC_DS_TBF 0x00000008 27#define BGMAC_DS_TDF 0x00000010 28#define BGMAC_DS_TIF 0x00000020 29#define BGMAC_DS_PO 0x00000040 30#define BGMAC_DS_MM_MASK 0x00000300 /* Mode of the interface */ 31#define BGMAC_DS_MM_SHIFT 8 32#define BGMAC_BIST_STATUS 0x00c 33#define BGMAC_INT_STATUS 0x020 /* Interrupt status */ 34#define BGMAC_IS_MRO 0x00000001 35#define BGMAC_IS_MTO 0x00000002 36#define BGMAC_IS_TFD 0x00000004 37#define BGMAC_IS_LS 0x00000008 38#define BGMAC_IS_MDIO 0x00000010 39#define BGMAC_IS_MR 0x00000020 40#define BGMAC_IS_MT 0x00000040 41#define BGMAC_IS_TO 0x00000080 42#define BGMAC_IS_DESC_ERR 0x00000400 /* Descriptor error */ 43#define BGMAC_IS_DATA_ERR 0x00000800 /* Data error */ 44#define BGMAC_IS_DESC_PROT_ERR 0x00001000 /* Descriptor protocol error */ 45#define BGMAC_IS_RX_DESC_UNDERF 0x00002000 /* Receive descriptor underflow */ 46#define BGMAC_IS_RX_F_OVERF 0x00004000 /* Receive FIFO overflow */ 47#define BGMAC_IS_TX_F_UNDERF 0x00008000 /* Transmit FIFO underflow */ 48#define BGMAC_IS_RX 0x00010000 /* Interrupt for RX queue 0 */ 49#define BGMAC_IS_TX0 0x01000000 /* Interrupt for TX queue 0 */ 50#define BGMAC_IS_TX1 0x02000000 /* Interrupt for TX queue 1 */ 51#define BGMAC_IS_TX2 0x04000000 /* Interrupt for TX queue 2 */ 52#define BGMAC_IS_TX3 0x08000000 /* Interrupt for TX queue 3 */ 53#define BGMAC_IS_TX_MASK 0x0f000000 54#define BGMAC_IS_INTMASK 0x0f01fcff 55#define BGMAC_IS_ERRMASK 0x0000fc00 56#define BGMAC_INT_MASK 0x024 /* Interrupt mask */ 57#define BGMAC_GP_TIMER 0x028 58#define BGMAC_INT_RECV_LAZY 0x100 59#define BGMAC_IRL_TO_MASK 0x00ffffff 60#define BGMAC_IRL_FC_MASK 0xff000000 61#define BGMAC_IRL_FC_SHIFT 24 /* Shift the number of interrupts triggered per received frame */ 62#define BGMAC_FLOW_CTL_THRESH 0x104 /* Flow control thresholds */ 63#define BGMAC_WRRTHRESH 0x108 64#define BGMAC_GMAC_IDLE_CNT_THRESH 0x10c 65#define BGMAC_PHY_ACCESS 0x180 /* PHY access address */ 66#define BGMAC_PA_DATA_MASK 0x0000ffff 67#define BGMAC_PA_ADDR_MASK 0x001f0000 68#define BGMAC_PA_ADDR_SHIFT 16 69#define BGMAC_PA_REG_MASK 0x1f000000 70#define BGMAC_PA_REG_SHIFT 24 71#define BGMAC_PA_WRITE 0x20000000 72#define BGMAC_PA_START 0x40000000 73#define BGMAC_PHY_CNTL 0x188 /* PHY control address */ 74#define BGMAC_PC_EPA_MASK 0x0000001f 75#define BGMAC_PC_MCT_MASK 0x007f0000 76#define BGMAC_PC_MCT_SHIFT 16 77#define BGMAC_PC_MTE 0x00800000 78#define BGMAC_TXQ_CTL 0x18c 79#define BGMAC_TXQ_CTL_DBT_MASK 0x00000fff 80#define BGMAC_TXQ_CTL_DBT_SHIFT 0 81#define BGMAC_RXQ_CTL 0x190 82#define BGMAC_RXQ_CTL_DBT_MASK 0x00000fff 83#define BGMAC_RXQ_CTL_DBT_SHIFT 0 84#define BGMAC_RXQ_CTL_PTE 0x00001000 85#define BGMAC_RXQ_CTL_MDP_MASK 0x3f000000 86#define BGMAC_RXQ_CTL_MDP_SHIFT 24 87#define BGMAC_GPIO_SELECT 0x194 88#define BGMAC_GPIO_OUTPUT_EN 0x198 89 90/* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */ 91#define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100 92#define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000 93 94#define BGMAC_HW_WAR 0x1e4 95#define BGMAC_PWR_CTL 0x1e8 96#define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */ 97#define BGMAC_DMA_BASE1 0x240 /* Tx controller only */ 98#define BGMAC_DMA_BASE2 0x280 /* Tx controller only */ 99#define BGMAC_DMA_BASE3 0x2C0 /* Tx controller only */ 100#define BGMAC_TX_GOOD_OCTETS 0x300 101#define BGMAC_TX_GOOD_OCTETS_HIGH 0x304 102#define BGMAC_TX_GOOD_PKTS 0x308 103#define BGMAC_TX_OCTETS 0x30c 104#define BGMAC_TX_OCTETS_HIGH 0x310 105#define BGMAC_TX_PKTS 0x314 106#define BGMAC_TX_BROADCAST_PKTS 0x318 107#define BGMAC_TX_MULTICAST_PKTS 0x31c 108#define BGMAC_TX_LEN_64 0x320 109#define BGMAC_TX_LEN_65_TO_127 0x324 110#define BGMAC_TX_LEN_128_TO_255 0x328 111#define BGMAC_TX_LEN_256_TO_511 0x32c 112#define BGMAC_TX_LEN_512_TO_1023 0x330 113#define BGMAC_TX_LEN_1024_TO_1522 0x334 114#define BGMAC_TX_LEN_1523_TO_2047 0x338 115#define BGMAC_TX_LEN_2048_TO_4095 0x33c 116#define BGMAC_TX_LEN_4096_TO_8191 0x340 117#define BGMAC_TX_LEN_8192_TO_MAX 0x344 118#define BGMAC_TX_JABBER_PKTS 0x348 /* Error */ 119#define BGMAC_TX_OVERSIZE_PKTS 0x34c /* Error */ 120#define BGMAC_TX_FRAGMENT_PKTS 0x350 121#define BGMAC_TX_UNDERRUNS 0x354 /* Error */ 122#define BGMAC_TX_TOTAL_COLS 0x358 123#define BGMAC_TX_SINGLE_COLS 0x35c 124#define BGMAC_TX_MULTIPLE_COLS 0x360 125#define BGMAC_TX_EXCESSIVE_COLS 0x364 /* Error */ 126#define BGMAC_TX_LATE_COLS 0x368 /* Error */ 127#define BGMAC_TX_DEFERED 0x36c 128#define BGMAC_TX_CARRIER_LOST 0x370 129#define BGMAC_TX_PAUSE_PKTS 0x374 130#define BGMAC_TX_UNI_PKTS 0x378 131#define BGMAC_TX_Q0_PKTS 0x37c 132#define BGMAC_TX_Q0_OCTETS 0x380 133#define BGMAC_TX_Q0_OCTETS_HIGH 0x384 134#define BGMAC_TX_Q1_PKTS 0x388 135#define BGMAC_TX_Q1_OCTETS 0x38c 136#define BGMAC_TX_Q1_OCTETS_HIGH 0x390 137#define BGMAC_TX_Q2_PKTS 0x394 138#define BGMAC_TX_Q2_OCTETS 0x398 139#define BGMAC_TX_Q2_OCTETS_HIGH 0x39c 140#define BGMAC_TX_Q3_PKTS 0x3a0 141#define BGMAC_TX_Q3_OCTETS 0x3a4 142#define BGMAC_TX_Q3_OCTETS_HIGH 0x3a8 143#define BGMAC_RX_GOOD_OCTETS 0x3b0 144#define BGMAC_RX_GOOD_OCTETS_HIGH 0x3b4 145#define BGMAC_RX_GOOD_PKTS 0x3b8 146#define BGMAC_RX_OCTETS 0x3bc 147#define BGMAC_RX_OCTETS_HIGH 0x3c0 148#define BGMAC_RX_PKTS 0x3c4 149#define BGMAC_RX_BROADCAST_PKTS 0x3c8 150#define BGMAC_RX_MULTICAST_PKTS 0x3cc 151#define BGMAC_RX_LEN_64 0x3d0 152#define BGMAC_RX_LEN_65_TO_127 0x3d4 153#define BGMAC_RX_LEN_128_TO_255 0x3d8 154#define BGMAC_RX_LEN_256_TO_511 0x3dc 155#define BGMAC_RX_LEN_512_TO_1023 0x3e0 156#define BGMAC_RX_LEN_1024_TO_1522 0x3e4 157#define BGMAC_RX_LEN_1523_TO_2047 0x3e8 158#define BGMAC_RX_LEN_2048_TO_4095 0x3ec 159#define BGMAC_RX_LEN_4096_TO_8191 0x3f0 160#define BGMAC_RX_LEN_8192_TO_MAX 0x3f4 161#define BGMAC_RX_JABBER_PKTS 0x3f8 /* Error */ 162#define BGMAC_RX_OVERSIZE_PKTS 0x3fc /* Error */ 163#define BGMAC_RX_FRAGMENT_PKTS 0x400 164#define BGMAC_RX_MISSED_PKTS 0x404 /* Error */ 165#define BGMAC_RX_CRC_ALIGN_ERRS 0x408 /* Error */ 166#define BGMAC_RX_UNDERSIZE 0x40c /* Error */ 167#define BGMAC_RX_CRC_ERRS 0x410 /* Error */ 168#define BGMAC_RX_ALIGN_ERRS 0x414 /* Error */ 169#define BGMAC_RX_SYMBOL_ERRS 0x418 /* Error */ 170#define BGMAC_RX_PAUSE_PKTS 0x41c 171#define BGMAC_RX_NONPAUSE_PKTS 0x420 172#define BGMAC_RX_SACHANGES 0x424 173#define BGMAC_RX_UNI_PKTS 0x428 174#define BGMAC_UNIMAC 0x800 175 176/* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */ 177#define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */ 178#define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */ 179/* The IOCTL values appear to be different in NS, NSP, and NS2, and do not match 180 * the values directly above 181 */ 182#define BGMAC_CLK_EN BIT(0) 183#define BGMAC_RESERVED_0 BIT(1) 184#define BGMAC_SOURCE_SYNC_MODE_EN BIT(2) 185#define BGMAC_DEST_SYNC_MODE_EN BIT(3) 186#define BGMAC_TX_CLK_OUT_INVERT_EN BIT(4) 187#define BGMAC_DIRECT_GMII_MODE BIT(5) 188#define BGMAC_CLK_250_SEL BIT(6) 189#define BGMAC_AWCACHE (0xf << 7) 190#define BGMAC_RESERVED_1 (0x1f << 11) 191#define BGMAC_ARCACHE (0xf << 16) 192#define BGMAC_AWUSER (0x3f << 20) 193#define BGMAC_ARUSER (0x3f << 26) 194#define BGMAC_RESERVED BIT(31) 195 196/* BCMA GMAC core specific IO status (BCMA_IOST) flags */ 197#define BGMAC_BCMA_IOST_ATTACHED 0x00000800 198 199#define BGMAC_NUM_MIB_TX_REGS \ 200 (((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1) 201#define BGMAC_NUM_MIB_RX_REGS \ 202 (((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1) 203 204#define BGMAC_DMA_TX_CTL 0x00 205#define BGMAC_DMA_TX_ENABLE 0x00000001 206#define BGMAC_DMA_TX_SUSPEND 0x00000002 207#define BGMAC_DMA_TX_LOOPBACK 0x00000004 208#define BGMAC_DMA_TX_FLUSH 0x00000010 209#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 210#define BGMAC_DMA_TX_MR_SHIFT 6 211#define BGMAC_DMA_TX_MR_1 0 212#define BGMAC_DMA_TX_MR_2 1 213#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800 214#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000 215#define BGMAC_DMA_TX_ADDREXT_SHIFT 16 216#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */ 217#define BGMAC_DMA_TX_BL_SHIFT 18 218#define BGMAC_DMA_TX_BL_16 0 219#define BGMAC_DMA_TX_BL_32 1 220#define BGMAC_DMA_TX_BL_64 2 221#define BGMAC_DMA_TX_BL_128 3 222#define BGMAC_DMA_TX_BL_256 4 223#define BGMAC_DMA_TX_BL_512 5 224#define BGMAC_DMA_TX_BL_1024 6 225#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */ 226#define BGMAC_DMA_TX_PC_SHIFT 21 227#define BGMAC_DMA_TX_PC_0 0 228#define BGMAC_DMA_TX_PC_4 1 229#define BGMAC_DMA_TX_PC_8 2 230#define BGMAC_DMA_TX_PC_16 3 231#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */ 232#define BGMAC_DMA_TX_PT_SHIFT 24 233#define BGMAC_DMA_TX_PT_1 0 234#define BGMAC_DMA_TX_PT_2 1 235#define BGMAC_DMA_TX_PT_4 2 236#define BGMAC_DMA_TX_PT_8 3 237#define BGMAC_DMA_TX_INDEX 0x04 238#define BGMAC_DMA_TX_RINGLO 0x08 239#define BGMAC_DMA_TX_RINGHI 0x0C 240#define BGMAC_DMA_TX_STATUS 0x10 241#define BGMAC_DMA_TX_STATDPTR 0x00001FFF 242#define BGMAC_DMA_TX_STAT 0xF0000000 243#define BGMAC_DMA_TX_STAT_DISABLED 0x00000000 244#define BGMAC_DMA_TX_STAT_ACTIVE 0x10000000 245#define BGMAC_DMA_TX_STAT_IDLEWAIT 0x20000000 246#define BGMAC_DMA_TX_STAT_STOPPED 0x30000000 247#define BGMAC_DMA_TX_STAT_SUSP 0x40000000 248#define BGMAC_DMA_TX_ERROR 0x14 249#define BGMAC_DMA_TX_ERRDPTR 0x0001FFFF 250#define BGMAC_DMA_TX_ERR 0xF0000000 251#define BGMAC_DMA_TX_ERR_NOERR 0x00000000 252#define BGMAC_DMA_TX_ERR_PROT 0x10000000 253#define BGMAC_DMA_TX_ERR_UNDERRUN 0x20000000 254#define BGMAC_DMA_TX_ERR_TRANSFER 0x30000000 255#define BGMAC_DMA_TX_ERR_DESCREAD 0x40000000 256#define BGMAC_DMA_TX_ERR_CORE 0x50000000 257#define BGMAC_DMA_RX_CTL 0x20 258#define BGMAC_DMA_RX_ENABLE 0x00000001 259#define BGMAC_DMA_RX_FRAME_OFFSET_MASK 0x000000FE 260#define BGMAC_DMA_RX_FRAME_OFFSET_SHIFT 1 261#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100 262#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400 263#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800 264#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 265#define BGMAC_DMA_RX_MR_SHIFT 6 266#define BGMAC_DMA_TX_MR_1 0 267#define BGMAC_DMA_TX_MR_2 1 268#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000 269#define BGMAC_DMA_RX_ADDREXT_SHIFT 16 270#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */ 271#define BGMAC_DMA_RX_BL_SHIFT 18 272#define BGMAC_DMA_RX_BL_16 0 273#define BGMAC_DMA_RX_BL_32 1 274#define BGMAC_DMA_RX_BL_64 2 275#define BGMAC_DMA_RX_BL_128 3 276#define BGMAC_DMA_RX_BL_256 4 277#define BGMAC_DMA_RX_BL_512 5 278#define BGMAC_DMA_RX_BL_1024 6 279#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */ 280#define BGMAC_DMA_RX_PC_SHIFT 21 281#define BGMAC_DMA_RX_PC_0 0 282#define BGMAC_DMA_RX_PC_4 1 283#define BGMAC_DMA_RX_PC_8 2 284#define BGMAC_DMA_RX_PC_16 3 285#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */ 286#define BGMAC_DMA_RX_PT_SHIFT 24 287#define BGMAC_DMA_RX_PT_1 0 288#define BGMAC_DMA_RX_PT_2 1 289#define BGMAC_DMA_RX_PT_4 2 290#define BGMAC_DMA_RX_PT_8 3 291#define BGMAC_DMA_RX_INDEX 0x24 292#define BGMAC_DMA_RX_RINGLO 0x28 293#define BGMAC_DMA_RX_RINGHI 0x2C 294#define BGMAC_DMA_RX_STATUS 0x30 295#define BGMAC_DMA_RX_STATDPTR 0x00001FFF 296#define BGMAC_DMA_RX_STAT 0xF0000000 297#define BGMAC_DMA_RX_STAT_DISABLED 0x00000000 298#define BGMAC_DMA_RX_STAT_ACTIVE 0x10000000 299#define BGMAC_DMA_RX_STAT_IDLEWAIT 0x20000000 300#define BGMAC_DMA_RX_STAT_STOPPED 0x30000000 301#define BGMAC_DMA_RX_STAT_SUSP 0x40000000 302#define BGMAC_DMA_RX_ERROR 0x34 303#define BGMAC_DMA_RX_ERRDPTR 0x0001FFFF 304#define BGMAC_DMA_RX_ERR 0xF0000000 305#define BGMAC_DMA_RX_ERR_NOERR 0x00000000 306#define BGMAC_DMA_RX_ERR_PROT 0x10000000 307#define BGMAC_DMA_RX_ERR_UNDERRUN 0x20000000 308#define BGMAC_DMA_RX_ERR_TRANSFER 0x30000000 309#define BGMAC_DMA_RX_ERR_DESCREAD 0x40000000 310#define BGMAC_DMA_RX_ERR_CORE 0x50000000 311 312#define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */ 313#define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */ 314#define BGMAC_DESC_CTL0_EOF 0x40000000 /* End of frame */ 315#define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */ 316#define BGMAC_DESC_CTL1_LEN 0x00003FFF 317 318#define BGMAC_PHY_NOREGS BRCM_PSEUDO_PHY_ADDR 319#define BGMAC_PHY_MASK 0x1F 320 321#define BGMAC_MAX_TX_RINGS 4 322#define BGMAC_MAX_RX_RINGS 1 323 324#define BGMAC_TX_RING_SLOTS 128 325#define BGMAC_RX_RING_SLOTS 512 326 327#define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ 328#define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ 329#define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ 330 BGMAC_RX_FRAME_OFFSET) 331/* Jumbo frame size with FCS */ 332#define BGMAC_RX_MAX_FRAME_SIZE 9724 333#define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) 334#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ 335 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 336 337#define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ 338#define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */ 339#define BGMAC_BFL_ENETVLAN 0x0100 /* can do vlan */ 340 341#define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030 342#define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000 343#define BGMAC_CHIPCTL_1_IF_TYPE_MII 0x00000010 344#define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020 345#define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0 346#define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000 347#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040 348#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080 349#define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0 350#define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000 351 352#define BGMAC_CHIPCTL_4_IF_TYPE_MASK 0x00003000 353#define BGMAC_CHIPCTL_4_IF_TYPE_RMII 0x00000000 354#define BGMAC_CHIPCTL_4_IF_TYPE_MII 0x00001000 355#define BGMAC_CHIPCTL_4_IF_TYPE_RGMII 0x00002000 356#define BGMAC_CHIPCTL_4_SW_TYPE_MASK 0x0000C000 357#define BGMAC_CHIPCTL_4_SW_TYPE_EPHY 0x00000000 358#define BGMAC_CHIPCTL_4_SW_TYPE_EPHYMII 0x00004000 359#define BGMAC_CHIPCTL_4_SW_TYPE_EPHYRMII 0x00008000 360#define BGMAC_CHIPCTL_4_SW_TYPE_RGMII 0x0000C000 361 362#define BGMAC_CHIPCTL_7_IF_TYPE_MASK 0x000000C0 363#define BGMAC_CHIPCTL_7_IF_TYPE_RMII 0x00000000 364#define BGMAC_CHIPCTL_7_IF_TYPE_MII 0x00000040 365#define BGMAC_CHIPCTL_7_IF_TYPE_RGMII 0x00000080 366 367#define ETHER_MAX_LEN (ETH_FRAME_LEN + ETH_FCS_LEN) 368 369/* Feature Flags */ 370#define BGMAC_FEAT_TX_MASK_SETUP BIT(0) 371#define BGMAC_FEAT_RX_MASK_SETUP BIT(1) 372#define BGMAC_FEAT_IOST_ATTACHED BIT(2) 373#define BGMAC_FEAT_NO_RESET BIT(3) 374#define BGMAC_FEAT_MISC_PLL_REQ BIT(4) 375#define BGMAC_FEAT_SW_TYPE_PHY BIT(5) 376#define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6) 377#define BGMAC_FEAT_SW_TYPE_RGMII BIT(7) 378#define BGMAC_FEAT_CMN_PHY_CTL BIT(8) 379#define BGMAC_FEAT_FLW_CTRL1 BIT(9) 380#define BGMAC_FEAT_FLW_CTRL2 BIT(10) 381#define BGMAC_FEAT_SET_RXQ_CLK BIT(11) 382#define BGMAC_FEAT_CLKCTLST BIT(12) 383#define BGMAC_FEAT_NO_CLR_MIB BIT(13) 384#define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14) 385#define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15) 386#define BGMAC_FEAT_IRQ_ID_OOB_6 BIT(16) 387#define BGMAC_FEAT_CC4_IF_SW_TYPE BIT(17) 388#define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII BIT(18) 389#define BGMAC_FEAT_CC7_IF_TYPE_RGMII BIT(19) 390#define BGMAC_FEAT_IDM_MASK BIT(20) 391 392struct bgmac_slot_info { 393 union { 394 struct sk_buff *skb; 395 void *buf; 396 }; 397 dma_addr_t dma_addr; 398}; 399 400struct bgmac_dma_desc { 401 __le32 ctl0; 402 __le32 ctl1; 403 __le32 addr_low; 404 __le32 addr_high; 405} __packed; 406 407enum bgmac_dma_ring_type { 408 BGMAC_DMA_RING_TX, 409 BGMAC_DMA_RING_RX, 410}; 411 412/** 413 * bgmac_dma_ring - contains info about DMA ring (either TX or RX one) 414 * @start: index of the first slot containing data 415 * @end: index of a slot that can *not* be read (yet) 416 * 417 * Be really aware of the specific @end meaning. It's an index of a slot *after* 418 * the one containing data that can be read. If @start equals @end the ring is 419 * empty. 420 */ 421struct bgmac_dma_ring { 422 u32 start; 423 u32 end; 424 425 struct bgmac_dma_desc *cpu_base; 426 dma_addr_t dma_base; 427 u32 index_base; /* Used for unaligned rings only, otherwise 0 */ 428 u16 mmio_base; 429 bool unaligned; 430 431 struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS]; 432}; 433 434struct bgmac_rx_header { 435 __le16 len; 436 __le16 flags; 437 __le16 pad[12]; 438}; 439 440struct bgmac { 441 union { 442 struct { 443 void __iomem *base; 444 void __iomem *idm_base; 445 void __iomem *nicpm_base; 446 } plat; 447 struct { 448 struct bcma_device *core; 449 /* Reference to CMN core for BCM4706 */ 450 struct bcma_device *cmn; 451 } bcma; 452 }; 453 454 struct device *dev; 455 struct device *dma_dev; 456 u32 feature_flags; 457 458 struct net_device *net_dev; 459 struct napi_struct napi; 460 struct mii_bus *mii_bus; 461 462 /* DMA */ 463 struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS]; 464 struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS]; 465 466 /* Stats */ 467 bool stats_grabbed; 468 u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS]; 469 u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS]; 470 471 /* Int */ 472 int irq; 473 u32 int_mask; 474 475 bool in_init; 476 477 /* Current MAC state */ 478 int mac_speed; 479 int mac_duplex; 480 481 u8 phyaddr; 482 bool has_robosw; 483 484 bool loopback; 485 486 u32 (*read)(struct bgmac *bgmac, u16 offset); 487 void (*write)(struct bgmac *bgmac, u16 offset, u32 value); 488 u32 (*idm_read)(struct bgmac *bgmac, u16 offset); 489 void (*idm_write)(struct bgmac *bgmac, u16 offset, u32 value); 490 bool (*clk_enabled)(struct bgmac *bgmac); 491 void (*clk_enable)(struct bgmac *bgmac, u32 flags); 492 void (*cco_ctl_maskset)(struct bgmac *bgmac, u32 offset, u32 mask, 493 u32 set); 494 u32 (*get_bus_clock)(struct bgmac *bgmac); 495 void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask, 496 u32 set); 497 int (*phy_connect)(struct bgmac *bgmac); 498}; 499 500struct bgmac *bgmac_alloc(struct device *dev); 501int bgmac_enet_probe(struct bgmac *bgmac); 502void bgmac_enet_remove(struct bgmac *bgmac); 503void bgmac_adjust_link(struct net_device *net_dev); 504int bgmac_phy_connect_direct(struct bgmac *bgmac); 505int bgmac_enet_suspend(struct bgmac *bgmac); 506int bgmac_enet_resume(struct bgmac *bgmac); 507 508struct mii_bus *bcma_mdio_mii_register(struct bgmac *bgmac); 509void bcma_mdio_mii_unregister(struct mii_bus *mii_bus); 510 511static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) 512{ 513 return bgmac->read(bgmac, offset); 514} 515 516static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value) 517{ 518 bgmac->write(bgmac, offset, value); 519} 520 521static inline u32 bgmac_umac_read(struct bgmac *bgmac, u16 offset) 522{ 523 return bgmac_read(bgmac, BGMAC_UNIMAC + offset); 524} 525 526static inline void bgmac_umac_write(struct bgmac *bgmac, u16 offset, u32 value) 527{ 528 bgmac_write(bgmac, BGMAC_UNIMAC + offset, value); 529} 530 531static inline u32 bgmac_idm_read(struct bgmac *bgmac, u16 offset) 532{ 533 return bgmac->idm_read(bgmac, offset); 534} 535 536static inline void bgmac_idm_write(struct bgmac *bgmac, u16 offset, u32 value) 537{ 538 bgmac->idm_write(bgmac, offset, value); 539} 540 541static inline bool bgmac_clk_enabled(struct bgmac *bgmac) 542{ 543 return bgmac->clk_enabled(bgmac); 544} 545 546static inline void bgmac_clk_enable(struct bgmac *bgmac, u32 flags) 547{ 548 bgmac->clk_enable(bgmac, flags); 549} 550 551static inline void bgmac_cco_ctl_maskset(struct bgmac *bgmac, u32 offset, 552 u32 mask, u32 set) 553{ 554 bgmac->cco_ctl_maskset(bgmac, offset, mask, set); 555} 556 557static inline u32 bgmac_get_bus_clock(struct bgmac *bgmac) 558{ 559 return bgmac->get_bus_clock(bgmac); 560} 561 562static inline void bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset, 563 u32 mask, u32 set) 564{ 565 bgmac->cmn_maskset32(bgmac, offset, mask, set); 566} 567 568static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask, 569 u32 set) 570{ 571 bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set); 572} 573 574static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask) 575{ 576 bgmac_maskset(bgmac, offset, mask, 0); 577} 578 579static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set) 580{ 581 bgmac_maskset(bgmac, offset, ~0, set); 582} 583 584static inline void bgmac_umac_maskset(struct bgmac *bgmac, u16 offset, u32 mask, u32 set) 585{ 586 bgmac_maskset(bgmac, BGMAC_UNIMAC + offset, mask, set); 587} 588 589static inline int bgmac_phy_connect(struct bgmac *bgmac) 590{ 591 return bgmac->phy_connect(bgmac); 592} 593#endif /* _BGMAC_H */ 594