1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. 4 * 5 * Derived from Intel e1000 driver 6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 7 */ 8 9#ifndef _ATL1C_H_ 10#define _ATL1C_H_ 11 12#include <linux/interrupt.h> 13#include <linux/types.h> 14#include <linux/errno.h> 15#include <linux/module.h> 16#include <linux/pci.h> 17#include <linux/netdevice.h> 18#include <linux/etherdevice.h> 19#include <linux/skbuff.h> 20#include <linux/ioport.h> 21#include <linux/slab.h> 22#include <linux/list.h> 23#include <linux/delay.h> 24#include <linux/sched.h> 25#include <linux/in.h> 26#include <linux/ip.h> 27#include <linux/ipv6.h> 28#include <linux/udp.h> 29#include <linux/mii.h> 30#include <linux/io.h> 31#include <linux/vmalloc.h> 32#include <linux/pagemap.h> 33#include <linux/tcp.h> 34#include <linux/ethtool.h> 35#include <linux/if_vlan.h> 36#include <linux/workqueue.h> 37#include <net/checksum.h> 38#include <net/ip6_checksum.h> 39 40#include "atl1c_hw.h" 41 42/* Wake Up Filter Control */ 43#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 44#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 45#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 46#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ 47#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 48 49#define AT_VLAN_TO_TAG(_vlan, _tag) \ 50 _tag = ((((_vlan) >> 8) & 0xFF) |\ 51 (((_vlan) & 0xFF) << 8)) 52 53#define AT_TAG_TO_VLAN(_tag, _vlan) \ 54 _vlan = ((((_tag) >> 8) & 0xFF) |\ 55 (((_tag) & 0xFF) << 8)) 56 57#define SPEED_0 0xffff 58#define HALF_DUPLEX 1 59#define FULL_DUPLEX 2 60 61#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN) 62#define MAX_JUMBO_FRAME_SIZE (6*1024) 63 64#define AT_MAX_RECEIVE_QUEUE 4 65#define AT_DEF_RECEIVE_QUEUE 1 66#define AT_MAX_TRANSMIT_QUEUE 4 67 68#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL 69#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL 70 71#define AT_TX_WATCHDOG (5 * HZ) 72#define AT_MAX_INT_WORK 5 73#define AT_TWSI_EEPROM_TIMEOUT 100 74#define AT_HW_MAX_IDLE_DELAY 10 75#define AT_SUSPEND_LINK_TIMEOUT 100 76 77#define AT_ASPM_L0S_TIMER 6 78#define AT_ASPM_L1_TIMER 12 79#define AT_LCKDET_TIMER 12 80 81#define ATL1C_PCIE_L0S_L1_DISABLE 0x01 82#define ATL1C_PCIE_PHY_RESET 0x02 83 84#define ATL1C_ASPM_L0s_ENABLE 0x0001 85#define ATL1C_ASPM_L1_ENABLE 0x0002 86 87#define AT_REGS_LEN (74 * sizeof(u32)) 88#define AT_EEPROM_LEN 512 89 90#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) 91#define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc) 92#define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc) 93#define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status) 94 95/* tpd word 1 bit 0:7 General Checksum task offload */ 96#define TPD_L4HDR_OFFSET_MASK 0x00FF 97#define TPD_L4HDR_OFFSET_SHIFT 0 98 99/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */ 100#define TPD_TCPHDR_OFFSET_MASK 0x00FF 101#define TPD_TCPHDR_OFFSET_SHIFT 0 102 103/* tpd word 1 bit 0:7 Custom Checksum task offload */ 104#define TPD_PLOADOFFSET_MASK 0x00FF 105#define TPD_PLOADOFFSET_SHIFT 0 106 107/* tpd word 1 bit 8:17 */ 108#define TPD_CCSUM_EN_MASK 0x0001 109#define TPD_CCSUM_EN_SHIFT 8 110#define TPD_IP_CSUM_MASK 0x0001 111#define TPD_IP_CSUM_SHIFT 9 112#define TPD_TCP_CSUM_MASK 0x0001 113#define TPD_TCP_CSUM_SHIFT 10 114#define TPD_UDP_CSUM_MASK 0x0001 115#define TPD_UDP_CSUM_SHIFT 11 116#define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */ 117#define TPD_LSO_EN_SHIFT 12 118#define TPD_LSO_VER_MASK 0x0001 119#define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */ 120#define TPD_CON_VTAG_MASK 0x0001 121#define TPD_CON_VTAG_SHIFT 14 122#define TPD_INS_VTAG_MASK 0x0001 123#define TPD_INS_VTAG_SHIFT 15 124#define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */ 125#define TPD_IPV4_PACKET_SHIFT 16 126#define TPD_ETH_TYPE_MASK 0x0001 127#define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */ 128 129/* tpd word 18:25 Custom Checksum task offload */ 130#define TPD_CCSUM_OFFSET_MASK 0x00FF 131#define TPD_CCSUM_OFFSET_SHIFT 18 132#define TPD_CCSUM_EPAD_MASK 0x0001 133#define TPD_CCSUM_EPAD_SHIFT 30 134 135/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */ 136#define TPD_MSS_MASK 0x1FFF 137#define TPD_MSS_SHIFT 18 138 139#define TPD_EOP_MASK 0x0001 140#define TPD_EOP_SHIFT 31 141 142struct atl1c_tpd_desc { 143 __le16 buffer_len; /* include 4-byte CRC */ 144 __le16 vlan_tag; 145 __le32 word1; 146 __le64 buffer_addr; 147}; 148 149struct atl1c_tpd_ext_desc { 150 u32 reservd_0; 151 __le32 word1; 152 __le32 pkt_len; 153 u32 reservd_1; 154}; 155/* rrs word 0 bit 0:31 */ 156#define RRS_RX_CSUM_MASK 0xFFFF 157#define RRS_RX_CSUM_SHIFT 0 158#define RRS_RX_RFD_CNT_MASK 0x000F 159#define RRS_RX_RFD_CNT_SHIFT 16 160#define RRS_RX_RFD_INDEX_MASK 0x0FFF 161#define RRS_RX_RFD_INDEX_SHIFT 20 162 163/* rrs flag bit 0:16 */ 164#define RRS_HEAD_LEN_MASK 0x00FF 165#define RRS_HEAD_LEN_SHIFT 0 166#define RRS_HDS_TYPE_MASK 0x0003 167#define RRS_HDS_TYPE_SHIFT 8 168#define RRS_CPU_NUM_MASK 0x0003 169#define RRS_CPU_NUM_SHIFT 10 170#define RRS_HASH_FLG_MASK 0x000F 171#define RRS_HASH_FLG_SHIFT 12 172 173#define RRS_HDS_TYPE_HEAD 1 174#define RRS_HDS_TYPE_DATA 2 175 176#define RRS_IS_NO_HDS_TYPE(flag) \ 177 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0) 178 179#define RRS_IS_HDS_HEAD(flag) \ 180 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \ 181 RRS_HDS_TYPE_HEAD) 182 183#define RRS_IS_HDS_DATA(flag) \ 184 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \ 185 RRS_HDS_TYPE_DATA) 186 187/* rrs word 3 bit 0:31 */ 188#define RRS_PKT_SIZE_MASK 0x3FFF 189#define RRS_PKT_SIZE_SHIFT 0 190#define RRS_ERR_L4_CSUM_MASK 0x0001 191#define RRS_ERR_L4_CSUM_SHIFT 14 192#define RRS_ERR_IP_CSUM_MASK 0x0001 193#define RRS_ERR_IP_CSUM_SHIFT 15 194#define RRS_VLAN_INS_MASK 0x0001 195#define RRS_VLAN_INS_SHIFT 16 196#define RRS_PROT_ID_MASK 0x0007 197#define RRS_PROT_ID_SHIFT 17 198#define RRS_RX_ERR_SUM_MASK 0x0001 199#define RRS_RX_ERR_SUM_SHIFT 20 200#define RRS_RX_ERR_CRC_MASK 0x0001 201#define RRS_RX_ERR_CRC_SHIFT 21 202#define RRS_RX_ERR_FAE_MASK 0x0001 203#define RRS_RX_ERR_FAE_SHIFT 22 204#define RRS_RX_ERR_TRUNC_MASK 0x0001 205#define RRS_RX_ERR_TRUNC_SHIFT 23 206#define RRS_RX_ERR_RUNC_MASK 0x0001 207#define RRS_RX_ERR_RUNC_SHIFT 24 208#define RRS_RX_ERR_ICMP_MASK 0x0001 209#define RRS_RX_ERR_ICMP_SHIFT 25 210#define RRS_PACKET_BCAST_MASK 0x0001 211#define RRS_PACKET_BCAST_SHIFT 26 212#define RRS_PACKET_MCAST_MASK 0x0001 213#define RRS_PACKET_MCAST_SHIFT 27 214#define RRS_PACKET_TYPE_MASK 0x0001 215#define RRS_PACKET_TYPE_SHIFT 28 216#define RRS_FIFO_FULL_MASK 0x0001 217#define RRS_FIFO_FULL_SHIFT 29 218#define RRS_802_3_LEN_ERR_MASK 0x0001 219#define RRS_802_3_LEN_ERR_SHIFT 30 220#define RRS_RXD_UPDATED_MASK 0x0001 221#define RRS_RXD_UPDATED_SHIFT 31 222 223#define RRS_ERR_L4_CSUM 0x00004000 224#define RRS_ERR_IP_CSUM 0x00008000 225#define RRS_VLAN_INS 0x00010000 226#define RRS_RX_ERR_SUM 0x00100000 227#define RRS_RX_ERR_CRC 0x00200000 228#define RRS_802_3_LEN_ERR 0x40000000 229#define RRS_RXD_UPDATED 0x80000000 230 231#define RRS_PACKET_TYPE_802_3 1 232#define RRS_PACKET_TYPE_ETH 0 233#define RRS_PACKET_IS_ETH(word) \ 234 ((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \ 235 RRS_PACKET_TYPE_ETH) 236#define RRS_RXD_IS_VALID(word) \ 237 ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1) 238 239#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \ 240 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1) 241#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \ 242 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6) 243 244#define RRS_MT_PROT_ID_TCPUDP BIT(19) 245 246struct atl1c_recv_ret_status { 247 __le32 word0; 248 __le32 rss_hash; 249 __le16 vlan_tag; 250 __le16 flag; 251 __le32 word3; 252}; 253 254/* RFD descriptor */ 255struct atl1c_rx_free_desc { 256 __le64 buffer_addr; 257}; 258 259/* DMA Order Settings */ 260enum atl1c_dma_order { 261 atl1c_dma_ord_in = 1, 262 atl1c_dma_ord_enh = 2, 263 atl1c_dma_ord_out = 4 264}; 265 266enum atl1c_dma_rcb { 267 atl1c_rcb_64 = 0, 268 atl1c_rcb_128 = 1 269}; 270 271enum atl1c_mac_speed { 272 atl1c_mac_speed_0 = 0, 273 atl1c_mac_speed_10_100 = 1, 274 atl1c_mac_speed_1000 = 2 275}; 276 277enum atl1c_dma_req_block { 278 atl1c_dma_req_128 = 0, 279 atl1c_dma_req_256 = 1, 280 atl1c_dma_req_512 = 2, 281 atl1c_dma_req_1024 = 3, 282 atl1c_dma_req_2048 = 4, 283 atl1c_dma_req_4096 = 5 284}; 285 286 287enum atl1c_nic_type { 288 athr_l1c = 0, 289 athr_l2c = 1, 290 athr_l2c_b, 291 athr_l2c_b2, 292 athr_l1d, 293 athr_l1d_2, 294 athr_mt, 295}; 296 297struct atl1c_hw_stats { 298 /* rx */ 299 unsigned long rx_ok; /* The number of good packet received. */ 300 unsigned long rx_bcast; /* The number of good broadcast packet received. */ 301 unsigned long rx_mcast; /* The number of good multicast packet received. */ 302 unsigned long rx_pause; /* The number of Pause packet received. */ 303 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */ 304 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */ 305 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */ 306 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */ 307 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */ 308 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */ 309 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */ 310 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */ 311 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */ 312 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */ 313 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */ 314 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */ 315 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */ 316 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */ 317 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */ 318 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */ 319 unsigned long rx_align_err; /* Alignment Error */ 320 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */ 321 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */ 322 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */ 323 324 /* tx */ 325 unsigned long tx_ok; /* The number of good packet transmitted. */ 326 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */ 327 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */ 328 unsigned long tx_pause; /* The number of Pause packet transmitted. */ 329 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */ 330 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ 331 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */ 332 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */ 333 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */ 334 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */ 335 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */ 336 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */ 337 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */ 338 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */ 339 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */ 340 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */ 341 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */ 342 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */ 343 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */ 344 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */ 345 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */ 346 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */ 347 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */ 348 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */ 349 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */ 350}; 351 352struct atl1c_hw { 353 u8 __iomem *hw_addr; /* inner register address */ 354 struct atl1c_adapter *adapter; 355 enum atl1c_nic_type nic_type; 356 enum atl1c_dma_order dma_order; 357 enum atl1c_dma_rcb rcb_value; 358 enum atl1c_dma_req_block dmar_block; 359 360 u16 device_id; 361 u16 vendor_id; 362 u16 subsystem_id; 363 u16 subsystem_vendor_id; 364 u8 revision_id; 365 u16 phy_id1; 366 u16 phy_id2; 367 368 spinlock_t intr_mask_lock; /* protect the intr_mask */ 369 u32 intr_mask; 370 371 u8 preamble_len; 372 u16 max_frame_size; 373 u16 min_frame_size; 374 375 enum atl1c_mac_speed mac_speed; 376 bool mac_duplex; 377 bool hibernate; 378 u16 media_type; 379#define MEDIA_TYPE_AUTO_SENSOR 0 380#define MEDIA_TYPE_100M_FULL 1 381#define MEDIA_TYPE_100M_HALF 2 382#define MEDIA_TYPE_10M_FULL 3 383#define MEDIA_TYPE_10M_HALF 4 384 385 u16 autoneg_advertised; 386 u16 mii_autoneg_adv_reg; 387 u16 mii_1000t_ctrl_reg; 388 389 u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */ 390 u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */ 391 u16 ict; /* Interrupt Clear timer (2us resolution) */ 392 u16 ctrl_flags; 393#define ATL1C_INTR_CLEAR_ON_READ 0x0001 394#define ATL1C_INTR_MODRT_ENABLE 0x0002 395#define ATL1C_CMB_ENABLE 0x0004 396#define ATL1C_SMB_ENABLE 0x0010 397#define ATL1C_TXQ_MODE_ENHANCE 0x0020 398#define ATL1C_RX_IPV6_CHKSUM 0x0040 399#define ATL1C_ASPM_L0S_SUPPORT 0x0080 400#define ATL1C_ASPM_L1_SUPPORT 0x0100 401#define ATL1C_ASPM_CTRL_MON 0x0200 402#define ATL1C_HIB_DISABLE 0x0400 403#define ATL1C_APS_MODE_ENABLE 0x0800 404#define ATL1C_LINK_EXT_SYNC 0x1000 405#define ATL1C_CLK_GATING_EN 0x2000 406#define ATL1C_FPGA_VERSION 0x8000 407 u16 link_cap_flags; 408#define ATL1C_LINK_CAP_1000M 0x0001 409 u32 smb_timer; 410 411 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger 412 interrupt request */ 413 u16 tpd_thresh; 414 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */ 415 u8 rfd_burst; 416 u32 base_cpu; 417 u32 indirect_tab; 418 u8 mac_addr[ETH_ALEN]; 419 u8 perm_mac_addr[ETH_ALEN]; 420 421 bool phy_configured; 422 bool re_autoneg; 423 bool emi_ca; 424 bool msi_lnkpatch; /* link patch for specific platforms */ 425}; 426 427/* 428 * atl1c_ring_header represents a single, contiguous block of DMA space 429 * mapped for the three descriptor rings (tpd, rfd, rrd) described below 430 */ 431struct atl1c_ring_header { 432 void *desc; /* virtual address */ 433 dma_addr_t dma; /* physical address*/ 434 unsigned int size; /* length in bytes */ 435}; 436 437/* 438 * atl1c_buffer is wrapper around a pointer to a socket buffer 439 * so a DMA handle can be stored along with the skb 440 */ 441struct atl1c_buffer { 442 struct sk_buff *skb; /* socket buffer */ 443 u16 length; /* rx buffer length */ 444 u16 flags; /* information of buffer */ 445#define ATL1C_BUFFER_FREE 0x0001 446#define ATL1C_BUFFER_BUSY 0x0002 447#define ATL1C_BUFFER_STATE_MASK 0x0003 448 449#define ATL1C_PCIMAP_SINGLE 0x0004 450#define ATL1C_PCIMAP_PAGE 0x0008 451#define ATL1C_PCIMAP_TYPE_MASK 0x000C 452 453#define ATL1C_PCIMAP_TODEVICE 0x0010 454#define ATL1C_PCIMAP_FROMDEVICE 0x0020 455#define ATL1C_PCIMAP_DIRECTION_MASK 0x0030 456 dma_addr_t dma; 457}; 458 459#define ATL1C_SET_BUFFER_STATE(buff, state) do { \ 460 ((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK; \ 461 ((buff)->flags) |= (state); \ 462 } while (0) 463 464#define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do { \ 465 ((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK; \ 466 ((buff)->flags) |= (type); \ 467 ((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK; \ 468 ((buff)->flags) |= (direction); \ 469 } while (0) 470 471/* transimit packet descriptor (tpd) ring */ 472struct atl1c_tpd_ring { 473 struct atl1c_adapter *adapter; 474 void *desc; /* descriptor ring virtual address */ 475 dma_addr_t dma; /* descriptor ring physical address */ 476 u16 num; 477 u16 size; /* descriptor ring length in bytes */ 478 u16 count; /* number of descriptors in the ring */ 479 u16 next_to_use; 480 atomic_t next_to_clean; 481 struct atl1c_buffer *buffer_info; 482 struct napi_struct napi; 483}; 484 485/* receive free descriptor (rfd) ring */ 486struct atl1c_rfd_ring { 487 void *desc; /* descriptor ring virtual address */ 488 dma_addr_t dma; /* descriptor ring physical address */ 489 u16 size; /* descriptor ring length in bytes */ 490 u16 count; /* number of descriptors in the ring */ 491 u16 next_to_use; 492 u16 next_to_clean; 493 struct atl1c_buffer *buffer_info; 494}; 495 496/* receive return descriptor (rrd) ring */ 497struct atl1c_rrd_ring { 498 struct atl1c_adapter *adapter; 499 void *desc; /* descriptor ring virtual address */ 500 dma_addr_t dma; /* descriptor ring physical address */ 501 u16 num; 502 u16 size; /* descriptor ring length in bytes */ 503 u16 count; /* number of descriptors in the ring */ 504 u16 next_to_use; 505 u16 next_to_clean; 506 struct napi_struct napi; 507}; 508 509/* board specific private data structure */ 510struct atl1c_adapter { 511 struct net_device *netdev; 512 struct pci_dev *pdev; 513 struct atl1c_hw hw; 514 struct atl1c_hw_stats hw_stats; 515 struct mii_if_info mii; /* MII interface info */ 516 u16 rx_buffer_len; 517 unsigned int tx_queue_count; 518 unsigned int rx_queue_count; 519 520 unsigned long flags; 521#define __AT_TESTING 0x0001 522#define __AT_RESETTING 0x0002 523#define __AT_DOWN 0x0003 524 unsigned long work_event; 525#define ATL1C_WORK_EVENT_RESET 0 526#define ATL1C_WORK_EVENT_LINK_CHANGE 1 527 u32 msg_enable; 528 529 bool have_msi; 530 u32 wol; 531 u16 link_speed; 532 u16 link_duplex; 533 534 spinlock_t mdio_lock; 535 atomic_t irq_sem; 536 537 struct work_struct common_task; 538 struct timer_list watchdog_timer; 539 struct timer_list phy_config_timer; 540 541 /* All Descriptor memory */ 542 struct atl1c_ring_header ring_header; 543 struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE]; 544 struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE]; 545 struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE]; 546 u32 bd_number; /* board number;*/ 547}; 548 549#define AT_WRITE_REG(a, reg, value) ( \ 550 writel((value), ((a)->hw_addr + reg))) 551 552#define AT_WRITE_FLUSH(a) (\ 553 readl((a)->hw_addr)) 554 555#define AT_READ_REG(a, reg, pdata) do { \ 556 if (unlikely((a)->hibernate)) { \ 557 readl((a)->hw_addr + reg); \ 558 *(u32 *)pdata = readl((a)->hw_addr + reg); \ 559 } else { \ 560 *(u32 *)pdata = readl((a)->hw_addr + reg); \ 561 } \ 562 } while (0) 563 564#define AT_WRITE_REGB(a, reg, value) (\ 565 writeb((value), ((a)->hw_addr + reg))) 566 567#define AT_READ_REGB(a, reg) (\ 568 readb((a)->hw_addr + reg)) 569 570#define AT_WRITE_REGW(a, reg, value) (\ 571 writew((value), ((a)->hw_addr + reg))) 572 573#define AT_READ_REGW(a, reg, pdata) do { \ 574 if (unlikely((a)->hibernate)) { \ 575 readw((a)->hw_addr + reg); \ 576 *(u16 *)pdata = readw((a)->hw_addr + reg); \ 577 } else { \ 578 *(u16 *)pdata = readw((a)->hw_addr + reg); \ 579 } \ 580 } while (0) 581 582#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 583 writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) 584 585#define AT_READ_REG_ARRAY(a, reg, offset) ( \ 586 readl(((a)->hw_addr + reg) + ((offset) << 2))) 587 588extern char atl1c_driver_name[]; 589 590void atl1c_reinit_locked(struct atl1c_adapter *adapter); 591s32 atl1c_reset_hw(struct atl1c_hw *hw); 592void atl1c_set_ethtool_ops(struct net_device *netdev); 593#endif /* _ATL1C_H_ */ 594