1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2023 Advanced Micro Devices, Inc */
3
4#ifndef _PDSC_H_
5#define _PDSC_H_
6
7#include <linux/debugfs.h>
8#include <net/devlink.h>
9
10#include <linux/pds/pds_common.h>
11#include <linux/pds/pds_core_if.h>
12#include <linux/pds/pds_adminq.h>
13#include <linux/pds/pds_intr.h>
14
15#define PDSC_DRV_DESCRIPTION	"AMD/Pensando Core Driver"
16
17#define PDSC_WATCHDOG_SECS	5
18#define PDSC_QUEUE_NAME_MAX_SZ  16
19#define PDSC_ADMINQ_MIN_LENGTH	16	/* must be a power of two */
20#define PDSC_NOTIFYQ_LENGTH	64	/* must be a power of two */
21#define PDSC_TEARDOWN_RECOVERY	false
22#define PDSC_TEARDOWN_REMOVING	true
23#define PDSC_SETUP_RECOVERY	false
24#define PDSC_SETUP_INIT		true
25
26struct pdsc_dev_bar {
27	void __iomem *vaddr;
28	phys_addr_t bus_addr;
29	unsigned long len;
30	int res_index;
31};
32
33struct pdsc;
34
35struct pdsc_vf {
36	struct pds_auxiliary_dev *padev;
37	struct pdsc *vf;
38	u16     index;
39	__le16  vif_types[PDS_DEV_TYPE_MAX];
40};
41
42struct pdsc_devinfo {
43	u8 asic_type;
44	u8 asic_rev;
45	char fw_version[PDS_CORE_DEVINFO_FWVERS_BUFLEN + 1];
46	char serial_num[PDS_CORE_DEVINFO_SERIAL_BUFLEN + 1];
47};
48
49struct pdsc_queue {
50	struct pdsc_q_info *info;
51	u64 dbval;
52	u16 head_idx;
53	u16 tail_idx;
54	u8 hw_type;
55	unsigned int index;
56	unsigned int num_descs;
57	u64 dbell_count;
58	u64 features;
59	unsigned int type;
60	unsigned int hw_index;
61	union {
62		void *base;
63		struct pds_core_admin_cmd *adminq;
64	};
65	dma_addr_t base_pa;	/* must be page aligned */
66	unsigned int desc_size;
67	unsigned int pid;
68	char name[PDSC_QUEUE_NAME_MAX_SZ];
69};
70
71#define PDSC_INTR_NAME_MAX_SZ		32
72
73struct pdsc_intr_info {
74	char name[PDSC_INTR_NAME_MAX_SZ];
75	unsigned int index;
76	unsigned int vector;
77	void *data;
78};
79
80struct pdsc_cq_info {
81	void *comp;
82};
83
84struct pdsc_buf_info {
85	struct page *page;
86	dma_addr_t dma_addr;
87	u32 page_offset;
88	u32 len;
89};
90
91struct pdsc_q_info {
92	union {
93		void *desc;
94		struct pdsc_admin_cmd *adminq_desc;
95	};
96	unsigned int bytes;
97	unsigned int nbufs;
98	struct pdsc_buf_info bufs[PDS_CORE_MAX_FRAGS];
99	struct pdsc_wait_context *wc;
100	void *dest;
101};
102
103struct pdsc_cq {
104	struct pdsc_cq_info *info;
105	struct pdsc_queue *bound_q;
106	struct pdsc_intr_info *bound_intr;
107	u16 tail_idx;
108	bool done_color;
109	unsigned int num_descs;
110	unsigned int desc_size;
111	void *base;
112	dma_addr_t base_pa;	/* must be page aligned */
113} ____cacheline_aligned_in_smp;
114
115struct pdsc_qcq {
116	struct pdsc *pdsc;
117	void *q_base;
118	dma_addr_t q_base_pa;	/* might not be page aligned */
119	void *cq_base;
120	dma_addr_t cq_base_pa;	/* might not be page aligned */
121	u32 q_size;
122	u32 cq_size;
123	bool armed;
124	unsigned int flags;
125
126	struct work_struct work;
127	struct pdsc_queue q;
128	struct pdsc_cq cq;
129	int intx;
130
131	u32 accum_work;
132	struct dentry *dentry;
133};
134
135struct pdsc_viftype {
136	char *name;
137	bool supported;
138	bool enabled;
139	int dl_id;
140	int vif_id;
141	struct pds_auxiliary_dev *padev;
142};
143
144/* No state flags set means we are in a steady running state */
145enum pdsc_state_flags {
146	PDSC_S_FW_DEAD,		    /* stopped, wait on startup or recovery */
147	PDSC_S_INITING_DRIVER,	    /* initial startup from probe */
148	PDSC_S_STOPPING_DRIVER,	    /* driver remove */
149
150	/* leave this as last */
151	PDSC_S_STATE_SIZE
152};
153
154struct pdsc {
155	struct pci_dev *pdev;
156	struct dentry *dentry;
157	struct device *dev;
158	struct pdsc_dev_bar bars[PDS_CORE_BARS_MAX];
159	struct pdsc_vf *vfs;
160	int num_vfs;
161	int vf_id;
162	int hw_index;
163	int uid;
164
165	unsigned long state;
166	u8 fw_status;
167	u8 fw_generation;
168	unsigned long last_fw_time;
169	u32 last_hb;
170	struct timer_list wdtimer;
171	unsigned int wdtimer_period;
172	struct work_struct health_work;
173	struct devlink_health_reporter *fw_reporter;
174	u32 fw_recoveries;
175
176	struct pdsc_devinfo dev_info;
177	struct pds_core_dev_identity dev_ident;
178	unsigned int nintrs;
179	struct pdsc_intr_info *intr_info;	/* array of nintrs elements */
180
181	struct workqueue_struct *wq;
182
183	unsigned int devcmd_timeout;
184	struct mutex devcmd_lock;	/* lock for dev_cmd operations */
185	struct mutex config_lock;	/* lock for configuration operations */
186	spinlock_t adminq_lock;		/* lock for adminq operations */
187	refcount_t adminq_refcnt;
188	struct pds_core_dev_info_regs __iomem *info_regs;
189	struct pds_core_dev_cmd_regs __iomem *cmd_regs;
190	struct pds_core_intr __iomem *intr_ctrl;
191	u64 __iomem *intr_status;
192	u64 __iomem *db_pages;
193	dma_addr_t phy_db_pages;
194	u64 __iomem *kern_dbpage;
195
196	struct pdsc_qcq adminqcq;
197	struct pdsc_qcq notifyqcq;
198	u64 last_eid;
199	struct pdsc_viftype *viftype_status;
200	struct work_struct pci_reset_work;
201};
202
203/** enum pds_core_dbell_bits - bitwise composition of dbell values.
204 *
205 * @PDS_CORE_DBELL_QID_MASK:	unshifted mask of valid queue id bits.
206 * @PDS_CORE_DBELL_QID_SHIFT:	queue id shift amount in dbell value.
207 * @PDS_CORE_DBELL_QID:		macro to build QID component of dbell value.
208 *
209 * @PDS_CORE_DBELL_RING_MASK:	unshifted mask of valid ring bits.
210 * @PDS_CORE_DBELL_RING_SHIFT:	ring shift amount in dbell value.
211 * @PDS_CORE_DBELL_RING:	macro to build ring component of dbell value.
212 *
213 * @PDS_CORE_DBELL_RING_0:	ring zero dbell component value.
214 * @PDS_CORE_DBELL_RING_1:	ring one dbell component value.
215 * @PDS_CORE_DBELL_RING_2:	ring two dbell component value.
216 * @PDS_CORE_DBELL_RING_3:	ring three dbell component value.
217 *
218 * @PDS_CORE_DBELL_INDEX_MASK:	bit mask of valid index bits, no shift needed.
219 */
220enum pds_core_dbell_bits {
221	PDS_CORE_DBELL_QID_MASK		= 0xffffff,
222	PDS_CORE_DBELL_QID_SHIFT		= 24,
223
224#define PDS_CORE_DBELL_QID(n) \
225	(((u64)(n) & PDS_CORE_DBELL_QID_MASK) << PDS_CORE_DBELL_QID_SHIFT)
226
227	PDS_CORE_DBELL_RING_MASK		= 0x7,
228	PDS_CORE_DBELL_RING_SHIFT		= 16,
229
230#define PDS_CORE_DBELL_RING(n) \
231	(((u64)(n) & PDS_CORE_DBELL_RING_MASK) << PDS_CORE_DBELL_RING_SHIFT)
232
233	PDS_CORE_DBELL_RING_0		= 0,
234	PDS_CORE_DBELL_RING_1		= PDS_CORE_DBELL_RING(1),
235	PDS_CORE_DBELL_RING_2		= PDS_CORE_DBELL_RING(2),
236	PDS_CORE_DBELL_RING_3		= PDS_CORE_DBELL_RING(3),
237
238	PDS_CORE_DBELL_INDEX_MASK		= 0xffff,
239};
240
241static inline void pds_core_dbell_ring(u64 __iomem *db_page,
242				       enum pds_core_logical_qtype qtype,
243				       u64 val)
244{
245	writeq(val, &db_page[qtype]);
246}
247
248int pdsc_fw_reporter_diagnose(struct devlink_health_reporter *reporter,
249			      struct devlink_fmsg *fmsg,
250			      struct netlink_ext_ack *extack);
251int pdsc_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
252		     struct netlink_ext_ack *extack);
253int pdsc_dl_flash_update(struct devlink *dl,
254			 struct devlink_flash_update_params *params,
255			 struct netlink_ext_ack *extack);
256int pdsc_dl_enable_get(struct devlink *dl, u32 id,
257		       struct devlink_param_gset_ctx *ctx);
258int pdsc_dl_enable_set(struct devlink *dl, u32 id,
259		       struct devlink_param_gset_ctx *ctx);
260int pdsc_dl_enable_validate(struct devlink *dl, u32 id,
261			    union devlink_param_value val,
262			    struct netlink_ext_ack *extack);
263
264void __iomem *pdsc_map_dbpage(struct pdsc *pdsc, int page_num);
265
266void pdsc_debugfs_create(void);
267void pdsc_debugfs_destroy(void);
268void pdsc_debugfs_add_dev(struct pdsc *pdsc);
269void pdsc_debugfs_del_dev(struct pdsc *pdsc);
270void pdsc_debugfs_add_ident(struct pdsc *pdsc);
271void pdsc_debugfs_add_viftype(struct pdsc *pdsc);
272void pdsc_debugfs_add_irqs(struct pdsc *pdsc);
273void pdsc_debugfs_add_qcq(struct pdsc *pdsc, struct pdsc_qcq *qcq);
274void pdsc_debugfs_del_qcq(struct pdsc_qcq *qcq);
275
276int pdsc_err_to_errno(enum pds_core_status_code code);
277bool pdsc_is_fw_running(struct pdsc *pdsc);
278bool pdsc_is_fw_good(struct pdsc *pdsc);
279int pdsc_devcmd(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
280		union pds_core_dev_comp *comp, int max_seconds);
281int pdsc_devcmd_locked(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
282		       union pds_core_dev_comp *comp, int max_seconds);
283int pdsc_devcmd_init(struct pdsc *pdsc);
284int pdsc_devcmd_reset(struct pdsc *pdsc);
285int pdsc_dev_init(struct pdsc *pdsc);
286void pdsc_dev_uninit(struct pdsc *pdsc);
287
288int pdsc_intr_alloc(struct pdsc *pdsc, char *name,
289		    irq_handler_t handler, void *data);
290void pdsc_intr_free(struct pdsc *pdsc, int index);
291void pdsc_qcq_free(struct pdsc *pdsc, struct pdsc_qcq *qcq);
292int pdsc_qcq_alloc(struct pdsc *pdsc, unsigned int type, unsigned int index,
293		   const char *name, unsigned int flags, unsigned int num_descs,
294		   unsigned int desc_size, unsigned int cq_desc_size,
295		   unsigned int pid, struct pdsc_qcq *qcq);
296int pdsc_setup(struct pdsc *pdsc, bool init);
297void pdsc_teardown(struct pdsc *pdsc, bool removing);
298int pdsc_start(struct pdsc *pdsc);
299void pdsc_stop(struct pdsc *pdsc);
300void pdsc_health_thread(struct work_struct *work);
301
302int pdsc_register_notify(struct notifier_block *nb);
303void pdsc_unregister_notify(struct notifier_block *nb);
304void pdsc_notify(unsigned long event, void *data);
305int pdsc_auxbus_dev_add(struct pdsc *cf, struct pdsc *pf);
306int pdsc_auxbus_dev_del(struct pdsc *cf, struct pdsc *pf);
307
308void pdsc_process_adminq(struct pdsc_qcq *qcq);
309void pdsc_work_thread(struct work_struct *work);
310irqreturn_t pdsc_adminq_isr(int irq, void *data);
311
312int pdsc_firmware_update(struct pdsc *pdsc, const struct firmware *fw,
313			 struct netlink_ext_ack *extack);
314
315void pdsc_fw_down(struct pdsc *pdsc);
316void pdsc_fw_up(struct pdsc *pdsc);
317void pdsc_pci_reset_thread(struct work_struct *work);
318
319#endif /* _PDSC_H_ */
320