1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Altera TSE SGDMA and MSGDMA Linux driver
3 * Copyright (C) 2014 Altera Corporation. All rights reserved
4 */
5
6#ifndef __ALTERA_SGDMAHW_H__
7#define __ALTERA_SGDMAHW_H__
8
9/* SGDMA descriptor structure */
10struct sgdma_descrip {
11	u32	raddr; /* address of data to be read */
12	u32	pad1;
13	u32	waddr;
14	u32	pad2;
15	u32	next;
16	u32	pad3;
17	u16	bytes;
18	u8	rburst;
19	u8	wburst;
20	u16	bytes_xferred;	/* 16 bits, bytes xferred */
21
22	/* bit 0: error
23	 * bit 1: length error
24	 * bit 2: crc error
25	 * bit 3: truncated error
26	 * bit 4: phy error
27	 * bit 5: collision error
28	 * bit 6: reserved
29	 * bit 7: status eop for recv case
30	 */
31	u8	status;
32
33	/* bit 0: eop
34	 * bit 1: read_fixed
35	 * bit 2: write fixed
36	 * bits 3,4,5,6: Channel (always 0)
37	 * bit 7: hardware owned
38	 */
39	u8	control;
40} __packed;
41
42#define SGDMA_DESC_LEN	sizeof(struct sgdma_descrip)
43
44#define SGDMA_STATUS_ERR		BIT(0)
45#define SGDMA_STATUS_LENGTH_ERR		BIT(1)
46#define SGDMA_STATUS_CRC_ERR		BIT(2)
47#define SGDMA_STATUS_TRUNC_ERR		BIT(3)
48#define SGDMA_STATUS_PHY_ERR		BIT(4)
49#define SGDMA_STATUS_COLL_ERR		BIT(5)
50#define SGDMA_STATUS_EOP		BIT(7)
51
52#define SGDMA_CONTROL_EOP		BIT(0)
53#define SGDMA_CONTROL_RD_FIXED		BIT(1)
54#define SGDMA_CONTROL_WR_FIXED		BIT(2)
55
56/* Channel is always 0, so just zero initialize it */
57
58#define SGDMA_CONTROL_HW_OWNED		BIT(7)
59
60/* SGDMA register space */
61struct sgdma_csr {
62	/* bit 0: error
63	 * bit 1: eop
64	 * bit 2: descriptor completed
65	 * bit 3: chain completed
66	 * bit 4: busy
67	 * remainder reserved
68	 */
69	u32	status;
70	u32	pad1[3];
71
72	/* bit 0: interrupt on error
73	 * bit 1: interrupt on eop
74	 * bit 2: interrupt after every descriptor
75	 * bit 3: interrupt after last descrip in a chain
76	 * bit 4: global interrupt enable
77	 * bit 5: starts descriptor processing
78	 * bit 6: stop core on dma error
79	 * bit 7: interrupt on max descriptors
80	 * bits 8-15: max descriptors to generate interrupt
81	 * bit 16: Software reset
82	 * bit 17: clears owned by hardware if 0, does not clear otherwise
83	 * bit 18: enables descriptor polling mode
84	 * bit 19-26: clocks before polling again
85	 * bit 27-30: reserved
86	 * bit 31: clear interrupt
87	 */
88	u32	control;
89	u32	pad2[3];
90	u32	next_descrip;
91	u32	pad3[3];
92};
93
94#define sgdma_csroffs(a) (offsetof(struct sgdma_csr, a))
95#define sgdma_descroffs(a) (offsetof(struct sgdma_descrip, a))
96
97#define SGDMA_STSREG_ERR	BIT(0) /* Error */
98#define SGDMA_STSREG_EOP	BIT(1) /* EOP */
99#define SGDMA_STSREG_DESCRIP	BIT(2) /* Descriptor completed */
100#define SGDMA_STSREG_CHAIN	BIT(3) /* Chain completed */
101#define SGDMA_STSREG_BUSY	BIT(4) /* Controller busy */
102
103#define SGDMA_CTRLREG_IOE	BIT(0) /* Interrupt on error */
104#define SGDMA_CTRLREG_IOEOP	BIT(1) /* Interrupt on EOP */
105#define SGDMA_CTRLREG_IDESCRIP	BIT(2) /* Interrupt after every descriptor */
106#define SGDMA_CTRLREG_ILASTD	BIT(3) /* Interrupt after last descriptor */
107#define SGDMA_CTRLREG_INTEN	BIT(4) /* Global Interrupt enable */
108#define SGDMA_CTRLREG_START	BIT(5) /* starts descriptor processing */
109#define SGDMA_CTRLREG_STOPERR	BIT(6) /* stop on dma error */
110#define SGDMA_CTRLREG_INTMAX	BIT(7) /* Interrupt on max descriptors */
111#define SGDMA_CTRLREG_RESET	BIT(16)/* Software reset */
112#define SGDMA_CTRLREG_COBHW	BIT(17)/* Clears owned by hardware */
113#define SGDMA_CTRLREG_POLL	BIT(18)/* enables descriptor polling mode */
114#define SGDMA_CTRLREG_CLRINT	BIT(31)/* Clears interrupt */
115
116#endif /* __ALTERA_SGDMAHW_H__ */
117