1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx System Management Interface (SMI) support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
8 */
9
10#ifndef _MV88E6XXX_SMI_H
11#define _MV88E6XXX_SMI_H
12
13#include "chip.h"
14
15/* Offset 0x00: SMI Command Register */
16#define MV88E6XXX_SMI_CMD			0x00
17#define MV88E6XXX_SMI_CMD_BUSY			0x8000
18#define MV88E6XXX_SMI_CMD_MODE_MASK		0x1000
19#define MV88E6XXX_SMI_CMD_MODE_45		0x0000
20#define MV88E6XXX_SMI_CMD_MODE_22		0x1000
21#define MV88E6XXX_SMI_CMD_OP_MASK		0x0c00
22#define MV88E6XXX_SMI_CMD_OP_22_WRITE		0x0400
23#define MV88E6XXX_SMI_CMD_OP_22_READ		0x0800
24#define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR	0x0000
25#define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA	0x0400
26#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA	0x0800
27#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC	0x0c00
28#define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK		0x003e
29#define MV88E6XXX_SMI_CMD_REG_ADDR_MASK		0x001f
30
31/* Offset 0x01: SMI Data Register */
32#define MV88E6XXX_SMI_DATA			0x01
33
34int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
35		       struct mii_bus *bus, int sw_addr);
36
37static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
38				     int dev, int reg, u16 *data)
39{
40	if (chip->smi_ops && chip->smi_ops->read)
41		return chip->smi_ops->read(chip, dev, reg, data);
42
43	return -EOPNOTSUPP;
44}
45
46static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
47				      int dev, int reg, u16 data)
48{
49	if (chip->smi_ops && chip->smi_ops->write)
50		return chip->smi_ops->write(chip, dev, reg, data);
51
52	return -EOPNOTSUPP;
53}
54
55#endif /* _MV88E6XXX_SMI_H */
56